The Aarch64 gdbstub code is guarded by checks on ARM_FEATURE_AARCH64
and isar_feature_aa64_sve(), only enabled for Aarch64 CPUs.
Remove TARGET_AARCH64 #ifdef'ry and build gdbstub64.c once.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
target/arm/internals.h | 2 +-
target/arm/gdbstub.c | 4 ----
target/arm/meson.build | 2 +-
3 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5e549b95e14..5fd2631e8e2 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1682,7 +1682,6 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1);
}
-#ifdef TARGET_AARCH64
GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
@@ -1692,6 +1691,7 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray
*buf, int reg);
int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg);
+#ifdef TARGET_AARCH64
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 30068c22627..e76142e8ddb 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -482,10 +482,8 @@ void arm_cpu_register_gdb_commands(ARMCPU *cpu)
g_autoptr(GString) qsupported_features = g_string_new(NULL);
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- #ifdef TARGET_AARCH64
aarch64_cpu_register_gdb_commands(cpu, qsupported_features,
query_table,
set_table);
- #endif
}
/* Set arch-specific handlers for 'q' commands. */
@@ -514,7 +512,6 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
* The lower part of each SVE register aliases to the FPU
* registers so we don't need to include both.
*/
-#ifdef TARGET_AARCH64
if (isar_feature_aa64_sve(&cpu->isar)) {
GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs,
cs->gdb_num_regs);
gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
@@ -546,7 +543,6 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
gdb_find_static_feature("aarch64-mte.xml"),
0);
}
-#endif
#endif
} else {
if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 3065081d241..503d106b588 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -3,6 +3,7 @@ arm_ss.add(files(
'cpu.c',
'debug_helper.c',
'gdbstub.c',
+ 'gdbstub64.c',
'helper.c',
'vfp_fpscr.c',
))
@@ -13,7 +14,6 @@ arm_ss.add(when: 'CONFIG_HVF', if_true:
files('hyp_gdbstub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'cpu64.c',
- 'gdbstub64.c',
))
arm_system_ss = ss.source_set()
--
2.47.1
