RITE meesage that
* follows).
*/
-static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
+static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim)
{
struct brw_compile *p = &c->func;
Looks like you double-edited this hunk. "brw_ff_gs_ff&quo
Patches 2-4 are
Reviewed-by: Chad Versace
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doing the renaming.
I'll plan on changing the name to brw_state_state[_base] tomorrow morning
unless I hear objections.
I also don't like vec4 in the name.
With the new name brw_{stage,shader}_state[_base], patch 5 is
Reviewed-by: Chad Versace
I prefer brw_stage_state without _base. I
Patches 6-7 are
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the name of a URB message (see Graphics BSpec:
3D-Media-GPGPU Engine > Shared Functions > URB > URB Messages [DevSNB] >
FF_SYNC Messages). It's a rather unfortunate coincidence that makes the
name look like a mistake :(
Doh. Ok.
Fix that, and patch 1 is
Reviewed-by: Chad Versac
On 08/26/2013 03:12 PM, Paul Berry wrote:
+ /* VS always requires at least 32 URB entries */
Haswell GT2 and GT3 require at least 64 URB entries.
+ unsigned vs_chunks =
+ ALIGN(32 * vs_entry_size_bytes, chunk_size_bytes) / chunk_size_bytes;
+ unsigned vs_wants =
+ ALIGN(brw->
---
4 files changed, 13 insertions(+), 4 deletions(-)
Reviewed-by: Chad Versace
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ING_SLOT_PSIZ).
+*/
+ slots_valid &= ~VARYING_BIT_LAYER;
+
/* Make sure that the values we store in vue_map->varying_to_slot and
* vue_map->slot_to_varying won't overflow the signed chars that are used
* to store them. Note that since vue_map->slot_to_varying someti
Whoops...
Series is
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d pbuffers.
Kristian
(CC'ing Ian to alert him about the EGLConfig sort order.)
This series looks good to me.
Reviewed-by: Chad Versace
Something to note is that eglChooseConfig(r=8, g=8, b=8) sorts the
RGBA1010102 EGLConfigs *before* the RGBA configs. I confirmed
this on GBM. The EG
Patches 1-3 are
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I like this patch. It removes a lot of boilerplate. And, it makes object
destruction easier to reason about, making it easier to reason about tricky
destruction bugs.
On 09/17/2013 11:59 AM, Paul Berry wrote:
On 15 September 2013 00:10, Francisco Jerez wrote:
This patch introduces a pair of h
On 09/17/2013 04:20 PM, Kristian Høgsberg wrote:
On Tue, Sep 17, 2013 at 1:49 PM, Chad Versace
wrote:
On 09/15/2013 12:16 AM, Kristian Høgsberg wrote:
Hi,
This little series adds support for creating EGLSurfaces with color
buffers
using the ARGB2101010 pixel format. We the new KMS addFB2
had to cc:)
The parts removed from Android.gen.mk were using generate_builtins.py,
which was also removed; that will trigger a compile failure.
This patch looks correct to me, though I didn't test it.
Reviewed-by: Chad Versace
I'll commit it now.
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ast two change rzalloc to ralloc. I assume that's a copy-paste error.
Other than that, patches 1-3 are
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On 09/18/2013 02:57 PM, Kenneth Graunke wrote:
On 09/15/2013 12:10 AM, Francisco Jerez wrote:
This patch introduces a pair of helper functions providing a common
implementation of the "new" and "delete" operators for all C++ classes
that are allocated by ralloc via placement new. The 'ralloc_ne
On 07/22/2013 03:54 PM, Frank Henigman wrote:> Extend the fast texture upload
from BGRA X-tiled to include RGBA,
> Alpha/Luminance, and Y-tiled. Speed improvements, measured with
> mesa demos teximage program, on 256 x 256 texture, in MB/s, on a
> Sandy Bridge (Ivy is comparable):
>
>
On 09/25/2013 10:40 AM, Paul Berry wrote:
On 25 September 2013 10:18, Chad Versace mailto:chad.vers...@linux.intel.com>> wrote:
On 07/22/2013 03:54 PM, Frank Henigman wrote:> Extend the fast texture
upload from BGRA X-tiled to include RGBA,
> diff --git a/src/mesa/driv
ation. Following a "simple" formula in the bspec was all you
needed to satisfy the requirement.
To prepare the code for this, extract all places where the miptree was
used, when we really only needed the region. This allows an upcoming
patch to simply allocate the region, and not the whole
On 09/26/2013 10:37 AM, Chad Versace wrote:
On 09/22/2013 10:37 AM, Ben Widawsky wrote:
Starting with Ivybridge, the hierarchical had relaxed requirements for
^^^
"the hierarchical" doesn't make sense. Just call it "the HiZ buffer
, which is fine; I just wanted
to explain the motivation.
CC: Chad Versace
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 149 +++---
1 file changed, 133 insertions(+), 16 deletions(-)
Thanks, committed.
On 02/11/2013 10:42 PM, Tapani Pälli wrote:
> From: bma
>
> Detect a duplicate Shader type as and error instead of silently allowing
> it, restrict to ES2 API.
>
> v2: Tapani Pälli
> - make the check run time instead of compile time
>
> Signed-off-by: bma
> Signed-off-
> Signed-off-by: Tapani Pälli
This patch looks good to me.
Reviewed-by: Chad Versace
Before committing, I'll wait a bit to give others a chance to review.
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On 02/13/2013 02:25 PM, Chad Versace wrote:
> On 02/13/2013 04:38 AM, Tapani Pälli wrote:
>> This patch implements a stub for GL_EXT_discard_framebuffer with
>> required checks listed by the extension specification. This extension
>> is required by GLBenchmark 2.5 when compil
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I'm seeking feedback on an EGL extension that I'm drafting. The ideas have
already been discussed at Khronos meetings to a good reception, but I want
feedback from Mesa developers too.
Summary
- ---
The extension, tentatively named EGL_EXT_platfor
e GL_STENCIL_ATTACHMENT:
>> + if (_mesa_is_winsys_fbo(fb))
>> +goto invalid_enum;
>> + break;
>> + default:
>> + goto invalid_enum;
>> + }
>> + }
>> +
>> + if (ctx->Driver.DiscardFramebuffer)
>> +
On 02/20/2013 05:44 PM, Eric Anholt wrote:
> Chad Versace writes:
>
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA1
>>
>> I'm seeking feedback on an EGL extension that I'm drafting. The ideas have
>> already been discussed at Khronos meetings to
ugs.freedesktop.org/show_bug.cgi?id=59495
Looks good to me. Please add a tag for bugzilla in the commit message.
Reviewed-by: Chad Versace
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On 02/24/2013 11:46 PM, Pekka Paalanen wrote:> On Tue, 19 Feb 2013 08:20:51
-0800
> Chad Versace wrote:
>
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA1
>>
>> I'm seeking feedback on an EGL extension that I'm drafting. The ideas have
>> alr
/es: NULL check in EGLImageTargetTexture2DOES
>
> src/mesa/main/teximage.c | 6 ++
> src/mesa/main/texparam.c | 6 ++
> 2 files changed, 12 insertions(+)
>
Reviewed-by: Chad Versace
Patches are now committed. Thanks.
Also, for small fixes like this please add one of the
NT_TYPE that apps can use to get
> this. I'm surprised that there isn't already a choice for
> EGL_TRANSPARENT_ALPHA.
>
> Signed-off-by: Ian Romanick
> Tested-by: Tian Ye
> Cc: Kristian Høgsberg
> Cc: Chad Versace
> Bugzilla: https://bugs.freedesktop.org/show_bu
On 02/25/2013 04:22 PM, Chad Versace wrote:
> Two nits.
>
> On 02/25/2013 10:51 AM, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> Previously only the 32-bit X visual would match the 32-bit RGBA
>> configs. This resulted in every config with alpha getting
On 02/25/2013 11:58 PM, Pekka Paalanen wrote:
> On Mon, 25 Feb 2013 09:09:22 -0800
> Chad Versace wrote:
> Thank you for the reply. Indeed, that dance to check for the extension
> is non-trivial, and I think it might be good to explain somehow in the
> spec, maybe in the Q&A
On 02/26/2013 06:23 AM, Jakob Bornecrantz wrote:
> [SNIP]
>
>>> Hi,
>>>
>>> is it possible to build a binary, that will use this extension if it is
>>> present in whatever libEGL is available at runtime, and if it is not,
>>> fall back gracefully to using the core eglGetDisplay()?
>>>
>>> Or is th
On 02/26/2013 11:15 PM, Eric Anholt wrote:
> I have some debug of HiZ rendering that looks like some rendering is not
> landing in my HiZ buffer. Unfortunately, fulsim choking on us violating
> hiz rendering rules was preventing me from using it as a debug aid.
>
> Once we get things reliable, we
mesa/drivers/dri/i965/gen6_blorp.cpp
> index 3834ae2..2b6db82 100644
Patch 2 is
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to copy the stencil data over, too. We could have skipped
> +* passing BRW_MAP_NO_TRANSCODE_BIT, but that would have meant
^
The name needs an update. Other than that, patches 3 and 4 are
Reviewed-by: Chad Versace
> @@ -752,25 +827,9 @@ intel_miptree_copy_slice(s
On 02/27/2013 11:39 AM, Eric Anholt wrote:
> Chad Versace writes:
>
>> On 02/26/2013 11:15 PM, Eric Anholt wrote:
>>> I have some debug of HiZ rendering that looks like some rendering is not
>>> landing in my HiZ buffer. Unfortunately, fulsim choking on us violati
From: Brian Paul
No longer pass -a flag to get_hash_generate.py script to specify
OpenGL, ES1, ES2, etc.
v2[chadv]: Fix Android makefile too.
---
Brian, this patch in your series breaks the Android build. Here is
a fixed version of your patch. The only difference is the hunk in
file Android.gen
The field was equivalent to (etc_format != MESA_FORMAT_NONE), and
therefore duplicate information.
This patch removes field and replaces all references to it with
`etc_format != MESA_FORMAT_NONE`.
No Piglit ETC test regresses on Intel Sandybridge.
Signed-off-by: Chad Versace
---
src/mesa
On 02/28/2013 11:01 AM, Kenneth Graunke wrote:
> On 02/28/2013 09:08 AM, Eric Anholt wrote:
>> Chad Versace writes:
>>
>>> On 02/27/2013 11:39 AM, Eric Anholt wrote:
>>>> Chad Versace writes:
>>>>
>>>>> On 02/26/2013 11:15 PM, Er
nd it
to confidently make changes.
No regressions against mesa-master-809fdc211, piglit-99055b7, Ivybridge
0x0126.
Chad Versace (12):
intel: Fix an instance of mixed tabs and spaces
intel: Add field intel_mipmap_slice::has_hiz
intel: Add accessor functions for intel_miptree_slice::has_hi
Fix a line to use only spaces. All adjacent lines were using spaces. This
fixes weird indentation.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel
in the miptree.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 ++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 12
2 files changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/in
Add two new functions:
intel_miptree_slice_has_hiz
intel_renderbuffer_has_hiz
These functions are not yet used.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/intel/intel_fbo.c | 7 +++
src/mesa/drivers/dri/intel/intel_fbo.h | 3 +++
src/mesa/drivers/dri/intel
These will later be used to determine if hiz is enabled for the given
slice via intel_miptree_slice_has_hiz().
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 ++
src/mesa/drivers/dri/i965/brw_blorp.h | 10 ++
2 files changed, 12 insertions(+)
diff --git
Add two new parameters, 'level' and 'layer'. A later patch will pass the
new parameters to intel_miptree_slice_has_hiz().
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_context.h| 2 ++
src/mesa/drivers/dri/i965/brw_misc_state.c | 19 ---
s/brw_state_upload/brw_upload_state/
Found because the link was broken.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index
behaviorial change because, currently, if a hiz miptree
is present then hiz is enabled for all slices in the tree.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_blorp.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_clear.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.h
parameter to
intel_miptree_create() does not really force Y tiling.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 90 +++---
1 file changed, 54 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src
Extract from intel_miptree_create() the logic for selecting
intel_mipmap_tree::format and ::etc_format into a new function,
intel_miptree_select_formats(). No behavioral change.
Now, intel_miptree_create() is short enough to be understandable.
Signed-off-by: Chad Versace
---
src/mesa/drivers
layout,
intel_miptree_create() overrides the tiling and alignment as needed.
Rather than override something after it has been set, it's safer to just
set it correctly in the first place. To do that, this patch pushes down
the workaround into brw_miptree_layout().
Signed-off-by: Chad Versace
---
.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 633e598..aea42e8 100644
--- a/src/mesa/drivers/dri/i965
I had to use a debugger to deduce what total_width/height really were.
This patch is for the benefit of those who come after so they don't have
to dig as hard.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 7 ++-
1 file changed, 6 insertions(+), 1 del
On 03/01/2013 11:00 AM, Ian Romanick wrote:
> On 02/28/2013 03:45 PM, Chad Versace wrote:
>> Miptree creation has a workaround for separate stencil buffers. After the
>> layout is created, we override the tiling to I915_NONE and align it 64x64,
>> the size of a W-tile.
&g
Both patches are
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On 04/09/2013 04:03 PM, Eric Anholt wrote:
Kenneth Graunke writes:
From: Chad Versace
On Haswell, HiZ will selectively be enabled on individual miptree slices
to workaround a hardware bug. The two new functions below will permit us
to detect if hiz is enabled for a particular slice
On 04/09/2013 04:15 PM, Eric Anholt wrote:
Kenneth Graunke writes:
From: Chad Versace
Enable hiz by setting intel_context::has_hiz. However, to work around
a hardware bug, we selectively enable hiz for only nicely aligned miptree
slices.
No Piglit regressions on Haswell 0x0d26 rev07 when
On 04/10/2013 10:51 AM, Eric Anholt wrote:
Chad Versace writes:
v2:
- Rerun Piglit on ivb and hsw.
- Replace
[PATCH 2/8] intel: Add functions for checking if objs have hiz enabled
with
[PATCH 2/7] intel: Add field intel_mipmap_slice::has_hiz
- Remove
commit message]
Reviewed-by: Chad Versace
---
src/egl/drivers/dri2/platform_x11.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_x11.c
b/src/egl/drivers/dri2/platform_x11.c
index da61cfc..e9ca241 100644
--- a/src/egl/drivers/dri2/platform_x11.c
On 04/10/2013 11:55 AM, Kenneth Graunke wrote:
We need know this in order to decide what tiling mode to use.
Cc: Eric Anholt
Cc: Paul Berry
Signed-off-by: Kenneth Graunke
For the series,
Reviewed-by: Chad Versace
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On 04/10/2013 02:08 PM, Kenneth Graunke wrote:
This reduces the nesting level slightly, and in my opinion, makes it a
bit easier to follow.
Cc: Paul Berry
Cc: Chad Versace
Cc: Eric Anholt
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 10 ++
1
ng by default on Gen6+. This was due to a
botched merge conflict resolution.
v2: Return a mask of valid tilings from intel_miptree_select_tiling.
This allows us to avoid the X-tiling fallback if Y-tiling is actually
mandatory.
Cc: Paul Berry
Cc: Chad Versace
Cc: Eric Anholt
Signed-o
On 04/12/2013 11:24 AM, Matt Turner wrote:
On Thu, Apr 11, 2013 at 4:29 PM, Matt Turner wrote:
For the sake of consistency.
Tested-by: Emil Velikov
Reviewed-and-Tested-by: Andreas Boll
---
Chad & Jose,
Could you test the first two patches of this series with the Android
and scons build sy
subimage.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Chad Versace
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Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.
CC: Anuj Phogat
CC: Paul Berry
OTC-Tracker: CHRMOS-812
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 6
In an older BSpec, the restriction was documented for HSW GT3. The
current BSpec lists the restriction in a table for IVB, HSW, and VLVT.
Only the gods know to which hardware the restriction really applies.
CC: Paul Berry
CC: Anuj Phogat
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri
Google disabled fast color clears for all hardware because it causes corruption
on Haswell. This patch series fixes it so that Google can re-enable fast clears.
Chad Versace (2):
i965/blorp: Update language for fast color clear non-msrt restriction
i965/hsw: Apply non-msrt fast color clear w
On 11/26/2013 07:13 PM, Paul Berry wrote:
On 26 November 2013 17:34, Chad Versace wrote:
Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.
CC: Anuj Phogat
CC: Paul Berry
OTC-Tracker: CHRMOS
On 11/26/2013 09:34 PM, Kenneth Graunke wrote:
On 11/26/2013 05:34 PM, Chad Versace wrote:
Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.
CC: Anuj Phogat
CC: Paul Berry
OTC-Tracker
On 12/01/2013 01:53 AM, Tapani Pälli wrote:
Commit a594cec broke EGL X11 backend by adding dependency between
X11 and DRM backends requiring HAVE_EGL_PLATFORM_DRM defined for X11.
This patch fixes the issue by adding additional define for libdrm
detection independent of which backend is being co
On 12/02/2013 09:55 PM, Tapani Pälli wrote:
On 12/02/2013 11:06 PM, Chad Versace wrote:
On 12/01/2013 01:53 AM, Tapani Pälli wrote:
Commit a594cec broke EGL X11 backend by adding dependency between
X11 and DRM backends requiring HAVE_EGL_PLATFORM_DRM defined for X11.
This patch fixes the
.
No Piglit regressions on Ivybridge 0x0166. No fixes either.
I know no Ivybridge nor Baytrail bug related to this workaround.
However, the BSpec says the extra alignment is required, so let's do it.
CC: "9.2, 10.0"
CC: Anuj Phogat
CC: Paul Berry
Signed-off-by: Chad Versace
hogat
CC: Paul Berry
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 35 +--
1 file changed, 11 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cp
correct; actually, what the hardware appears to do is to
+ * align whatever rectangle is sent down the pipeline to the nearest
+ * multiple of 2x2 blocks, and then scale it up by a factor of N
+ * horizontally and 2 vertically. So the resulting alignment is 4
+ *
On 12/05/2013 04:36 AM, Paul Berry wrote:
On 4 December 2013 15:07, Chad Versace mailto:chad.vers...@linux.intel.com>> wrote:
bugget, verticeally, and vestically! oh my!
Wow, I wish I could say I did all those typos on purpose. Those are hilarious!
They're all fixed now.
amp;& !partial_clear &&
wm_prog_key.use_simd16_replicated_data &&
is_color_fast_clear_compatible(brw, format, &ctx->Color.ClearColor)) {
Thanks a bunch.
Reviewed-by: Chad Versace
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https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/8bc07bb70163c3706fb4ba5f980e57dc942f56dd
CC: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70740
Signed-off-by: Stéphane Marchesin
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri
On 12/20/2013 07:56 AM, Paul Berry wrote:
On 20 December 2013 04:47, Chad Versace wrote:
We need to emit depth stall flushes before depth and hiz resolves.
Placing them at the top of blorp's state emission fixes the hang.
Fixes HiZ hang in the new WebGL Google maps on Sandybridge Chro
On 12/20/2013 01:36 PM, Kenneth Graunke wrote:
On 12/20/2013 04:47 AM, Chad Versace wrote:
We need to emit depth stall flushes before depth and hiz resolves.
Placing them at the top of blorp's state emission fixes the hang.
Fixes HiZ hang in the new WebGL Google maps on Sandybridge Chro
On 12/19/2013 01:50 AM, Lauri Kasanen wrote:
On Wed, 18 Dec 2013 17:57:16 -0800
Matt Turner wrote:
On Tue, Dec 17, 2013 at 7:15 AM, Lauri Kasanen
It seems to me that the Intel code that uses this SSE4.1 function
is still buggy, as it has no runtime check - would it not crash
if built on a
On 12/10/2013 09:54 PM, Chia-I Wu wrote:
When the depth buffer is already cleared, skip GEN6_HIZ_OP_DEPTH_CLEAR. This
is made possible by tracking which slices have been cleared in
"struct intel_mipmap_level". The hiz_cleared flag is unset when the depth
buffer is rendered to or when a HiZ reso
The patches look good to me, and I verified that this caused no Piglit
regressions on Ivybridge when applied to master-8ab47b4.
Reviewed-by: Chad Versace
I committed them to master.
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On Tue, Jan 07, 2014 at 05:41:56AM -0800, Paul Berry wrote:
> On 6 January 2014 17:05, Chad Versace wrote:
>
> In solving a HiZ hang before Christmas vacation, I discovered that Mesa
> wasn't
> emitting sufficient workaround flushes. That bug was solved in
FILE__, __LINE__);
abort();
}
...
}
v2: Explain how I determined that need_workaround_flush wasn't getting
set when expected.
CC: Kenneth Graunke
CC: Paul Berry
CC: Stéphane Marchesin
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++
le after review completes and
they get committed to master.
Chad Versace (3):
i965/gen6/blorp: Set need_workaround_flush immediately after primitive
i965/gen6/blorp: Set need_workaround_flush at top of blorp
i965/gen6/blorp: Remove redundant HiZ workaround
src/mesa/drivers/dri/i965/brw_
sh in gen7_blorp_emit_primitive() because the
workaround applies only to gen6.
Reviewed-by: Paul Berry
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 1 -
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/driver
(codename
Stumpy) without a hang.
CC: Kenneth Graunke
CC: Paul Berry
CC: Stéphane Marchesin
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 14 --
1 file changed, 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers
On Tue, Jan 07, 2014 at 06:01:57AM -0800, Paul Berry wrote:
> On 6 January 2014 17:05, Chad Versace wrote:
>
> Commit 1a92881 added extra flushes to fix a HiZ hang in
> WebGL Google Maps. With the extra flushes emitted by the previous two
> patches, the flushes added
On Wed, Jan 08, 2014 at 07:59:38AM -0800, Paul Berry wrote:
> On 7 January 2014 16:58, Chad Versace wrote:
>
> Unconditionally set brw->need_workaround_flush at the top of gen6 blorp
> state emission.
>
> The art of emitting workaround flushes on Sandybri
For both patches,
Reviewed-by: Chad Versace
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w begin to remove the threading wrappers in
src/egl/main.
I'm not familiar with C11's thread headers, so patch 2 is
Acked-by: Chad Versace
Patches 3-7 are:
Reviewed-by: Chad Versace
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On Thu, Jan 09, 2014 at 01:07:58PM -0800, Carl Worth wrote:
> Hi folks,
>
> I just released Mesa 10.0.2 (a bit late) and followed it by immediately
> working through my queue of commits nominated for the stable branch,
> which I've just pushed out.
>
> Since the code for 10.0.2 was done and pushe
On Fri, Jan 10, 2014 at 08:14:19AM -0500, Rob Clark wrote:
> On Thu, Jan 9, 2014 at 10:36 PM, Eric Anholt wrote:
> > Rob Clark writes:
> >
> >> From: Rob Clark
> >> static int
> >> droid_open_device(void)
> >> {
> >> @@ -773,7 +672,7 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay
>
insertions(+), 6 deletions(-)
Please.
Acked-by: Chad Versace
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rc/mesa/drivers/dri/i965/intel_fbo.h | 4 +-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 39 +++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 21 +++
> 6 files changed, 118 insertions(+), 20 deletions(-)
This patch looks good to me.
Reviewed-by:
On Tue, Jan 28, 2014 at 11:59:14AM +, Emil Velikov wrote:
> Signed-off-by: Emil Velikov
> ---
> src/egl/drivers/dri2/platform_android.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index 4a20
On Wed, Mar 26, 2014 at 05:12:20PM -0700, Ian Romanick wrote:
> Tomorrow or Friday I'm going to send out the last of the
> GL_ARB_separate_shader_objects patches. Shortly after that, I will send
> out patches to enable GL_EXT_separate_shader_objects on GLES. This EXT
> is the GLES subset of the A
On Fri, Apr 18, 2014 at 05:30:02PM -0700, Ian Romanick wrote:
> On 04/18/2014 05:07 PM, Jamey Sharp wrote:
> > On Fri, Apr 18, 2014 at 4:49 PM, Ian Romanick wrote:
> >> On 04/18/2014 03:37 PM, Sarah Sharp wrote:
> If you use the unchecked
> > variant of the request, then the error is placed in th
ra opportunity for a memory) leak.
> >
> > Is there more difference than I know?
> >
> > I have 3 additional comments in the code below.
>
> Thanks for the review Ian!
>
> > > I talked to Kristen Høgsberg, who added most of the Mesa XCB calls, and
> >
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