Add two new parameters, 'level' and 'layer'. A later patch will pass the
new parameters to intel_miptree_slice_has_hiz().
Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_misc_state.c | 19 ++++++++++++++++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 ++++-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 5 ++++-
4 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index c173e49..4d18152 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1129,6 +1129,8 @@ bool brwCreateContext(int api,
* brw_misc_state.c
*/
void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_level,
+ uint32_t depth_layer,
struct intel_mipmap_tree *stencil_mt,
uint32_t *out_tile_mask_x,
uint32_t *out_tile_mask_y);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1024c42..862083a 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -267,9 +267,13 @@ brw_depthbuffer_format(struct brw_context *brw)
* This returns the worst-case mask of the low bits that have to go into the
* packet. If the 3 buffers don't agree on the drawing offset ANDed with this
* mask, then we're in trouble.
+ *
+ * If \a depth_mt is null, the \a depth_level and \a depth_layer are ignored.
*/
void
brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_level,
+ uint32_t depth_layer,
struct intel_mipmap_tree *stencil_mt,
uint32_t *out_tile_mask_x,
uint32_t *out_tile_mask_y)
@@ -337,16 +341,25 @@ brw_workaround_depthstencil_alignment(struct brw_context
*brw)
bool rebase_stencil = false;
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb,
BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb,
BUFFER_STENCIL);
- struct intel_mipmap_tree *depth_mt = NULL;
+ struct intel_mipmap_tree *depth_mt;
+ uint32_t depth_level, depth_layer;
struct intel_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
uint32_t tile_x = 0, tile_y = 0, stencil_tile_x = 0, stencil_tile_y = 0;
uint32_t stencil_draw_x = 0, stencil_draw_y = 0;
- if (depth_irb)
+ if (depth_irb) {
depth_mt = depth_irb->mt;
+ depth_level = depth_irb->mt_level;
+ depth_layer = depth_irb->mt_layer;
+ } else {
+ depth_mt = NULL;
+ depth_layer = 0;
+ depth_level = 0;
+ }
uint32_t tile_mask_x, tile_mask_y;
- brw_get_depthstencil_tile_masks(depth_mt, stencil_mt,
+ brw_get_depthstencil_tile_masks(depth_mt, depth_level, depth_layer,
+ stencil_mt,
&tile_mask_x, &tile_mask_y);
if (depth_irb) {
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 3834ae2..29b45aa 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -828,7 +828,10 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw,
uint32_t draw_y = params->depth.y_offset;
uint32_t tile_mask_x, tile_mask_y;
- brw_get_depthstencil_tile_masks(params->depth.mt, NULL,
+ brw_get_depthstencil_tile_masks(params->depth.mt,
+ params->depth.level,
+ params->depth.layer,
+ NULL /*stencil_mt*/,
&tile_mask_x, &tile_mask_y);
/* 3DSTATE_DEPTH_BUFFER */
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 21caa0a..1a19dd4 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -584,7 +584,10 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context
*brw,
uint32_t tile_mask_x, tile_mask_y;
if (params->depth.mt) {
- brw_get_depthstencil_tile_masks(params->depth.mt, NULL,
+ brw_get_depthstencil_tile_masks(params->depth.mt,
+ params->depth.level,
+ params->depth.layer,
+ NULL /*stencil_mt*/,
&tile_mask_x, &tile_mask_y);
}
--
1.8.1.2
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