On Wednesday, October 28, 2015 02:32:00 PM Jason Ekstrand wrote:
> This series adds a nir_pass datastructure and some helpers for managing
> optimization and lowering passes. I've been meaning to get around to this
> for some time. There are a couple of primary benifits to this:
>
> First, this
Did you care about WoA support, or not ? (ARM target, added in VC2012),
compatible with Windows RT and Windows 10 IoT.
De : mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] De la part de
Janusz Ganczarski
Envoyé : mardi 3 novembre 2015 04:43
À : mesa-dev@lists.freedesktop.org
Objet :
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_split_var_copies.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/nir/nir_split_var_copies.c
b/src/glsl/nir/nir_split_var_copies.c
index d2ea58a..d463f7b 100644
--- a/src/glsl/nir/nir_split_var_copies.c
+++ b/src/glsl/nir/nir
OPT() is the normal macro for passes that return booleans, while OPT_V()
is a variant that works for passes that don't properly report progress.
(Such passes should be fixed to return a boolean, eventually.)
These macros take care of calling nir_validate_shader() and setting
progress appropriately
We can't preserve dominance or live variable information.
This also begs the question: what about globals? Metadata only exists
at the nir_function_impl level, so it would seem there is no metadata
about global variables for us to invalidate.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir
Hello,
Here's my alternative suggestion to Jason's pass manager series.
First, it implements an OPT() macro in the i965 NIR backend, and
uses it for ~all passes. (Other drivers are obviously free to do likewise!)
I chose to group up some operations (such as input lowering) which
technically use
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_global_vars_to_local.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_lower_global_vars_to_local.c
b/src/glsl/nir/nir_lower_global_vars_to_local.c
index fab2366..9fa64ed 100644
--- a/src/glsl/nir/nir_lower_global_v
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_copy_propagate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/glsl/nir/nir_opt_copy_propagate.c
b/src/glsl/nir/nir_opt_copy_propagate.c
index 96520f8..7d8bdd7 100644
--- a/src/glsl/nir/nir_opt_copy_propagate.c
+++ b/src/gls
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_vec_to_movs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c
b/src/glsl/nir/nir_lower_vec_to_movs.c
index c08b721..736a66c 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl/nir
Failing to call nir_metadata_preserve() can have nasty consequences:
some pass breaks dominance information, but leaves it marked as valid,
causing some subsequent pass to go haywire and probably crash.
This pass adds a simple validation mechanism to ensure passes handle
this properly. We add a n
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_remove_phis.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/nir/nir_opt_remove_phis.c
b/src/glsl/nir/nir_opt_remove_phis.c
index 5bdf7ef..66d3754 100644
--- a/src/glsl/nir/nir_opt_remove_phis.c
+++ b/src/glsl/nir/nir_opt
There are currently two methods in llvmpipe code to calculate coeffs to
be used as inputs for the fragment shader. The two methods use slightly
different ways to do the floating point calculations and thus produce
slightly different results.
The decision which method to use is determined by the si
On Tue, Nov 3, 2015 at 2:14 AM, Ilia Mirkin wrote:
> On Mon, Nov 2, 2015 at 8:07 PM, Ian Romanick wrote:
>> On 11/02/2015 04:50 PM, Ilia Mirkin wrote:
>>> GL_EXT_color_buffer_float adds support for float buffers in ES3.0+, but
>>> explicitly disallows 32-bit blending. However this restriction was
On Tue, Nov 3, 2015 at 9:51 AM, Marek Olšák wrote:
> On Tue, Nov 3, 2015 at 2:14 AM, Ilia Mirkin wrote:
>> On Mon, Nov 2, 2015 at 8:07 PM, Ian Romanick wrote:
>>> On 11/02/2015 04:50 PM, Ilia Mirkin wrote:
GL_EXT_color_buffer_float adds support for float buffers in ES3.0+, but
explicit
On Fri, 2015-10-30 at 16:19 +0200, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > Right now some opcodes that only use constant surface indexing mark them as
> > used in the generator while others do it in the visitor. When the opcode can
> > handle both direct and indirect surface ind
On 2 November 2015 at 19:41, Jason Ekstrand wrote:
> On Mon, Nov 2, 2015 at 9:33 AM, Connor Abbott wrote:
>> On Mon, Nov 2, 2015 at 8:35 AM, Emil Velikov
>> wrote:
>>> Hi all,
>>>
>>> From a quick look, it seems that NIR copies (almost ?) all the state
>>> from GLSL IR even if it doesn't use it
On 3 November 2015 at 00:29, Matt Turner wrote:
> Generated by
>
>sed -i -e 's/\.bits\././g' *.c *.h *.cpp
>sed -i -e 's/dw1\.//g' *.c *.h *.cpp
>
> and then reverting changes to comments in gen7_blorp.cpp and
> brw_fs_generator.cpp.
>
> There wasn't any utility offered by forcing the prog
On 3 November 2015 at 00:29, Matt Turner wrote:
> Put fields that are meaningless with an immediate in the same storage
> with the immediate.
There is something funky here. Should it be
"Put fields that are meaningless _without_ an immediate in the same storage
_as_ the immediate..."
-Emil
_
Some I managed to not end up with [PATCH] in subject or my coverletter.
This is my first patch to mesa-dev. Hopefully, I have done everything correctly.
I posed the idea about a week ago:
Manipulate GALLIUM_HUD post-launch (interactively)
http://lists.freedesktop.org/archives/mesa-dev/20
- env GALLIUM_HUD_VISIBLE: control default visibility
- env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal
---
docs/envvars.html | 6 ++
src/gallium/auxiliary/hud/hud_context.c | 23 +++
2 files changed, 29 insertions(+)
diff --git a/docs/en
This is my first patch to mesa-dev. Hopefully, I have done everything correctly.
I posed the idea about a week ago:
Manipulate GALLIUM_HUD post-launch (interactively)
http://lists.freedesktop.org/archives/mesa-dev/2015-October/098544.html
I decided to keep it simple for my first patch and im
On 3 November 2015 at 00:29, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_defines.h| 10 ++
> src/mesa/drivers/dri/i965/brw_eu_emit.c| 2 +-
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 +++--
> src/mesa/drivers/dri/i965/brw_reg.h| 25
Matt Turner writes:
> This reverts commit bbf8239f92ecd79431dfa41402e1c85318e7267f.
>
> I didn't like that commit to begin with -- computing things at compile
> time is fine -- but for purposes of verifying that the resulting values
> are correct, looking up 0x00 and 0x30 in a table is a lot bett
Hi,
This seems otherwise OK, but you should use sigaction() instead of
signal() for portability (see NOTES section in the manual page).
- Eero
On 11/03/2015 12:43 PM, boombatower wrote:
- env GALLIUM_HUD_VISIBLE: control default visibility
- env GALLIUM_HUD_SIGNAL_TOGGLE: toggle vis
Iago Toral writes:
> On Fri, 2015-10-30 at 16:19 +0200, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> > Right now some opcodes that only use constant surface indexing mark them as
>> > used in the generator while others do it in the visitor. When the opcode
>> > can
>> > handle bo
Matt Turner writes:
> Generated by
>
>sed -i -e 's/\.bits\././g' *.c *.h *.cpp
>sed -i -e 's/dw1\.//g' *.c *.h *.cpp
>
> and then reverting changes to comments in gen7_blorp.cpp and
> brw_fs_generator.cpp.
>
> There wasn't any utility offered by forcing the programmer to list these
> to a
On Tue, Nov 3, 2015 at 11:43 AM, boombatower wrote:
> - env GALLIUM_HUD_VISIBLE: control default visibility
> - env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal
> ---
> docs/envvars.html | 6 ++
> src/gallium/auxiliary/hud/hud_context.c | 23 +
On Tue, 2015-11-03 at 15:28 +0200, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Fri, 2015-10-30 at 16:19 +0200, Francisco Jerez wrote:
> >> Iago Toral Quiroga writes:
> >>
> >> > Right now some opcodes that only use constant surface indexing mark them
> >> > as
> >> > used in the gener
On Tue, Nov 3, 2015 at 5:08 AM, Emil Velikov wrote:
> On 2 November 2015 at 19:41, Jason Ekstrand wrote:
>> On Mon, Nov 2, 2015 at 9:33 AM, Connor Abbott wrote:
>>> On Mon, Nov 2, 2015 at 8:35 AM, Emil Velikov
>>> wrote:
Hi all,
From a quick look, it seems that NIR copies (almos
Iago Toral writes:
> On Tue, 2015-11-03 at 15:28 +0200, Francisco Jerez wrote:
>> Iago Toral writes:
>>
>> > On Fri, 2015-10-30 at 16:19 +0200, Francisco Jerez wrote:
>> >> Iago Toral Quiroga writes:
>> >>
>> >> > Right now some opcodes that only use constant surface indexing mark
>> >> > th
On 11/03/2015 03:43 AM, boombatower wrote:
- env GALLIUM_HUD_VISIBLE: control default visibility
- env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal
---
docs/envvars.html | 6 ++
src/gallium/auxiliary/hud/hud_context.c | 23 +++
2 files
On 11/02/2015 08:42 PM, Janusz Ganczarski wrote:
Hello,
In attachment fixed Visual C++ 2015 (VC 14) builds for Mesa.
Currently only gallium softpipe driver support. Gallium llvmpipe
driver support work in progress.
I'm not sure we're interested in MSVC project files (I'm certainly not).
Unles
On 3 November 2015 at 00:29, Matt Turner wrote:
Please add a bit of commit message - "Mostly unused as of last commit.
Fold the remaining cases (GRF only?) to use the base brw_reg struct."
or anything else that you feel is appropriate.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp
On 3 November 2015 at 00:29, Matt Turner wrote:
> The test (file == BAD_FILE) works on registers for which the constructor
> has not run because BAD_FILE is zero. The next commit will move
> BAD_FILE in the enum so that it's no longer zero.
Doesn't the DECLARE_RALLOC_CXX_OPERATORS macro and fs_r
On 3 November 2015 at 00:29, Matt Turner wrote:
> @@ -422,7 +423,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
> uint8_t vf3)
> fs_reg::fs_reg(struct brw_reg reg) :
> backend_reg(reg)
> {
> - this->file = HW_REG;
> + this->file = (enum register_file)reg.file;
You're not ad
On 3 November 2015 at 00:29, Matt Turner wrote:
> index 6eeafd5..3d2b051 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -423,7 +423,6 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
> uint8_t vf3)
> fs_reg::fs_reg(struct brw_reg re
On 3 November 2015 at 00:29, Matt Turner wrote:
> This reverts commit bbf8239f92ecd79431dfa41402e1c85318e7267f.
>
> I didn't like that commit to begin with -- computing things at compile
> time is fine -- but for purposes of verifying that the resulting values
> are correct, looking up 0x00 and 0x
On 3 November 2015 at 00:29, Matt Turner wrote:
> @@ -387,7 +342,9 @@ vec4_visitor::opt_vector_float()
>
>remaining_channels &= ~inst->dst.writemask;
>if (remaining_channels == 0) {
> - vec4_instruction *mov = MOV(inst->dst, imm);
> + unsigned vf;
> + memcp
On 11/03/2015 05:43 PM, Brian Paul wrote:
On 11/03/2015 03:43 AM, boombatower wrote:
- env GALLIUM_HUD_VISIBLE: control default visibility
- env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal
---
docs/envvars.html | 6 ++
src/gallium/auxiliary/hud/hud_conte
Hi Matt,
On 3 November 2015 at 00:29, Matt Turner wrote:
> backend_reg (from which fs_reg, src_reg, and dst_reg inherit) includes a
> brw_reg that's used for "hardware regs" -- precolored registers or
> architecture
> registers. This leads to properties like source modifiers, the register type,
On 3 November 2015 at 15:48, Brian Paul wrote:
> On 11/02/2015 08:42 PM, Janusz Ganczarski wrote:
>>
>> Hello,
>> In attachment fixed Visual C++ 2015 (VC 14) builds for Mesa.
>> Currently only gallium softpipe driver support. Gallium llvmpipe
>> driver support work in progress.
>
>
> I'm not sure
Hello Jimmy,
Please add your name to your git config.
On 3 November 2015 at 10:43, boombatower wrote:
> - env GALLIUM_HUD_VISIBLE: control default visibility
> - env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal
> ---
> docs/envvars.html | 6 ++
> src/galliu
On Tue, Nov 3, 2015 at 2:08 AM, Emil Velikov wrote:
> On 2 November 2015 at 19:41, Jason Ekstrand wrote:
>> On Mon, Nov 2, 2015 at 9:33 AM, Connor Abbott wrote:
>>> On Mon, Nov 2, 2015 at 8:35 AM, Emil Velikov
>>> wrote:
Hi all,
From a quick look, it seems that NIR copies (almos
On 10/31/2015 11:45 AM, Ilia Mirkin wrote:
On Sat, Oct 31, 2015 at 10:23 AM, Brian Paul wrote:
On 10/30/2015 11:15 PM, Ilia Mirkin wrote:
This will allow gallium drivers to send messages to KHR_debug endpoints
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/util/u_debug.c | 16 +
Francisco Jerez writes:
> Iago Toral writes:
>
>> On Tue, 2015-11-03 at 15:28 +0200, Francisco Jerez wrote:
>>> Iago Toral writes:
>>>
>>> > On Fri, 2015-10-30 at 16:19 +0200, Francisco Jerez wrote:
>>> >> Iago Toral Quiroga writes:
>>> >>
>>> >> > Right now some opcodes that only use consta
On Tue, Nov 3, 2015 at 2:38 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>> Put fields that are meaningless with an immediate in the same storage
>> with the immediate.
> There is something funky here. Should it be
>
> "Put fields that are meaningless _without_ an imm
On Tue, Nov 3, 2015 at 3:11 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_defines.h| 10 ++
>> src/mesa/drivers/dri/i965/brw_eu_emit.c| 2 +-
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 +++--
On Tue, Nov 3, 2015 at 3:31 AM, Kenneth Graunke wrote:
> OPT() is the normal macro for passes that return booleans, while OPT_V()
> is a variant that works for passes that don't properly report progress.
> (Such passes should be fixed to return a boolean, eventually.)
>
> These macros take care of
On Tue, Nov 3, 2015 at 8:04 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>
> Please add a bit of commit message - "Mostly unused as of last commit.
> Fold the remaining cases (GRF only?) to use the base brw_reg struct."
> or anything else that you feel is appropriate.
On Tue, Nov 3, 2015 at 11:58 AM, Brian Paul wrote:
> On 10/31/2015 11:45 AM, Ilia Mirkin wrote:
>>
>> On Sat, Oct 31, 2015 at 10:23 AM, Brian Paul wrote:
>>>
>>> On 10/30/2015 11:15 PM, Ilia Mirkin wrote:
This will allow gallium drivers to send messages to KHR_debug endpoints
On Tue, Nov 3, 2015 at 8:05 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>> The test (file == BAD_FILE) works on registers for which the constructor
>> has not run because BAD_FILE is zero. The next commit will move
>> BAD_FILE in the enum so that it's no longer zero
On 3 November 2015 at 17:27, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 2:38 AM, Emil Velikov wrote:
>> On 3 November 2015 at 00:29, Matt Turner wrote:
>>> Put fields that are meaningless with an immediate in the same storage
>>> with the immediate.
>> There is something funky here. Should it b
On Tue, Nov 3, 2015 at 8:06 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>
>> @@ -422,7 +423,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
>> uint8_t vf3)
>> fs_reg::fs_reg(struct brw_reg reg) :
>> backend_reg(reg)
>> {
>> - this->file = HW_REG;
On Tue, Nov 3, 2015 at 8:07 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>
>> index 6eeafd5..3d2b051 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -423,7 +423,6 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint
https://bugs.freedesktop.org/show_bug.cgi?id=92783
Ben Widawsky changed:
What|Removed |Added
CC||b...@bwidawsk.net
--
You are receiving t
On Tue, Nov 3, 2015 at 8:09 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>
>> @@ -387,7 +342,9 @@ vec4_visitor::opt_vector_float()
>>
>>remaining_channels &= ~inst->dst.writemask;
>>if (remaining_channels == 0) {
>> - vec4_instruction *mov = MO
This fixes crashes with some piglit OpenCL tests.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/n
To get the size (in bytes) of a compute parameter, clover first calls
get_compute_param() with a NULL data pointer. The RET() macro is based
on nv50.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 45 --
1 file changed, 21 insertions(+
On Tue, Nov 3, 2015 at 1:35 PM, Samuel Pitoiset
wrote:
> To get the size (in bytes) of a compute parameter, clover first calls
> get_compute_param() with a NULL data pointer. The RET() macro is based
> on nv50.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_scre
On 11/03/2015 07:26 PM, Ilia Mirkin wrote:
On Tue, Nov 3, 2015 at 1:35 PM, Samuel Pitoiset
wrote:
To get the size (in bytes) of a compute parameter, clover first calls
get_compute_param() with a NULL data pointer. The RET() macro is based
on nv50.
Signed-off-by: Samuel Pitoiset
---
src/ga
On 3 November 2015 at 18:02, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 8:05 AM, Emil Velikov wrote:
>> On 3 November 2015 at 00:29, Matt Turner wrote:
>>> The test (file == BAD_FILE) works on registers for which the constructor
>>> has not run because BAD_FILE is zero. The next commit will mo
Series Reviewed-by: Jordan Justen
For the 2de4e8fdbae1e1909ce35f8ba15608a124686fb0 version on your drm
gt4 branch.
On 2015-10-23 10:56:33, Ben Widawsky wrote:
> Cc: Kristian Høgsberg
> Cc: Damien Lespiau
> Signed-off-by: Ben Widawsky
> ---
> intel/intel_chipset.h | 12 +++-
> 1 file
On 3 November 2015 at 17:55, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 8:04 AM, Emil Velikov wrote:
>> On 3 November 2015 at 00:29, Matt Turner wrote:
>>
>> Please add a bit of commit message - "Mostly unused as of last commit.
>> Fold the remaining cases (GRF only?) to use the base brw_reg st
Seried Reviewed-by: Jordan Justen
For the dde33fc23c4ef8b8e02fb5768161fdaa078847d5 version on your mesa
gt4 branch.
On 2015-10-29 17:30:35, Ben Widawsky wrote:
> Like other gen8+ hardware, the hardware automatically scales up thread counts
> and URB sizes, so there is no need to do anything but
On Tue, Nov 3, 2015 at 10:45 AM, Emil Velikov wrote:
> I already have a few patches for what. I've even started exploring
> which constructors we can nuke :-)
> Can you post a branch somewhere so that I can rebase + send before you
> get onto the next batch.
Sure. It's the brw_reg branch of my tr
On 3 November 2015 at 18:10, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 8:07 AM, Emil Velikov wrote:
>> On 3 November 2015 at 00:29, Matt Turner wrote:
>>
>>> index 6eeafd5..3d2b051 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>>> @@ -423,
On 03/11/15 15:48, Brian Paul wrote:
On 11/02/2015 08:42 PM, Janusz Ganczarski wrote:
Hello,
In attachment fixed Visual C++ 2015 (VC 14) builds for Mesa.
Currently only gallium softpipe driver support. Gallium llvmpipe
driver support work in progress.
I'm not sure we're interested in MSVC proj
Now with the correct email address ...
Cheers,
Tom
From: StDenis, Tom
Sent: Tuesday, November 3, 2015 13:03
To: mesa-dev@lists.freedesktop.org
Cc: gpudriverdevsupport
Subject: Avoid segfault in omx deconstructor
If the constructor fails before the lists are i
On Tue, Nov 3, 2015 at 2:33 AM, Emil Velikov wrote:
> On 3 November 2015 at 00:29, Matt Turner wrote:
>> Generated by
>>
>>sed -i -e 's/\.bits\././g' *.c *.h *.cpp
>>sed -i -e 's/dw1\.//g' *.c *.h *.cpp
>>
>> and then reverting changes to comments in gen7_blorp.cpp and
>> brw_fs_generator
On 3 November 2015 at 18:20, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 8:09 AM, Emil Velikov wrote:
>> On 3 November 2015 at 00:29, Matt Turner wrote:
>>
>>> @@ -387,7 +342,9 @@ vec4_visitor::opt_vector_float()
>>>
>>>remaining_channels &= ~inst->dst.writemask;
>>>if (remaining
Hi all,
While working on FP64 for i965, there's an issue that I thought of
with the vec4 backend that I'm not sure how to resolve. From what I
understand, the execmask works the same way in Align16 mode as Align1
mode, except that you only use the first 8 channels in practice for
SIMD4x2, and the
The subject line should have something like "st/omx: ...".
Apart from that the patch is Reviewed-by: Christian König
Regards,
Christian.
On 03.11.2015 19:06, StDenis, Tom wrote:
Now with the correct email address ...
Cheers,
Tom
---
Ian, any comment on this?
On Fri, Sep 25, 2015 at 1:32 PM, Ilia Mirkin wrote:
> Hi Ian (and other spec experts),
>
> The ARB_ssbo spec mentions the following:
>
> OpenGL 4.0 (either core or compatibility profile) is required.
>
> ...
>
> Additionally, the shading language provides the mem
Connor Abbott writes:
> Hi all,
>
> While working on FP64 for i965, there's an issue that I thought of
> with the vec4 backend that I'm not sure how to resolve. From what I
> understand, the execmask works the same way in Align16 mode as Align1
> mode, except that you only use the first 8 channel
On Tue, Nov 3, 2015 at 5:48 AM, Francisco Jerez wrote:
> Matt Turner writes:
>
>> Generated by
>>
>>sed -i -e 's/\.bits\././g' *.c *.h *.cpp
>>sed -i -e 's/dw1\.//g' *.c *.h *.cpp
>>
>> and then reverting changes to comments in gen7_blorp.cpp and
>> brw_fs_generator.cpp.
>>
>> There wasn'
On Tue, Nov 3, 2015 at 3:00 PM, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 5:48 AM, Francisco Jerez wrote:
>> Matt Turner writes:
>>
>>> Generated by
>>>
>>>sed -i -e 's/\.bits\././g' *.c *.h *.cpp
>>>sed -i -e 's/dw1\.//g' *.c *.h *.cpp
>>>
>>> and then reverting changes to comments in
On Tue, Nov 3, 2015 at 12:09 PM, Ilia Mirkin wrote:
> On Tue, Nov 3, 2015 at 3:00 PM, Matt Turner wrote:
>> On Tue, Nov 3, 2015 at 5:48 AM, Francisco Jerez
>> wrote:
>>> Matt Turner writes:
>>>
Generated by
sed -i -e 's/\.bits\././g' *.c *.h *.cpp
sed -i -e 's/dw1\.//
On Tue, Nov 3, 2015 at 12:13 PM, Matt Turner wrote:
> On Tue, Nov 3, 2015 at 12:09 PM, Ilia Mirkin wrote:
>> On Tue, Nov 3, 2015 at 3:00 PM, Matt Turner wrote:
>>> On Tue, Nov 3, 2015 at 5:48 AM, Francisco Jerez
>>> wrote:
Matt Turner writes:
> Generated by
>
>sed -i
On 11/03/2015 09:31 AM, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/nir/nir_opt_remove_phis.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/glsl/nir/nir_opt_remove_phis.c
> b/src/glsl/nir/nir_opt_remove_phis.c
> index 5bdf7ef..66d3754 100644
> --
On 11/03/2015 09:31 AM, Kenneth Graunke wrote:
> We can't preserve dominance or live variable information.
>
> This also begs the question: what about globals? Metadata only exists
> at the nir_function_impl level, so it would seem there is no metadata
> about global variables for us to invalidat
On Tue, Nov 3, 2015 at 5:16 AM, Francisco Jerez wrote:
> Matt Turner writes:
>
>> This reverts commit bbf8239f92ecd79431dfa41402e1c85318e7267f.
>>
>> I didn't like that commit to begin with -- computing things at compile
>> time is fine -- but for purposes of verifying that the resulting values
>
This fixes crashes with some piglit OpenCL tests.
Changes since v2:
- get rid of ul suffixes when they are unnecessary
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/dr
To get the size (in bytes) of a compute parameter, clover first calls
get_compute_param() with a NULL data pointer. The RET() macro is based
on nv50.
Changes since v2:
- get rid of ul suffixes when they are unnecessary
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_scr
On Saturday, October 31, 2015 02:22:47 PM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 30
> +++---
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i96
Series is:
Reviewed-by: Ilia Mirkin
On Tue, Nov 3, 2015 at 4:04 PM, Samuel Pitoiset
wrote:
> To get the size (in bytes) of a compute parameter, clover first calls
> get_compute_param() with a NULL data pointer. The RET() macro is based
> on nv50.
>
> Changes since v2:
> - get rid of ul suffixes
On Mon, Oct 26, 2015 at 5:08 AM, Pohjolainen, Topi
wrote:
> On Wed, Oct 21, 2015 at 03:58:13PM -0700, Matt Turner wrote:
>> Often annotations are identical between sets of consecutive
>> instructions. We can perhaps avoid some memory allocations by reusing
>> the previous annotation.
>> ---
>> sr
This commit adds the capability to NIR to support separate textures and
samplers. As it currently stands, glsl_to_nir only sets the sampler and
leaves the texture alone as it did before and nir_lower_samplers assumes
this. However, backends can, if they wish, assume that they are separate
because
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 8bc21df..6155274 100644
--- a/src/mesa/drivers/dri
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp| 47 +++--
src/mesa/drivers/dri/i965/brw_fs.h | 4 ++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
Separate textures and samplers are something that a lot of hardware
supports. Our hardware in particular has done this ever since the original
i965 chips. Part of this is because DX has made it a requirement for some
time now. GL allows you to expose it sort-of but weasel-words it enough
that yo
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 20 ++--
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 8058b34..b06a069 10064
---
src/mesa/drivers/dri/i965/brw_vec4.h | 4 +++-
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 27 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 12
3 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Reviewed-by: Jason Ekstrand
On Tue, Nov 3, 2015 at 12:31 AM, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/nir/nir_opt_copy_propagate.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/src/glsl/nir/nir_opt_copy_propagate.c
> b/src/glsl/nir/nir_opt_copy
On Tue, Nov 3, 2015 at 12:31 AM, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/nir/nir_lower_global_vars_to_local.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/glsl/nir/nir_lower_global_vars_to_local.c
> b/src/glsl/nir/nir_lower_global_vars_to_local
Reviewed-by: Jason Ekstrand
On Tue, Nov 3, 2015 at 12:31 AM, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/nir/nir_split_var_copies.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/glsl/nir/nir_split_var_copies.c
> b/src/glsl/nir/nir_split_var_cop
On Tue, Nov 3, 2015 at 12:31 AM, Kenneth Graunke wrote:
> We can't preserve dominance or live variable information.
>
> This also begs the question: what about globals? Metadata only exists
> at the nir_function_impl level, so it would seem there is no metadata
> about global variables for us to
Reviewed-by: Jason Ekstrand
On Tue, Nov 3, 2015 at 12:31 AM, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/nir/nir_lower_vec_to_movs.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c
> b/src/glsl/nir/nir_lower_vec_t
Reviewed-by: Jason Ekstrand
On Tue, Nov 3, 2015 at 12:19 PM, Eduardo Lima Mitev wrote:
> On 11/03/2015 09:31 AM, Kenneth Graunke wrote:
>> Signed-off-by: Kenneth Graunke
>> ---
>> src/glsl/nir/nir_opt_remove_phis.c | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/src/glsl/nir/n
We're about to put more pass management stuff in here so it needs a better
name.
Reviewed-by: Kristian Høgsberg
---
src/glsl/Makefile.sources | 2 +-
src/glsl/nir/nir_metadata.c | 54 -
src/glsl/nir/nir_pass.c | 54 ++
Reviewed-by: Kristian Høgsberg
---
src/glsl/nir/nir.h| 2 --
src/glsl/nir/nir_opt_copy_propagate.c | 2 +-
src/glsl/nir/nir_opt_dce.c| 2 +-
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 1d3e281..f2d01e
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