On Saturday, October 31, 2015 02:22:47 PM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 30
> +++++++++++++++-----------
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index b8f90f2..606fbd0 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -1183,24 +1183,27 @@ vec4_visitor::gs_end_primitive()
>
> void
> vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
> - dst_reg dst, src_reg offset,
> + dst_reg dst, src_reg surf_offset,
> src_reg src0, src_reg src1)
> {
> - unsigned mlen = 0;
> + unsigned mlen = 1 + (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
> + src_reg src_payload(this, glsl_type::uint_type, mlen);
> + dst_reg payload(src_payload);
> + payload.writemask = WRITEMASK_X;
>
> /* Set the atomic operation offset. */
> - emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), offset));
> - mlen++;
> + emit(MOV(offset(payload, 0), surf_offset));
> + unsigned i = 1;
>
> /* Set the atomic operation arguments. */
> if (src0.file != BAD_FILE) {
> - emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), src0));
> - mlen++;
> + emit(MOV(offset(payload, i), src0));
> + i++;
> }
>
> if (src1.file != BAD_FILE) {
> - emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), src1));
> - mlen++;
> + emit(MOV(offset(payload, i), src1));
> + i++;
> }
>
> /* Emit the instruction. Note that this maps to the normal SIMD8
> @@ -1208,24 +1211,27 @@ vec4_visitor::emit_untyped_atomic(unsigned atomic_op,
> unsigned surf_index,
> * unused channels will be masked out.
> */
> vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
> - brw_message_reg(0),
> + src_payload,
> src_reg(surf_index), src_reg(atomic_op));
> inst->mlen = mlen;
> }
>
> void
> vec4_visitor::emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
> - src_reg offset)
> + src_reg surf_offset)
> {
> + dst_reg offset(this, glsl_type::uint_type);
> + offset.writemask = WRITEMASK_X;
> +
> /* Set the surface read offset. */
> - emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X), offset));
> + emit(MOV(offset, surf_offset));
>
> /* Emit the instruction. Note that this maps to the normal SIMD8
> * untyped surface read message, but that's OK because unused
> * channels will be masked out.
> */
> vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst,
> - brw_message_reg(0),
> + src_reg(offset),
> src_reg(surf_index), src_reg(1));
> inst->mlen = 1;
> }
> Looks good to me - it's always great to see more Gen7+ only MRF code going away. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
signature.asc
Description: This is a digitally signed message part.
_______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
