On Wed, 2015-08-05 at 12:24 -0700, Connor Abbott wrote:
> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
> > The original GLSL IR intrinsics have been lowered to an internal
> > version that accepts a block index and an offset instead of a
> > SSBO reference.
> > ---
> > src/glsl/nir/g
On Wed, 2015-08-05 at 12:17 -0700, Connor Abbott wrote:
> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
> > ---
> > src/glsl/nir/glsl_to_nir.cpp | 36
> > src/glsl/nir/nir_intrinsics.h | 12 ++--
> > 2 files changed, 42 insertions(+), 6 de
On Wed, Aug 05, 2015 at 01:47:26PM +0300, Francisco Jerez wrote:
> "Pohjolainen, Topi" writes:
>
> > On Wed, Aug 05, 2015 at 10:36:09AM +0300, Pohjolainen, Topi wrote:
> >> On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
> >> > v2: Move the image_params array back to brw_stage_pr
The series looks good. You could probably s/GLuint/unsigned
in patch three as it is not "in the API", but that's a nitpick.
(You're fixing warnings, and not making things worse)
Either way the series is:
Reviewed-by: Thomas Helland
Someone else needs to push these for you (?).
AFAIK you don't ha
That is correct Thomas. I do not have commit access to push these myself.
On 6 August 2015 at 18:35, Thomas Helland wrote:
> The series looks good. You could probably s/GLuint/unsigned
> in patch three as it is not "in the API", but that's a nitpick.
> (You're fixing warnings, and not making thi
On Wed, Aug 05, 2015 at 12:51:19PM +0300, Pohjolainen, Topi wrote:
> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> > This will be used to pass image meta-data to the shader when we cannot
> > use typed surface reads and writes. All entries except surface_idx
> > and size are o
On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> > This will be used to pass image meta-data to the shader when we cannot
> > use typed surface reads and writes. All entries except surface_idx
> > and size are o
Reviewed-by: Tapani Pälli
On 08/05/2015 04:13 PM, Timothy Arceri wrote:
Stage ref cannot be queried for transform feedback.
Also simplify the build_stageref function by passing the
correct mode for uniforms.
Cc: Tapani Pälli
---
No piglit regressions, no program_interface_query CTS regress
EdB writes:
> As sugested by Tom a long time ago
> and in order to be able to create Piglit tests
>
> v2:
> replace NOT_SUPPORTED_BY_CL_1_1 macro with an inline function
> remove extra space in clLinkProgram arg
>
> v3:
> use __func__
>
Hah! Using __func__ *is* an argument to prefer a macro over
"Pohjolainen, Topi" writes:
> On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
>> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
>> > This will be used to pass image meta-data to the shader when we cannot
>> > use typed surface reads and writes. All entries ex
-NaN != NaN, and -Inf != Inf, so this should be safe.
Found while working on my VRP pass.
Shader-db results on my IVB:
total instructions in shared programs: 1698267 -> 1698067 (-0.01%)
instructions in affected programs: 15785 -> 15585 (-1.27%)
helped:36
HURT:
These where found when going through the mysteriously
high gains I got from the VRP pass. My pass was doing
bad things, but upon inspection I found these.
First patch is benefitial, the rest shows no change
on a shader-db run on my system.
Thomas Helland (3):
nir: Simplify fne(fneg(a), a) -> fne
The same rationale as in the other patches.
No shader-db changes.
Signed-off-by: Thomas Helland
---
src/glsl/nir/nir_opt_algebraic.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index 3e483fb..d005f81 100644
--- a/s
The positive and negative value of a float can only
be equal to each other if it is -0.0f and 0.0f.
This is safe for Nan and Inf, as -Nan != Nan, and -Inf != Inf
This gives no changes in my shader-db
Signed-off-by: Thomas Helland
---
src/glsl/nir/nir_opt_algebraic.py | 1 +
1 file changed, 1 ins
https://bugs.freedesktop.org/show_bug.cgi?id=91263
Marek Olšák changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Mon, Jul 20, 2015 at 07:23:00PM +0300, Francisco Jerez wrote:
> v2: Add CS support.
> ---
> src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw_gs.c | 1 +
> src/mesa/drivers/dri/i965/brw_vs.c | 3 ++-
> src/mesa/drivers/dri/i965/brw_wm.c | 3 ++-
> 4 files chang
On Mon, Jul 20, 2015 at 07:23:47PM +0300, Francisco Jerez wrote:
> v2: Add CS support. Move the image_params array back to
> brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 10 +++-
> src/mesa/drivers/dri/i965/brw_gs_surface_sta
On 08/06/2015 07:44 AM, Daniel Scharrer wrote:
CC: "10.6"
---
v2: added CC for 10.6
renamed _mesa_tex_target_to_index to tex_target_to_index
moved declaration of variable before code
added missing spaces in ternary operators
src/mesa/main/get.c | 93 +
CC: "10.6"
---
v2: added CC for 10.6
renamed _mesa_tex_target_to_index to tex_target_to_index
moved declaration of variable before code
added missing spaces in ternary operators
src/mesa/main/get.c | 93
src/mesa/main/texparam.c
"Pohjolainen, Topi" writes:
> On Mon, Jul 20, 2015 at 07:23:00PM +0300, Francisco Jerez wrote:
>> v2: Add CS support.
>> ---
>> src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
>> src/mesa/drivers/dri/i965/brw_gs.c | 1 +
>> src/mesa/drivers/dri/i965/brw_vs.c | 3 ++-
>> src/mesa/drivers/dri/i9
Francisco Jerez writes:
> "Pohjolainen, Topi" writes:
>
>> On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
>>> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
>>> > This will be used to pass image meta-data to the shader when we cannot
>>> > use typed surface
But, isn't -INT_MIN == INT_MIN?
Regards,
Boyan Ding
2015-08-06 19:36 GMT+08:00 Thomas Helland :
> The same rationale as in the other patches.
> No shader-db changes.
>
> Signed-off-by: Thomas Helland
> ---
> src/glsl/nir/nir_opt_algebraic.py | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --
Iago Toral Quiroga writes:
> The dst is always written, in this case the predicate is only used to select
> the value to write, so if we are spilling the dst we always want to write
> whatever value we selected to scratch.
> ---
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 ++-
> 1 file
Iago Toral Quiroga writes:
> ---
> .../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 24
> +++---
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
Francisco Jerez writes:
> Iago Toral writes:
>
>> On Fri, 2015-07-31 at 13:12 +0300, Francisco Jerez wrote:
>>> Iago Toral writes:
>>>
>>> > On Thu, 2015-07-30 at 17:08 +0300, Francisco Jerez wrote:
>>> >> Iago Toral Quiroga writes:
>>> >>
>>> >> > When we have code such as this:
>>> >> >
>>
On a related note, can we disable HDP flushes and other flushes for
USWC when we don't use write
combining and CPU writes to VRAM? Maybe by adding a per-IB flag that
would instruct the
kernel to flush or not flush HDP?
Marek
On Wed, Aug 5, 2015 at 4:18 AM, Michel Dänzer wrote:
> On 03.08.2015 21
From: Marek Olšák
v2: just clear the flag before the allocation
---
src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/src/gallium/dr
can we disable HDP flushes and other flushes for
USWC when we don't use write
combining and CPU writes to VRAM?
Nope, write combining happens in the CPU before the write request is
send over the PCIe bus.
The HDP is a (rather small) read/write cache in GPUs memory controller
as far as I know.
On Thu, Aug 6, 2015 at 6:36 AM, Thomas Helland
wrote:
> -NaN != NaN, and -Inf != Inf, so this should be safe.
>
What about -0.0 ? Does feq/fne treat both negative and positive zero as
equivalent?
--Aaron
> Found while working on my VRP pass.
>
> Shader-db results on my IVB:
> total instructi
Nevermind. Patch 2 answers that question in the commit message.
--Aaron
On Thu, Aug 6, 2015 at 10:25 AM, Aaron Watry wrote:
>
>
> On Thu, Aug 6, 2015 at 6:36 AM, Thomas Helland
> wrote:
>
>> -NaN != NaN, and -Inf != Inf, so this should be safe.
>>
>
> What about -0.0 ? Does feq/fne treat both
Iago Toral Quiroga writes:
> If we have spilled/unspilled a register in the current instruction, avoid
> emitting unspills for the same register in the same instruction or consecutive
> instructions following the current one as long as they keep reading the
> spilled
> register. This should allo
On Thu, Apr 2, 2015 at 12:30 PM, wrote:
> From: Mathias Froehlich
>
> Hi Brian,
>
> Thanks for the review!
> The Patch with unneeded parentheses removed.
> Ok, to push?
>
> Greetings
>
> Mathias
>
>
> This is the only real user of _WindowMap which has the depth
> buffer scaling multiplied in. Ma
I intend to remove nir_builder::cf_node_list, so I can't have this code
poking at it directly. The proper way is to set the insertion point and
then simply insert things there.
Signed-off-by: Kenneth Graunke
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 32
1 fi
I intend to remove nir_builder::cf_node_list, so I can't have this code
poking at it directly. The proper way is to set the insertion point and
then simply insert things there.
Signed-off-by: Kenneth Graunke
---
src/mesa/program/prog_to_nir.c | 22 +++---
1 file changed, 11 inse
It is now mostly working, and I've incorporated a bunch
of the feedback I got on the last posting. I promised to
have it out on the list by american office hours today,
so here it goes.
There is a massive issue with the compare_entries function.
I'm hacking on that atm, trying to come up with a so
The NIR cursor API is exactly what we want for the builder's insertion
point. This simplifies the API, the implementation, and is actually
more flexible as well.
This required a bit of reworking of TGSI->NIR's if/loop stack handling;
we now store cursors instead of cf_node_lists, for better or wo
On Thu, Aug 6, 2015 at 12:23 AM, Iago Toral wrote:
> On Wed, 2015-08-05 at 12:24 -0700, Connor Abbott wrote:
>> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
>> > The original GLSL IR intrinsics have been lowered to an internal
>> > version that accepts a block index and an offset ins
Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
needed to include no tiling at all, but the name
MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
confusion by replacing "ALLOC" with "TILING" in the identifiers.
---
Once reviewed, I plan to land the patches in the
On Wed, Aug 05, 2015 at 06:54:06PM -0700, Matt Turner wrote:
> Regression since commit 3a31876600, when tiling modes were moved into
> layout_flags.
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/
Signed-off-by: Jordan Justen
---
src/glsl/builtin_variables.cpp | 2 ++
src/glsl/shader_enums.h| 1 +
2 files changed, 3 insertions(+)
diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp
index 8fa7b19..5154b2f 100644
--- a/src/glsl/builtin_variables.cpp
+++ b/src
git://people.freedesktop.org/~jljusten/mesa cs-global-id-v1
http://patchwork.freedesktop.org/bundle/jljusten/cs-global-id-v1
For i965, these also depend on the texture sampling series:
http://patchwork.freedesktop.org/bundle/jljusten/cs%20texture%20sampling/
And the gl_LocalInvocationID series:
h
We lower this based on the extension spec formula:
gl_GlobalInvocationID =
gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID
Suggested-by: Kenneth Graunke
Signed-off-by: Jordan Justen
---
src/glsl/Makefile.sources | 1 +
src/glsl/ir_optimization.h | 1 +
src/gl
gl_GlobalInvocationID =
gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID
Therefore, if gl_GlobalInvocationID is used, then we mark these other
variables as being used. This prevents them from being considered dead
variables and being removed.
Signed-off-by: Jordan Justen
---
src/glsl/
On Thu, Aug 6, 2015 at 12:30 AM, Iago Toral wrote:
> On Wed, 2015-08-05 at 12:17 -0700, Connor Abbott wrote:
>> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
>> > ---
>> > src/glsl/nir/glsl_to_nir.cpp | 36
>> > src/glsl/nir/nir_intrinsics.h | 12
Why doesn't the lowering pass do that? Do you need to call it earlier?
Or does it rely on some information that only becomes available later?
On Thu, Aug 6, 2015 at 2:01 PM, Jordan Justen wrote:
> gl_GlobalInvocationID =
> gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID
>
> Therefore,
On Thu, Aug 06, 2015 at 11:03:55AM -0700, Matt Turner wrote:
> Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
> needed to include no tiling at all, but the name
> MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
> confusion by replacing "ALLOC" with "TILING" in t
By the way, there are a number of these derived system values...
instead of creating lowering for all of them, have you considered just
starting out *every* CS with the instructions to compute them and then
not having any lowering at all? The dead code elim should take care of
removing any that are
On Thu, Aug 6, 2015 at 11:14 AM, Ben Widawsky wrote:
> On Thu, Aug 06, 2015 at 11:03:55AM -0700, Matt Turner wrote:
>> Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
>> needed to include no tiling at all, but the name
>> MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We ca
On Thu, Aug 06, 2015 at 11:39:04AM -0700, Matt Turner wrote:
> On Thu, Aug 6, 2015 at 11:14 AM, Ben Widawsky wrote:
> > On Thu, Aug 06, 2015 at 11:03:55AM -0700, Matt Turner wrote:
> >> Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
> >> needed to include no tiling at all, but
2015-08-06 16:22 GMT+02:00 Boyan Ding :
> But, isn't -INT_MIN == INT_MIN?
>
> Regards,
> Boyan Ding
>
Yup. That's correct. Thanks for pointing that out.
That means this patch is wrong, so I NAK myself on this one.
Regards,
ThoHel
> 2015-08-06 19:36 GMT+08:00 Thomas Helland :
>> The same rational
Hi,
These are state tracker patches for HEVC decoding and other stuff. It was all
done by Christian König and Leo Liu as part of working on GCN 1.2 hardware
support.
I'm sending this mainly for non-AMD developers who would like to review it.
Marek
__
From: Leo Liu
v2 (chk): reorder the flush
Signed-off-by: Leo Liu
Signed-off-by: Christian König
Acked-by: Alex Deucher
---
src/gallium/state_trackers/omx/vid_enc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/state_trackers/omx/vid_enc.c
b/src/gallium/state_trackers/omx/v
From: Leo Liu
Put tasks to the FIFO queue for results
Signed-off-by: Leo Liu
Acked-by: Alex Deucher
Reviewed-by: Christian König
---
src/gallium/state_trackers/omx/vid_enc.c | 20 +++-
src/gallium/state_trackers/omx/vid_enc.h | 4 +++-
2 files changed, 22 insertions(+), 2 de
From: Leo Liu
Signed-off-by: Leo Liu
Acked-by: Alex Deucher
Reviewed-by: Christian König
---
src/gallium/include/pipe/p_video_enums.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/include/pipe/p_video_enums.h
b/src/gallium/include/pipe/p_video_enums.h
inde
From: Christian König
Signed-off-by: Christian König
Reviewed-by: Leo Liu
---
src/gallium/auxiliary/util/u_video.h | 7 +++
src/gallium/include/pipe/p_video_enums.h | 10 ++-
src/gallium/include/pipe/p_video_state.h | 105 +++
3 files changed, 120 insertions
From: Christian König
v2: fix return code
Signed-off-by: Christian König
Reviewed-by: Leo Liu
---
configure.ac | 2 +-
src/gallium/state_trackers/vdpau/decode.c| 122 ++-
src/gallium/state_trackers/vdpau/vdpau_private.h | 20
(Don't top quote)
On Thu, Aug 6, 2015 at 7:22 AM, Boyan Ding wrote:
> But, isn't -INT_MIN == INT_MIN?
In C (-INT_MIN) is undefined since it relies on behavior of signed
integer overflow.
In GLSL though, I think you're right. The spec says that addition
subtraction, and shift operations (weird t
2015-08-07 0:08 GMT+02:00 Matt Turner :
> (Don't top quote)
>
> On Thu, Aug 6, 2015 at 7:22 AM, Boyan Ding wrote:
>> But, isn't -INT_MIN == INT_MIN?
>
> In C (-INT_MIN) is undefined since it relies on behavior of signed
> integer overflow.
>
> In GLSL though, I think you're right. The spec says th
On Thu, Aug 6, 2015 at 6:08 PM, Matt Turner wrote:
> (Don't top quote)
>
> On Thu, Aug 6, 2015 at 7:22 AM, Boyan Ding wrote:
>> But, isn't -INT_MIN == INT_MIN?
>
> In C (-INT_MIN) is undefined since it relies on behavior of signed
> integer overflow.
>
> In GLSL though, I think you're right. The
2015-08-06 19:22 GMT+02:00 Thomas Helland :
> It is now mostly working, and I've incorporated a bunch
> of the feedback I got on the last posting. I promised to
> have it out on the list by american office hours today,
> so here it goes.
>
> There is a massive issue with the compare_entries functio
Kenneth Graunke writes:
> The NIR cursor API is exactly what we want for the builder's insertion
> point. This simplifies the API, the implementation, and is actually
> more flexible as well.
>
> This required a bit of reworking of TGSI->NIR's if/loop stack handling;
> we now store cursors inste
On Thu, Aug 6, 2015 at 4:36 AM, Thomas Helland
wrote:
> -NaN != NaN, and -Inf != Inf, so this should be safe.
> Found while working on my VRP pass.
>
> Shader-db results on my IVB:
> total instructions in shared programs: 1698267 -> 1698067 (-0.01%)
> instructions in affected programs: 15785 -
On Thu, Aug 6, 2015 at 4:36 AM, Thomas Helland
wrote:
> The positive and negative value of a float can only
> be equal to each other if it is -0.0f and 0.0f.
> This is safe for Nan and Inf, as -Nan != Nan, and -Inf != Inf
> This gives no changes in my shader-db
>
> Signed-off-by: Thomas Helland
>
On Thursday, August 06, 2015 10:15:24 AM Kenneth Graunke wrote:
> -static inline void
> -nir_builder_insert_after_instr(nir_builder *build, nir_instr *after_instr)
> +nir_builder_instr_insert(nir_builder *build, nir_instr *instr)
> {
> - build->cf_node_list = NULL;
> - build->before_instr = NU
So, I was sort of imagining that we'd want to go a little farther with
this, and make nir_instr_insert_before/after_* a wrapper around a
cursor based API just called "nir_instr_insert". Then
nir_builder_instr_insert() would become even simpler, since it would
just call nir_instr_insert() and then p
Passing NULL to C11 threads functions isn't safe, so there's no need for
our implementation to handle it. Cuts about 1k of .text.
text data bss dec hex filename
5009514 19844026328 5234282 4fde6a i965_dri.so before
5008346 19844026328 5233114 4fd9da i965_
---
src/mesa/main/mtypes.h | 1 -
src/mesa/main/samplerobj.c | 16 +++-
2 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2adfae2..fcc527f 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1153,
We were locking the Shared->Mutex and then using calling functions like
_mesa_HashInsert that do additional per-hash-table locking internally.
Instead just lock each hash-table's mutex and use functions like
_mesa_HashInsertLocked and the new _mesa_HashRemoveLocked.
In order to do this, we need t
---
src/mesa/main/fbobject.c | 1 -
src/mesa/main/mtypes.h | 1 -
src/mesa/main/renderbuffer.c | 15 +++
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index cc342c2..918889e 100644
--- a/src/mesa/main/fbo
Patches 1-11 improve performance of SynMark OglBatch7 by 6.29586% +/- 0.277734%
(n=337) and OglMultithread by 1.12564% +/- 0.424038% (n=209). I haven't
benchmarked individual patches because I'd like to not waste all that time if I
get review feedback that requires me to change things. :)
Patches
---
src/mesa/main/hash.c | 19 +++
src/mesa/main/hash.h | 2 ++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/hash.c b/src/mesa/main/hash.c
index 315b5d6..aa1c6a1 100644
--- a/src/mesa/main/hash.c
+++ b/src/mesa/main/hash.c
@@ -328,8 +328,8 @@ _mesa
---
src/mesa/main/arrayobj.c| 4 +---
src/mesa/main/framebuffer.c | 4 +---
src/mesa/main/pipelineobj.c | 4 +---
src/mesa/main/shaderobj.c | 8 ++--
4 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index f581e4c..da6757e
---
src/mesa/main/arrayobj.c | 8
src/mesa/main/bufferobj.c| 17 -
src/mesa/main/renderbuffer.c | 2 --
src/mesa/main/samplerobj.c | 8
src/mesa/main/shaderobj.c| 12
src/mesa/program/program.c | 14 --
6 files changed,
---
src/mesa/main/mtypes.h | 1 +
src/mesa/main/samplerobj.c | 10 ++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 4e00fb6..962dad9 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1153,6 +1153
"Container objects" like vertex array objects, framebuffer objects, and
pipeline objects are not shared between contexts, so they require no
locking.
---
src/mesa/main/arrayobj.c| 6 --
src/mesa/main/fbobject.c| 9 -
src/mesa/main/framebuffer.c | 9 -
src/mesa/main/mtyp
---
src/mesa/main/mtypes.h | 1 -
src/mesa/program/program.c | 15 +++
2 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index fcc527f..c597ccc 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2095,7
---
src/mesa/main/bufferobj.c | 17 +++--
src/mesa/main/mtypes.h| 1 -
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index cc035ff..78af229 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.
---
src/mesa/main/mtypes.h | 1 -
src/mesa/main/texobj.c | 17 +++--
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index b8329a0..43d2f67 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1180,7 +1180
---
src/mesa/main/mtypes.h | 1 +
src/mesa/program/program.c | 19 +++
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 962dad9..19f65ee 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -20
On Tuesday, July 21, 2015 07:54:14 PM Connor Abbott wrote:
> Back when I was getting NIR up and running, I created a bunch of
> functions that dealt with modifying control flow; they allowed you to
> remove control flow nodes (if's, loops, and basic blocks) as well as
> insert newly-created control
Hi All,
Are there any news about the status of the r600g driver for PowerPC? All
PowerPC users can only use Radeon HD6XXX graphics cards and lower cards
for 3D acceleration. It isn't possible to activate 3D acceleration on
Radeon HD7XXX and higher.
Rgds,
Christian
On 05 August 2015 at 08:4
Yes, yes... I know this is an expert group but I searched the whole web,
sent a few
emails and nothing... this is driving me mad...
The point is driDriverAPI is initialized in
src/gallium/state_trackers/dri/drm/dri2.c but
this variable is only used in src/mesa/drivers...
mesa3d web site states th
Reviewed-by: Timothy Arceri
On Thu, 2015-08-06 at 17:10 -0700, Matt Turner wrote:
> ---
> src/mesa/main/arrayobj.c | 8
> src/mesa/main/bufferobj.c| 17 -
> src/mesa/main/renderbuffer.c | 2 --
> src/mesa/main/samplerobj.c | 8
> src/mesa/main/shade
On Thu, 2015-08-06 at 17:10 -0700, Matt Turner wrote:
> Passing NULL to C11 threads functions isn't safe, so there's no need for
> our implementation to handle it. Cuts about 1k of .text.
>
>text data bss dec hex filename
> 5009514 19844026328 5234282 4fde6a i965_
It's simply the first nir_cf_node in the nir_function_impl::body list,
which is easy enough to access - we don't to store a pointer to it
explicitly. Removing it means we don't need to maintain the pointer
when, say, splitting the start block when modifying control flow.
Thanks to Connor Abbott f
On 07.08.2015 00:17, Christian König wrote:
>> can we disable HDP flushes and other flushes for USWC
What other flushes are you thinking of? If you mean the mb() in the
kernel which flushes the write-combining buffers, that's also needed for
the register writes regardless of write-combining.
>>
On 07/31/2015 04:18 PM, Lofstedt, Marta wrote:
Thanks Tapani,
However,
For patch 9 there is a V3 for which I can't see any new objections:
http://patchwork.freedesktop.org/patch/51879/
This looks good to me.
If you have any new ones could you please clarify.
My interpretation of the comm
On Thu, 2015-08-06 at 11:06 -0700, Connor Abbott wrote:
> On Thu, Aug 6, 2015 at 12:30 AM, Iago Toral wrote:
> > On Wed, 2015-08-05 at 12:17 -0700, Connor Abbott wrote:
> >> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga
> >> wrote:
> >> > ---
> >> > src/glsl/nir/glsl_to_nir.cpp | 36 +
On Thu, 2015-08-06 at 18:27 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > If we have spilled/unspilled a register in the current instruction, avoid
> > emitting unspills for the same register in the same instruction or
> > consecutive
> > instructions following the current one
Hi,
On Thursday, August 06, 2015 12:32:18 Ilia Mirkin wrote:
> > @@ -182,6 +187,13 @@ _tnl_InvalidateState( struct gl_context *ctx, GLuint
> > new_state )
> > }
> >}
> > }
> > +
> > + if (new_state & (_NEW_VIEWPORT | _NEW_BUFFERS)) {
> > + double scale[3], translate[3
On 07.08.2015 00:11, Marek Olšák wrote:
> From: Marek Olšák
>
> v2: just clear the flag before the allocation
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
> src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
> src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
> 3 fil
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