On 07.08.2015 00:17, Christian König wrote: >> can we disable HDP flushes and other flushes for USWC
What other flushes are you thinking of? If you mean the mb() in the kernel which flushes the write-combining buffers, that's also needed for the register writes regardless of write-combining. >> when we don't use write combining and CPU writes to VRAM? > Nope, write combining happens in the CPU before the write request is > send over the PCIe bus. > > The HDP is a (rather small) read/write cache in GPUs memory controller > as far as I know. Yes, that's my understanding as well. In theory it might be possible to track if there have been any CPU writes to VRAM since the last HDP flush, but it might be a lot of effort for uncertain gain. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
