Signed-off-by: Tapani Pälli
---
src/compiler/glsl/glsl_parser_extras.cpp | 26 ++
src/util/disk_cache.c| 5 +++--
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
b/src/compiler/glsl/glsl_parser
Patch disables EGL_ANDROID_blob_cache and sets own get/set
cache functions internally, this makes any EGL app to utilize
cache automatically.
Signed-off-by: Tapani Pälli
---
src/egl/drivers/dri2/egl_dri2.c | 3 --
src/egl/main/eglapi.c | 77 +
2
Signed-off-by: Tapani Pälli
---
src/egl/drivers/dri2/egl_dri2.c | 43 +
src/egl/drivers/dri2/egl_dri2.h | 4
src/egl/main/eglapi.c | 29 +++
src/egl/main/eglapi.h | 4
src/egl/main/egldisplay.h |
Cache set and get are called in similar fashion as what is happening
with disk cache. Functionality requires ARB_get_program_binary and
EGL_ANDROID_blob_cache support.
Signed-off-by: Tapani Pälli
---
src/mesa/Makefile.sources | 2 +
src/mesa/main/program_blob_cache.c | 141 +++
Signed-off-by: Tapani Pälli
---
src/mesa/drivers/dri/i965/intel_screen.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 3e016b5b7a..01752700cf 100644
--- a/src/mesa/drivers/dri/i965
Original reason why this was enabled was to get sha1 functionality
which used to be guarded by shader cache define. Instead of disk
cache, Android will utilize EGL_ANDROID_blob_cache for caching.
Signed-off-by: Tapani Pälli
---
Android.common.mk | 1 -
1 file changed, 1 deletion(-)
diff --git a
Hi;
This series enables EGL_ANDROID_blob_cache extension. Overall approach
is to skip linking of shader programs by utilizing functionality of
ARB_get_program_binary extension.
2 first patches are separate and could be pushed in, rest is RFC and
last patch is additional debug patch that makes Me
Patch moves existing functionality from shader_cache_read_program_metadata
to a helper function.
Signed-off-by: Tapani Pälli
---
src/compiler/Makefile.sources | 1 +
src/compiler/glsl/meson.build | 1 +
src/compiler/glsl/program.cpp | 88 ++
s
Signed-off-by: Tapani Pälli
---
include/GL/internal/dri_interface.h | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index 34a5c9fb01..de367d8f77 100644
--- a/include/GL/intern
These will be utilized by EGL_ANDROID_blob_cache extension.
Signed-off-by: Tapani Pälli
---
src/mesa/main/mtypes.h | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index a4f1e78f41..073b6c8536 100644
--- a/src/mesa/main/mtypes.
Signed-off-by: Tapani Pälli
---
src/compiler/glsl/shader_cache.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/shader_cache.h b/src/compiler/glsl/shader_cache.h
index c0598f37e8..eeefb3aeb2 100644
--- a/src/compiler/glsl/shader_cache.h
+++ b/src/compi
On 8 January 2018 at 17:12, Dave Airlie wrote:
> On 6 January 2018 at 03:41, Gert Wollny wrote:
>> Am Freitag, den 05.01.2018, 18:18 +0100 schrieb Gert Wollny:
>>>
>>> Well, I have tested some piglits now and the behaviour is quite
>>> wired:
>>>
>>> When I run nop as the very first piglit after
mmm... you're right, I'l add that too. Thanks!
On Mon, 2018-01-08 at 08:23 -0800, Jason Ekstrand wrote:
> This looks good to me. However, I think we'll need to do the same
> thing for LowerTESPatchVerticesIn and they can probably be handled by
> the same pass.
>
> On Mon, Jan 8, 2018 at 5:13 AM,
On 01/08/2018 06:59 PM, Marek Olšák wrote:
From: Marek Olšák
This is unused because it's for libGL/libEGL, not drivers.
IMO this is not enough, you would need to also remove the query for this
as well (driQueryOptionb in intel_screen.c), otherwise we hit assertion.
Maybe just set bool allo
On Mon, Jan 8, 2018 at 7:25 PM, Ilia Mirkin wrote:
> On Mon, Jan 8, 2018 at 4:18 PM, Rob Herring wrote:
>> Many of the functions declared in tgsi_build.h return structs (not struct
>> pointers). Therefore the full struct definitions are needed to avoid
>> warnings or errors:
>>
>> In file include
From: Roland Scheidegger
For eg/cm, the r600_gb_backend_map will always be 0. I assume this is a bug
in the drm kernel driver, as it just just never fills the information in.
I am not entirely sure if the map is supposed to be needed for these chips,
since unlike on r600/r700 the value calculated
From: Roland Scheidegger
Juniper really has a maximum of 4 RBEs (16 pixels). However, predication
always locks up on my HD 5750, and through experiments it looks like if we're
pretending it has a maximum of 8, with 4 disabled, it works correctly.
My conclusion would be that there's a bug (likely
From: Roland Scheidegger
The logic had two fatal flaws which completely killed the default value.
1) drm will overwrite the value anyway even if the chip can't be handled
2) the default value logic is relying on num_render_backends, which was
filled in later.
Luckily noone is relying on it, but i
https://bugs.freedesktop.org/show_bug.cgi?id=104214
--- Comment #24 from Sven ---
I'm sorry but multiple issue seem to be discussed here:
- dota crashing on startup (seems to be fixed)
- dota crashing on alt+tab (not yet fixed)
- mpv crashing (not yet fixed)
The alt+tab crash I'm seeing seems t
On Mon, Jan 8, 2018 at 4:18 PM, Rob Herring wrote:
> Many of the functions declared in tgsi_build.h return structs (not struct
> pointers). Therefore the full struct definitions are needed to avoid
> warnings or errors:
>
> In file included from
> src/gallium/drivers/nouveau/codegen/nv50_ir_from_
Matt Turner writes:
> This reverts commit 2d0457203871c843ebfc90fb895b65a9b14cd9bb.
Reviewed-by: Scott D Phillips
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Matt Turner writes:
> Some cases weren't handled, such as stride 4 which is needed for 64-bit
> operations. Presumably fixes the assertion failure mentioned in commit
> 2d0457203871 (Revert "i965/fs: Use align1 mode on ternary instructions
> on Gen10+") but who can really say since the commit neg
On Mon, Jan 8, 2018 at 7:25 PM, Connor Abbott wrote:
> In order to reduce moves when coalescing multiple registers into a
> larger register, RA will try to coalesce MERGE instructions with their
> definitions. For example, for something like this in GLSL:
>
> uint a = ...;
> uint b = ...;
> uint64
On Mon, Jan 08, 2018 at 04:06:53PM -0800, Jason Ekstrand wrote:
> On Fri, Dec 15, 2017 at 2:53 PM, Rafael Antognolli
> > wrote:
>
> On gen10+, if surface->clear_color_addr is present, use it directly
> intead of copying it to the surface state.
>
> Signed-off-by: Rafael Antognolli
On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
>
> On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > On Gen10+, if we use the clear state address field in the surface state
> > instead of the c
On Mon, Jan 08, 2018 at 03:14:54PM -0800, Nanley Chery wrote:
> On Fri, Dec 15, 2017 at 02:53:32PM -0800, Rafael Antognolli wrote:
> > Similarly to vulkan where we store the clear value in the aux surface,
> > we can do the same in GL.
> >
> > Signed-off-by: Rafael Antognolli
> > ---
> > src/mes
In order to reduce moves when coalescing multiple registers into a
larger register, RA will try to coalesce MERGE instructions with their
definitions. For example, for something like this in GLSL:
uint a = ...;
uint b = ...;
uint64 x = packUint2x32(a, b);
The compiler will try to coalesce x with
On Fri, Dec 15, 2017 at 2:53 PM, Rafael Antognolli <
rafael.antogno...@intel.com> wrote:
> On gen10+, if surface->clear_color_addr is present, use it directly
> intead of copying it to the surface state.
>
> Signed-off-by: Rafael Antognolli
> ---
> src/intel/blorp/blorp_genX_exec.h | 12
On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
> On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > On Gen10+, if we use the clear state address field in the surface state
> > instead of the clear color directly, there's a restriction that the
> > address must point to th
On Mon, Jan 8, 2018 at 2:29 PM, Nanley Chery wrote:
> On Fri, Dec 15, 2017 at 02:53:29PM -0800, Rafael Antognolli wrote:
> > gen10 can emit the clear color by setting it on a buffer somewhere, and
> > then adding only the address to the surface state.
> >
> > This commit add support for that on i
On Fri, Dec 15, 2017 at 2:53 PM, Rafael Antognolli <
rafael.antogno...@intel.com> wrote:
> genxml does not support having two address fields with different names
> but same position in the state struct. Both "Clear Color Address"
> and "Clear Depth Address Low" mean the same thing, only for differ
On Fri, Dec 15, 2017 at 02:53:28PM -0800, Rafael Antognolli wrote:
> genxml does not support having two address fields with different names
> but same position in the state struct. Both "Clear Color Address"
> and "Clear Depth Address Low" mean the same thing, only for different
> surface types.
>
On Fri, Dec 15, 2017 at 02:53:35PM -0800, Rafael Antognolli wrote:
> This warning showed up after aux_bo started being used inside
>
> if (use_clear_address) {...
>
> But use_clear_address depends on aux_surf being not null, in which case
> aux_bo would also be set. Make the compiler happy anyway
On Fri, Dec 15, 2017 at 02:53:32PM -0800, Rafael Antognolli wrote:
> Similarly to vulkan where we store the clear value in the aux surface,
> we can do the same in GL.
>
> Signed-off-by: Rafael Antognolli
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 +
> 1 f
Reviewed-by: Timothy Arceri
On 09/01/18 02:41, Karol Herbst wrote:
From: Rob Clark
This was handled for VS, but not for GS.
Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_tra
On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> On Gen10+, if we use the clear state address field in the surface state
> instead of the clear color directly, there's a restriction that the
> address must point to the lower part of a 64 byte cache-line.
>
> Signed-off-by: Rafa
On Thu, Jan 04, 2018 at 11:36:48AM -0800, Kenneth Graunke wrote:
> Apparently, Geminilake requires you to whack a chicken bit to select
> either compute or tessellation mode for barriers. The recommendation
> is to switch between them at PIPELINE_SELECT time.
>
> We may not need to do this all th
On Monday, 2018-01-08 21:58:16 +, Emil Velikov wrote:
> On 8 January 2018 at 12:00, Eric Engestrom wrote:
> > On Thursday, 2018-01-04 14:10:52 +, Emil Velikov wrote:
> >> Hello list,
> >>
> >> The release candidate for Mesa 17.3.2 is now available. Currently we have:
> >> - 13 queued
> >>
On Fri, Dec 15, 2017 at 02:53:29PM -0800, Rafael Antognolli wrote:
> gen10 can emit the clear color by setting it on a buffer somewhere, and
> then adding only the address to the surface state.
>
> This commit add support for that on isl_surf_fill_state, and if that is
> requested, skip setting th
On Mon, Jan 8, 2018 at 10:33 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> On 17/12/17 05:46, Jason Ekstrand wrote:
>
>> ---
>> src/compiler/spirv/spirv_to_nir.c | 17 ++---
>> 1 file changed, 10 insertions(+), 7 deletions(-)
>>
>> diff --git a/src/compiler/spirv/s
https://bugs.freedesktop.org/show_bug.cgi?id=104214
Mark Janes changed:
What|Removed |Added
CC||thellst...@vmware.com
--- Comment #23 from
On 8 January 2018 at 12:00, Eric Engestrom wrote:
> On Thursday, 2018-01-04 14:10:52 +, Emil Velikov wrote:
>> Hello list,
>>
>> The release candidate for Mesa 17.3.2 is now available. Currently we have:
>> - 13 queued
>> - 18 nominated (outstanding)
>> - and 0 rejected patches
>>
>>
>> In
Cleaner.
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 877f68ee7cf..b4fcd92b6bd 100644
--- a/src/mesa/d
Having a boolean for "we're using malloc'd shadow copies for all
buffers" is cleaner than having a cpu_map pointer for each. It was
okay when we had one buffer, but this is more obvious.
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 39
Growing the batch/state buffer is a lot more dangerous than I thought.
A number of places emit multiple state buffer sections, and then write
data to the returned pointer, or save a pointer to brw->batch.state.bo
and then use it in relocations. If each call can grow, this can result
in stale map
Now that we have two of these, we're duplicating a bunch of this logic.
The next commit will add more logic, which would make the duplication
seem worse.
This ends up setting EXEC_OBJECT_CAPTURE on the batch, which isn't
necessary (it's already captured), but it should be harmless.
---
src/mesa/d
On 01/06/2018 12:12 PM, Marek Olšák wrote:
From: Marek Olšák
SGPRS: 2170102 -> 2158430 (-0.54 %)
VGPRS: 1645656 -> 1641516 (-0.25 %)
Spilled SGPRs: 9078 -> 8810 (-2.95 %)
Spilled VGPRs: 130 -> 114 (-12.31 %)
Scratch size: 1508 -> 1492 (-1.06 %) dwords per thread
Code Size: 52094872 -> 5269254
We also need to update spirv.core.grammar.json at the same time. I've gone
ahead and pulled the latest and squashed it into your patch. I also added
Reviewed-by: Jason Ekstrand
and pushed. Thanks!
On Mon, Jan 8, 2018 at 10:46 AM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrot
On 01/06/2018 12:12 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/amd/common/ac_llvm_build.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 164f310..ed00d20 100644
--- a/src/amd/common/ac_llvm
Many of the functions declared in tgsi_build.h return structs (not struct
pointers). Therefore the full struct definitions are needed to avoid
warnings or errors:
In file included from
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:23:
external/mesa3d/src/gallium/auxiliary/tgsi/tgsi_bu
9-10:
Reviewed-by: Samuel Pitoiset
On 01/06/2018 12:12 PM, Marek Olšák wrote:
From: Marek Olšák
State trackers must use a user buffer or const_uploader,
or set pipe_resource::flags same as const_uploader->flags.
---
src/gallium/drivers/radeonsi/si_descriptors.c | 6 ++
1 file changed,
Patches 5-8 are:
Reviewed-by: Samuel Pitoiset
On 01/06/2018 12:12 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 42 +++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 28 ++-
src/gallium/winsys/radeon
On 01/06/2018 12:12 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/auxiliary/pipebuffer/pb_bufmgr_cache.c | 2 +-
src/gallium/auxiliary/pipebuffer/pb_cache.c| 20
src/gallium/auxiliary/pipebuffer/pb_cache.h| 6 --
src/gallium/winsys/am
I have a nit for patch 6 and a question on patch 9, maybe there is a
thing on change on that one.
Otherwise this is :
Reviewed-by: Lionel Landwerlin
On 17/12/17 05:46, Jason Ekstrand wrote:
This series is another 11 patches in the direction of improving SPIR-V
error messages and validation.
---
src/compiler/spirv/spirv.h | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/spirv.h b/src/compiler/spirv/spirv.h
index 61559a1c9c..233dc6d691 100644
--- a/src/compiler/spirv/spirv.h
+++ b/src/compiler/spirv/spirv.h
@@ -1,5 +1,5
On 17/12/17 05:46, Jason Ekstrand wrote:
---
src/compiler/spirv/spirv_to_nir.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 83c75c7..ffea442 100644
--- a/src/compiler/spirv/sp
On 17/12/17 05:46, Jason Ekstrand wrote:
---
src/compiler/spirv/spirv_to_nir.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 208ec95..d65c0d0 100644
--- a/src/compiler/spirv/spirv_to_nir.c
From: Marek Olšák
This is unused because it's for libGL/libEGL, not drivers.
---
src/mesa/drivers/dri/common/dri_util.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index d4fba0b..e6a7d23 100644
--- a/src/
The driver options are the defaults. drirc overrides the defaults.
~/.drirc overrides both the defaults and drirc. Environment variables
override everything.
Marek
On Mon, Jan 8, 2018 at 9:37 AM, Tapani Pälli wrote:
>
>
> On 01/08/2018 01:55 AM, Steven Newbury wrote:
>>
>> On Fri, 2017-12-15 at
On Mon, Jan 8, 2018 at 8:40 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Hmm... The email subject says it's the v3.
> Am I missing something? (it's at the top of the list in my client, so it's
> probably the last you sent).
>
Nope, it's my e-mail client that's failing me... Sor
https://patchwork.freedesktop.org/series/35979/
On Mon, Jan 8, 2018 at 8:40 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Hmm... The email subject says it's the v3.
> Am I missing something? (it's at the top of the list in my client, so it's
> probably the last you sent).
>
>
>
On Mon, 2018-01-01 at 22:49 +0100, Igor Gnatenko wrote:
> ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
> `u_thread_setname':
> /builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:66:
> undefined reference to `pthread_setname_np'
> ../../src/util/.libs
Hmm... The email subject says it's the v3.
Am I missing something? (it's at the top of the list in my client, so
it's probably the last you sent).
On 08/01/18 16:38, Jason Ekstrand wrote:
There's a v3 of this
On Mon, Jan 8, 2018 at 8:36 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.
There's a v3 of this
On Mon, Jan 8, 2018 at 8:36 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> This series is :
>
> Reviewed-by: Lionel Landwerlin
>
>
> On 04/01/18 01:34, Jason Ekstrand wrote:
>
>> ---
>> src/compiler/spirv/spirv_to_nir.c | 28
>>
This series is :
Reviewed-by: Lionel Landwerlin
On 04/01/18 01:34, Jason Ekstrand wrote:
---
src/compiler/spirv/spirv_to_nir.c | 28
src/compiler/spirv/vtn_private.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/s
This looks good to me. However, I think we'll need to do the same thing
for LowerTESPatchVerticesIn and they can probably be handled by the same
pass.
On Mon, Jan 8, 2018 at 5:13 AM, Iago Toral Quiroga
wrote:
> Intel was the only user, now it does this in NIR.
> ---
> src/compiler/glsl/builtin
On Mon, Jan 8, 2018 at 5:13 AM, Iago Toral Quiroga
wrote:
> ---
> src/intel/compiler/brw_nir.h | 2 ++
> src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 29
> ++
> 2 files changed, 31 insertions(+)
>
> diff --git a/src/intel/compiler/brw_nir.h b/src/in
For the series:
Reviewed-by: Marek Olšák
Marek
On Mon, Jan 8, 2018 at 6:07 AM, Timothy Arceri wrote:
> Fixes the following piglit tests in radeonsi:
>
> vs-tcs-tes-tessinner-tessouter-inputs-quads.shader_test
> vs-tcs-tes-tessinner-tessouter-inputs-tris.shader_test
> vs-tes-tessinner-tessouter
From: Rob Clark
This was handled for VS, but not for GS.
Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_gs*
s
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 48e2920a15..9864f9366d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/commo
Please, could someone take a look at this patch? Thanks in advance.
J.A.
On Mon, 2017-12-04 at 17:35 +0100, Juan A. Suarez Romero wrote:
> According with OpenGL GLSL 4.20 spec, section 4.3.9, page 57:
>
>"It is a link-time error if any particular shader interface
> contains:
>
Ignore the 1/4 in the subject, that was my mistake, this is a single
patch.
Iago
On Mon, 2018-01-08 at 13:57 +0100, Iago Toral Quiroga wrote:
> From the Vulkan spec with KHX extensions:
>
> "If queries are used while executing a render pass instance that
> has
> multiview enabled, the query
Intel was the only user, now it does this in NIR.
---
src/compiler/glsl/builtin_variables.cpp | 13 +
src/mesa/drivers/dri/i965/brw_context.c | 1 -
src/mesa/main/mtypes.h | 1 -
3 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/src/compiler/glsl/builtin
---
src/intel/compiler/brw_nir.h | 2 ++
src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 29 ++
2 files changed, 31 insertions(+)
diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 809d4c338d..a29d858806 100644
--- a/src/inte
We want this here instead of nir_lower_system_values because for
Vulkan we don't want this lowering to take place.
---
src/mesa/drivers/dri/i965/brw_program.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.
This version adds the same behavior for vkCmdWriteTimestamp, which has
similar interactions with multiview for our case.
Iago
On Mon, 2018-01-08 at 13:57 +0100, Iago Toral Quiroga wrote:
> From the Vulkan spec with KHX extensions:
>
> "If queries are used while executing a render pass instance
From the Vulkan spec with KHX extensions:
"If queries are used while executing a render pass instance that has
multiview enabled, the query uses N consecutive query indices
in the query pool (starting at query) where N is the number of bits
set in the view mask in the subpass the query
On Thursday, 2018-01-04 14:10:52 +, Emil Velikov wrote:
> Hello list,
>
> The release candidate for Mesa 17.3.2 is now available. Currently we have:
> - 13 queued
> - 18 nominated (outstanding)
> - and 0 rejected patches
>
>
> In the current queue we have:
>
> Multiple fixes in the RADV
thanks for the three first patches. They seem like they could make it
a bit easier for me to implement this in nouveau, but I don't know
when I will have the chance to look into that, because I want to fix
64 bit stuff in general first.
On Mon, Jan 8, 2018 at 1:35 AM, Timothy Arceri wrote:
> This
https://bugs.freedesktop.org/show_bug.cgi?id=103538
Daniel Stone changed:
What|Removed |Added
Summary|vkDestroySwapchain causes |vkDestroySwapchain causes
Reviewed-by: Lionel Landwerlin
On 08/01/18 06:33, Kenneth Graunke wrote:
This will make aubinator_error_decode decode them properly.
---
src/intel/genxml/gen10.xml | 2 ++
src/intel/genxml/gen75.xml | 2 ++
src/intel/genxml/gen8.xml | 2 ++
src/intel/genxml/gen9.xml | 2 ++
4 files chan
Reviewed-by: Bas Nieuwenhuizen
On Fri, Jan 5, 2018 at 5:26 PM, Samuel Pitoiset
wrote:
> VGPR1 is only needed for topology that needs 3 offsets like
> triangles or quads.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_shader.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 delet
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Thu, Jan 4, 2018 at 6:39 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_device.c | 2 ++
> src/amd/vulkan/radv_private.h | 1 +
> src/amd/vulkan/radv_shader.c | 5 -
> 3 files changed, 7 insertion
On 01/05/2018 08:32 PM, Marek Olšák wrote:
Here: https://cgit.freedesktop.org/~mareko/mesa/log/?h=master
LLVM: https://reviews.llvm.org/D41663
Thanks! Looks good to me, no performance changes and no regressions as well.
This patch is:
Reviewed-by: Samuel Pitoiset
Marek
On Fri, Jan 5, 2
Just wanted to clarify this one thing here, otherwise I think Rob/krh
covered it all.
On Thu, Dec 28, 2017 at 10:24:38AM -0800, Miguel Angel Vico wrote:
> Daniel Vetter wrote:
> > I think in the interim figuring out how to expose kms capabilities
> > better (and necessarily standardizing at least
Reviewed-by: Samuel Pitoiset
On 01/08/2018 07:45 AM, Timothy Arceri wrote:
nir_to_llvm_context will always be NULL for radeonsi so we need
work around this.
---
src/amd/common/ac_nir_to_llvm.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/src/amd/commo
Hello Michael,
Finally I found some free time to spent on this.
Can you please give me a small example on how I can get the device_ids ?
Currently to retrieve the available driver options I'm doing something like
this:
1 - Count the number of screens using "ScreenCount" function from Xlib.
2 -
On 01/08/2018 01:55 AM, Steven Newbury wrote:
On Fri, 2017-12-15 at 23:04 +0100, Mario Kleiner wrote:
Some clients may not like RGB10X2 and RGB10A2 fbconfigs and
visuals. Add a new driconf option 'allow_rgb10_configs' to
allow per application enable/disable.
The option defaults to enabled.
v
On 01/06/2018 01:36, Dylan Baker wrote:
Quoting Greg V (2017-12-31 08:55:25)
---
src/gallium/drivers/radeonsi/meson.build | 2 +-
src/mesa/meson.build | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/meson.build
b/src/gall
On 01/06/2018 01:06, Dylan Baker wrote:
Quoting Greg V (2017-12-31 08:55:22)
+is_like_linux = host_machine.system() == 'linux' or
host_machine.system().contains('bsd') # FIXME: illumos?
This won't cover dragonflybsd, which is just 'dragonfly'
I think something like this would be better:
is_l
On 01/06/2018 01:27, Dylan Baker wrote:
We absolutely can't merge this as-is, it will break all of the these since
they'll end up linking the backend and frontend, which we're not supposed to do.
The bug you linked to has nothing to do with the problem you describe either,
that issue is that `de
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