On Tuesday, October 10, 2017 6:55:14 PM PDT Ilia Mirkin wrote:
> Do you need to initialize to null? Haven't looked at context, just guessing
> based on your description.
Yikes, yes, fixed locally. Thanks!
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On Tue, Oct 10, 2017 at 1:10 PM, Jason Ekstrand
wrote:
> On Tue, Oct 10, 2017 at 9:16 AM, Connor Abbott
> wrote:
>
>> I'm a little nervous about this, because really, the only solution to
>> this problem is to ignore all non-WE_all definitions of all variables
>> in liveness analysis. For exampl
The same line of code is a few lines above.
---
src/amd/vulkan/radv_pipeline_cache.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline_cache.c
b/src/amd/vulkan/radv_pipeline_cache.c
index bced425966..714edf03a4 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/
This is the drivers on-disk cache intended to be used as a
fallback as opposed to the pipeline cache provided by apps.
---
src/amd/vulkan/radv_device.c | 13 +
src/amd/vulkan/radv_private.h | 6 ++
src/util/disk_cache.h | 15 +++
3 files changed, 34 insertions
---
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
src/amd/vulkan/radv_debug.c | 2 +-
src/amd/vulkan/radv_device.c | 4 +---
src/amd/vulkan/radv_image.c | 4 ++--
src/amd/vulkan/radv_meta_clear.c | 4 ++--
src/amd/vulkan/radv_pipeline.c | 4 ++--
src/amd/vulkan/r
If the app provided in-memory pipeline cache doesn't yet contain
what we are looking for, or it doesn't provide one at all then we
fallback to the on-disk cache.
---
src/amd/vulkan/radv_pipeline_cache.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.
This condition was triggered by piglit's draw-e
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.
This condition was triggered by piglit's draw-e
On 11/10/17 11:30, Kenneth Graunke wrote:
On Tuesday, October 10, 2017 4:57:08 PM PDT Timothy Arceri wrote:
From: Kenneth Graunke
ARB_enhanced_layouts enables us to pack array varyings with
non-arrays types e.g.
layout(location = 0) in vec3 a[6];
layout(location = 0, component = 3) in float b
Reviewed-by: Gurchetan Singh
On Tue, Oct 10, 2017 at 5:46 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> Clarify when headers can be updated here.
>
> Signed-off-by: Dave Airlie
> ---
> include/drm-uapi/README | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm-uapi/README
From: Dave Airlie
Clarify when headers can be updated here.
Signed-off-by: Dave Airlie
---
include/drm-uapi/README | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm-uapi/README b/include/drm-uapi/README
index d67fb562..27de91c 100644
--- a/include/drm-uapi/README
+++ b/include
On Tuesday, October 10, 2017 4:57:08 PM PDT Timothy Arceri wrote:
> From: Kenneth Graunke
>
> ARB_enhanced_layouts enables us to pack array varyings with
> non-arrays types e.g.
>
> layout(location = 0) in vec3 a[6];
> layout(location = 0, component = 3) in float b;
>
> With this change we calc
The original implementation allocated a new BO here, but we decided to
switch to intel_upload_space, which returns a reference to the current
upload BO. We accidentally kept the brw_bo_alloc, even though it's no
longer necessary - intel_upload_space will immediately unreference it,
causing us to a
On 11/10/17 10:50, Dave Airlie wrote:
From: Dave Airlie
With the ssao demo from Vulkan demos:
radv/rx480: 440->440fps
anv/haswell: 24->34 fps
The demo does a 0->32 loop across a ubo with 32 members.
Signed-off-by: Dave Airlie
Reviewed-by: Timothy Arceri
---
src/compiler/nir/nir_opt_lo
From: Kenneth Graunke
ARB_enhanced_layouts enables us to pack array varyings with
non-arrays types e.g.
layout(location = 0) in vec3 a[6];
layout(location = 0, component = 3) in float b;
With this change we calculate the size of output registers in a
separate pass, before allocating them.
Revi
Bah...
Reviewed-by: Jason Ekstrand
On Tue, Oct 10, 2017 at 4:47 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This assert was firing just running demos.
>
> Jason said it should be this.
>
> Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image)
> Signed-off-by: Dave Airlie
From: Dave Airlie
With the ssao demo from Vulkan demos:
radv/rx480: 440->440fps
anv/haswell: 24->34 fps
The demo does a 0->32 loop across a ubo with 32 members.
Signed-off-by: Dave Airlie
---
src/compiler/nir/nir_opt_loop_unroll.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
From: Dave Airlie
This assert was firing just running demos.
Jason said it should be this.
Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image)
Signed-off-by: Dave Airlie
---
src/intel/vulkan/anv_wsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src
Acked-by: Marek Olšák
Marek
On Wed, Oct 11, 2017 at 12:07 AM, Rob Herring wrote:
> Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the
> Android build:
>
> external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal
> error: 'llvm-c/TargetMachine.h' file not f
"The GL state tracker, which is the only one that runs into the
multi-context subtleties (due to share groups), already guarantees that
sampler views are destroyed before their context of creation is destroyed."
How does the GL state tracker guarantee this? Does this guarantee also
apply to pipe_
That requires a generated header that was rolled into a loop.
fixes: a47c525f3281a27 ("meson: build glx")
Signed-off-by: Dylan Baker
---
src/mapi/glapi/gen/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mapi/glapi/gen/meson.build b/src/mapi/glapi/gen/meson.build
index 79aa2a
From: Jason Ekstrand
This improves the FillTex benchmark in GLBench 2.7 by 30% on my Broxton.
On Ken's Broxton which only has single-channel ram, it improves by 210%.
v2 (Ken): Check mt->aux_usage == ISL_AUX_USAGE_CCS_E rather than using
intel_miptree_is_lossless_compressed().
---
src
From: Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 34 +
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 69860e28e3b..9ae27c70280 100644
From: Jason Ekstrand
Framebuffer access includes framebuffer reads so we need to invalidate
the texture cache. We do not, however, need to flush the depth cache
because you cannot do bind a depth texture as an image.
---
src/mesa/drivers/dri/i965/brw_program.c | 2 +-
1 file changed, 1 insertio
From: Jason Ekstrand
Texture uploads and downloads may go through the render pipe which may
result in texturing from or rendering to the texture or the PBO. We
need to flush accordingly.
---
src/mesa/drivers/dri/i965/brw_program.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
dif
From: Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 7396597d9f9..69860e28e3b 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_
From: Topi Pohjolainen
v2:
- Fix return value (s/MESA_FORMAT_NONE/false/) (Anuj)
- Move _mesa_tex_format_from_format_and_type() just
in the end avoiding additional if-block (Anuj)
- Explain better the array alignment restriction (Anuj)
- Do not bail out in case of gl_pixelstore_a
Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the
Android build:
external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal
error: 'llvm-c/TargetMachine.h' file not found
^~~~
Update the Android makefiles so that drivers/radeon is
Reviewed-by: Marek Olšák
Marek
On Tue, Oct 10, 2017 at 11:40 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> This fixes sequences like:
>
> 1. Context 1 samples from texture with sRGB decode enabled
> 2. Context 2 samples from texture with sRGB decode disabled
> 3. Context 1 samples from
Same as on IRC:
On 10.10.2017 04:06, Marek Olšák wrote:
Is there any difference with piglit/drawoverhead?
Yes, there is.
If yes, would this be useful?
https://patchwork.freedesktop.org/patch/41241/
Surprisingly, not that much. I'm going to think though a couple of other
options, but want
From: Nicolai Hähnle
This fixes sequences like:
1. Context 1 samples from texture with sRGB decode enabled
2. Context 2 samples from texture with sRGB decode disabled
3. Context 1 samples from texture with sRGB decode disabled
Previously, step 3 would see the prev_sRGBDecode value from context
On 11 October 2017 at 02:00, Alex Smith wrote:
> Signed-off-by: Alex Smith
Thanks Alex,
pushed.
Dave.
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Consistently use it as a PIPE_VIDEO_ENTRYPOINT.
v2: Return an error if the entrypoint is not set (Christian).
Signed-off-by: Mark Thompson
---
On 10/10/17 08:32, Christian König wrote:
> Am 09.10.2017 um 22:45 schrieb Mark Thompson:
>> Consistently use it as a PIPE_VIDEO_ENTRYPOINT.
>>
>> Signed
Quoting Kyriazis, George (2017-10-10 12:14:00)
>
> > On Oct 10, 2017, at 1:23 PM, Dylan Baker wrote:
> >
> > Quoting Kyriazis, George (2017-10-10 11:02:26)
> >>
> >>> On Oct 10, 2017, at 12:46 PM, Dylan Baker wrote:
> >>>
> >>> Quoting Jose Fonseca (2017-10-10 08:41:49)
> On 10/10/17 16:
On Tue, Oct 10, 2017 at 12:52 PM, Francisco Jerez
wrote:
> Jason Ekstrand writes:
>
> > On Wed, Oct 4, 2017 at 5:29 PM, Connor Abbott
> wrote:
> >
> >> This won't completely solve the problem. For example, what if you
> >> hoist the assignment to color2 outside the loop?
> >>
> >> vec4 color2;
Emil Velikov writes:
> On 4 October 2017 at 15:10, Jan Vesely wrote:
>> On Wed, 2017-10-04 at 14:59 +0100, Emil Velikov wrote:
>>> On 3 October 2017 at 19:19, Jan Vesely wrote:
>>> > On Tue, 2017-10-03 at 17:51 +0100, Emil Velikov wrote:
>>> > > From: Emil Velikov
>>> > >
>>> > > The only driv
On Tue, Oct 10, 2017 at 9:16 AM, Connor Abbott wrote:
> I'm a little nervous about this, because really, the only solution to
> this problem is to ignore all non-WE_all definitions of all variables
> in liveness analysis. For example, in something like:
>
> vec4 color2 = ...
> if (...) {
>col
Jason Ekstrand writes:
> On Wed, Oct 4, 2017 at 5:29 PM, Connor Abbott wrote:
>
>> This won't completely solve the problem. For example, what if you
>> hoist the assignment to color2 outside the loop?
>>
>> vec4 color2;
>> while (1) {
>>vec4 color = texture();
>>color2 = color * 2;
>>
> On Oct 10, 2017, at 1:23 PM, Dylan Baker wrote:
>
> Quoting Kyriazis, George (2017-10-10 11:02:26)
>>
>>> On Oct 10, 2017, at 12:46 PM, Dylan Baker wrote:
>>>
>>> Quoting Jose Fonseca (2017-10-10 08:41:49)
On 10/10/17 16:31, Kyriazis, George wrote:
> Hello…
>
> Piglit on w
Samuel Iglesias Gonsálvez writes:
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/compiler/nir/nir_lower_tex.c | 68
>
> 1 file changed, 68 insertions(+)
>
> diff --git a/src/compiler/nir/nir_lower_tex.c
> b/src/compiler/nir/nir_lower_tex.c
> in
Quoting Kyriazis, George (2017-10-10 11:02:26)
>
> > On Oct 10, 2017, at 12:46 PM, Dylan Baker wrote:
> >
> > Quoting Jose Fonseca (2017-10-10 08:41:49)
> >> On 10/10/17 16:31, Kyriazis, George wrote:
> >>> Hello…
> >>>
> >>> Piglit on windows prints out a message saying “Timeout are not
> >>>
Emil Velikov writes:
> From: Emil Velikov
>
> The __DRI_IMAGE version can be 17 or over, while the function pointer is
> NULL. Guard for that instead of crashing.
>
> Fixes: bad24395d91 ("egl/dri: use createImageFromRenderbuffer2 when
> available")
> Cc: Nicolai Hähnle
> Signed-off-by: Emil Vel
For the series:
Reviewed-by: Marek Olšák
Marek
On Tue, Oct 10, 2017 at 2:11 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> It's not used -- DFRACEXP gets array indexes of its exponent out-parameter
> lowered earlier -- and it wouldn't have worked correctly anyway when both
> dst and dst
Quoting Nicolai Hähnle (2017-10-10 09:30:31)
> On 10.10.2017 04:45, Timothy Arceri wrote:
> > While modern pthread mutexes are very fast, they still incur a call to an
> > external DSO and overhead of the generality and features of pthread mutexes.
> > Most mutexes in mesa only needs lock/unlock, a
> On Oct 10, 2017, at 12:46 PM, Dylan Baker wrote:
>
> Quoting Jose Fonseca (2017-10-10 08:41:49)
>> On 10/10/17 16:31, Kyriazis, George wrote:
>>> Hello…
>>>
>>> Piglit on windows prints out a message saying “Timeout are not implemented
>>> on Windows.”. These timeouts are the test timeouts
For patches 2-3:
Reviewed-by: Marek Olšák
Marek
On Tue, Oct 10, 2017 at 4:45 AM, Timothy Arceri wrote:
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 34
> +--
> src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 2 +-
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.
From: Emil Velikov
The __DRI_IMAGE version can be 17 or over, while the function pointer is
NULL. Guard for that instead of crashing.
Fixes: bad24395d91 ("egl/dri: use createImageFromRenderbuffer2 when
available")
Cc: Nicolai Hähnle
Signed-off-by: Emil Velikov
---
src/egl/drivers/dri2/egl_dri
On Tue, Oct 10, 2017 at 1:11 PM, Daniel Stone wrote:
> Hi Marek,
>
> On 9 October 2017 at 18:05, Marek Olšák wrote:
>> surf->is_linear = surf->u.legacy.level[0].mode ==
>> RADEON_SURF_MODE_LINEAR_ALIGNED;
>> + surf->is_displayable = surf->micro_tile_mode ==
>> RADEON_MICRO_MODE_DI
Quoting Jose Fonseca (2017-10-10 08:41:49)
> On 10/10/17 16:31, Kyriazis, George wrote:
> > Hello…
> >
> > Piglit on windows prints out a message saying “Timeout are not implemented
> > on Windows.”. These timeouts are the test timeouts in case a test hangs.
> >
> > What do people do when runni
On 19 September 2017 at 19:06, Eric Anholt wrote:
> My intent is to develop the vc5 driver in-tree for some time to build the
> CL generation and shader compiler code, and keep out-of-tree patches for
> talking to an actual kernel driver until the kernel driver can be
> stabilized on the hardware.
Hi Dan,
Small question, which is somewhat orthogonal to the patch. Sorry :-\
On 2 October 2017 at 17:31, Daniel Stone wrote:
>
> - if (dri2_dpy->wl_dmabuf && dri2_dpy->image->base.version >= 15) {
> - struct zwp_linux_buffer_params_v1 *params;
> + if (dri2_dpy->image->base.version >= 1
Reviewed-by: Marek Olšák
Marek
On Mon, Oct 9, 2017 at 10:28 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> ---
> src/gallium/drivers/r600/r600_buffer_common.c | 2 --
> src/gallium/drivers/r600/r600_pipe_common.h | 12
> src/gallium/drivers/r600/r
Reviewed-by: Marek Olšák
Marek
On Fri, Oct 6, 2017 at 10:39 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> It's not used, and the assignment for the TGSI case was incorrect
> for sampler arrays.
> ---
> src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 -
> src/mesa/state_tracker/st_glsl_t
Reviewed-by: Marek Olšák
BTW, desktop OpenGL does have GL_TEXTURE_SRGB_DECODE_EXT, so the
comments are incorrect.
Marke
On Fri, Oct 6, 2017 at 10:39 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> See the comment for the relevant spec quote.
>
> Fixes
> dEQP-GLES31.functional.srgb_textu
Thanks for making those changes.
Reviewed-by: Dylan Baker
Quoting Brian Paul (2017-10-09 19:26:22)
> If one uses a parent build script to download/build Mesa we may not
> have a full git repository (maybe a tar archive) so the 'git rev-parse'
> command will fail.
>
> This updates the script to
On 10.10.2017 18:30, Emil Velikov wrote:
On 6 October 2017 at 21:16, Nicolai Hähnle wrote:
From: Nicolai Hähnle
Tested with dEQP-EGL tests.
+.createImageWithModifiers = NULL,
+.createImageFromDmaBufs2 = NULL,
+.queryDmaBufFormats = NULL,
+.queryDmaBufModi
On Mon, Oct 9, 2017 at 7:45 PM, Timothy Arceri wrote:
> After a recent discussion about this code from 2015 I was curious
> to give it a try. The outstanding review item was that we shouldn't
> be replacing the C11 mtx type/functions with our own, so I've renamed
> the fast path to simple_mtx* and
Eric Anholt writes:
> [ Unknown signature status ]
> Nicolai Hähnle writes:
>
>> Patches 1 & 2:
>>
>> Acked-by: Nicolai Hähnle
>>
>> Patches 4 & 5:
>>
>> Reviewed-by: Nicolai Hähnle
>> (for the gallium parts; it would have been nice to split patch 4 up into
>> gallium and driver parts, but I
No, this is a different situation. On i965, the hardware keeps track
of that stuff automatically. The problem is that the header, which is
shared across all the threads in a wavefront and specifies stuff like
LOD, LOD bias, texture array offset, etc., uses the same register
space as normal, vector
On 6 October 2017 at 21:16, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> Tested with dEQP-EGL tests.
> +.createImageWithModifiers = NULL,
> +.createImageFromDmaBufs2 = NULL,
> +.queryDmaBufFormats = NULL,
> +.queryDmaBufModifiers = NULL,
> +.que
On 10.10.2017 04:45, Timothy Arceri wrote:
While modern pthread mutexes are very fast, they still incur a call to an
external DSO and overhead of the generality and features of pthread mutexes.
Most mutexes in mesa only needs lock/unlock, and the idea here is that we can
inline the atomic operati
I hope I'm not butting in too much with irrelevant info, but I think
we had a similar issue in nouveau. On Kepler, texture instructions
take an arbitrary amount of time to complete, and only write into
destination registers on completion, while other instructions are
executing after that tex dispat
On 10.10.2017 18:24, Emil Velikov wrote:
On 6 October 2017 at 21:16, Nicolai Hähnle wrote:
+ if (dri2_dpy->image->base.version >= 17) {
Don't forget to check for the function pointer:
if (dri2_dpy->image->base.version >= 17 &&
dri2_dpy->image->createImageFromRenderbuffer2) {
Too late :/
On 6 October 2017 at 21:16, Nicolai Hähnle wrote:
> + if (dri2_dpy->image->base.version >= 17) {
Don't forget to check for the function pointer:
if (dri2_dpy->image->base.version >= 17 &&
dri2_dpy->image->createImageFromRenderbuffer2) {
-Emil
___
me
On 6 October 2017 at 21:16, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> src/egl/drivers/dri2/platform_x11_dri3.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c
> b/src/egl/drivers/dri2/platform_x11_dri3.c
> index 45bb56ca17e..eadd37
I'm a little nervous about this, because really, the only solution to
this problem is to ignore all non-WE_all definitions of all variables
in liveness analysis. For example, in something like:
vec4 color2 = ...
if (...) {
color2 = texture();
}
texture() can also overwrite inactive channels of
Timothy Arceri writes:
> On 10/10/17 09:31, Timothy Arceri wrote:
>> On 10/10/17 09:06, Eric Anholt wrote:
>>> Timothy Arceri writes:
>>>
This is intended to be called before nir_lower_io() so that we
can do some linking optimisations with the results. It can also
be used with dri
Signed-off-by: Alex Smith
---
src/amd/vulkan/radv_formats.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 88305abd04..5c79ea7406 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -961,6
On Oct 10, 2017, at 10:41 AM, Jose Fonseca
mailto:jfons...@vmware.com>> wrote:
On 10/10/17 16:31, Kyriazis, George wrote:
Hello…
Piglit on windows prints out a message saying “Timeout are not implemented on
Windows.”. These timeouts are the test timeouts in case a test hangs.
What do people do
On 10/10/17 16:31, Kyriazis, George wrote:
Hello…
Piglit on windows prints out a message saying “Timeout are not implemented on
Windows.”. These timeouts are the test timeouts in case a test hangs.
What do people do when running piglit on windows and they hit a timeout? I
would imagine ther
On 10/10/17 14:35, Samuel Iglesias Gonsálvez wrote:
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_tex.c | 68
1 file changed, 68 insertions(+)
diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
i
Hi Suresh,
On 10 October 2017 at 07:20, sguttula wrote:
> when display type is VA_DISPLAY_DRM_RENDERNODES and if
> drm screen create method is not enabled then vscreen is
> NULL. To fix this issue,this patch will enable
> vl_drm_screen_create() for surfaceless platforms
>
Repeating some earlier q
Hello…
Piglit on windows prints out a message saying “Timeout are not implemented on
Windows.”. These timeouts are the test timeouts in case a test hangs.
What do people do when running piglit on windows and they hit a timeout? I
would imagine there would be a non-zero number of people runnin
On 10 October 2017 at 13:38, Marek Olšák wrote:
>
> I think all our mutexes are mtx_plain, but the simple mutexes can't be used
> with cond vars.
>
Sadly we have a few mtx_recursive instances - 3 in mesa/main and 1 in svga.
-Emil
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For the series:
Reviewed-by: Roland Scheidegger
(I don't have any preference for !! or != albeit I do think doing it
explicit either way makes it more obvious indeed.)
Roland
Am 10.10.2017 um 04:29 schrieb Brian Paul:
> v2: use !! in the function to be explicit about type conversion. Though,
>
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_tex.c | 68
1 file changed, 68 insertions(+)
diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
index 65681decb1c..d3380710405 100644
--- a/src/compiler/
It is already done in NIR.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 5b8ccd50bff..5c2f04ea268 100644
--- a/src/intel/compi
It is already done in NIR.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4_nir.cpp | 9 -
src/intel/compiler/brw_vec4_visitor.cpp | 12
2 files changed, 21 deletions(-)
diff --git a/src/intel/compiler/brw_vec4_nir.cpp
b/src/intel/compiler/brw_
Fixes:
dEQP-VK.spirv_assembly.instruction.*.image_sampler.*
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_cfg.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index 25ff254bcec..8b139068f
Hi!
Thanks for keeping up with the long wait =)
I revisited this not too long ago, and found that with the new
pointer hashing function the benefits are zero to negative
from this series. I've reduced it to only the instruction set and
the string_to_uint_map patch but it's not convincing.
I suspec
On 10/07/2017 01:22 PM, Mark Thompson wrote:
On 07/10/17 15:23, Leo Liu wrote:
On 2017-10-01 01:40 PM, Mark Thompson wrote:
This is a new interface in libva2 to support wider use-cases of passing
surfaces to external APIs. In particular, this allows export of NV12 and
P010 surfaces.
v2: Con
On Oct 10, 2017 4:46 AM, "Timothy Arceri" wrote:
After a recent discussion about this code from 2015 I was curious
to give it a try. The outstanding review item was that we shouldn't
be replacing the C11 mtx type/functions with our own, so I've renamed
the fast path to simple_mtx* and added a cou
For the series:
Reviewed-by: Marek Olšák
Marek
On Oct 10, 2017 1:56 PM, "Nicolai Hähnle" wrote:
> Both patches:
>
> Reviewed-by: Nicolai Hähnle
>
> On 10.10.2017 05:25, Dave Airlie wrote:
>
>> From: Dave Airlie
>>
>> This lowers ffma to a * b + c.
>>
>> This seems like it should keep Marek
On 10.10.2017 13:11, Daniel Stone wrote:
Hi Marek,
On 9 October 2017 at 18:05, Marek Olšák wrote:
surf->is_linear = surf->u.legacy.level[0].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED;
+ surf->is_displayable = surf->micro_tile_mode ==
RADEON_MICRO_MODE_DISPLAY ||
+
From: Nicolai Hähnle
Replace the undefined destination by a new temporary register.
Cleanup merge_two_dsts while we're at it.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 38 ++
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/src/mesa/state_tracke
From: Nicolai Hähnle
It's not used -- DFRACEXP gets array indexes of its exponent out-parameter
lowered earlier -- and it wouldn't have worked correctly anyway when both
dst and dst1 use relative addressing.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 7 ++-
1 file changed, 2 insertions
From: Nicolai Hähnle
Make sure we actually allocate two adjacent TGSI temporaries. The
current code fails e.g. when an arithmetic operation has two
operands with indirect accesses.
I will send out a new piglit test
(arb_gpu_shader_int64/execution/indirect-array-two-accesses.shader_test)
Cc: mes
From: Nicolai Hähnle
The dynamic index of a vector (not array!) is lowered to a sequence of
conditional assignments. However, the interpolate_at_* expressions
require that the interpolant is an l-value of a shader input.
So instead of doing conditional assignments of parts of the shader input
an
From: Nicolai Hähnle
The intended rule has been clarified in GLSL 4.60, Section 8.13.2
(Interpolation Functions):
"For all of the interpolation functions, interpolant must be an l-value
from an in declaration; this can include a variable, a block or
structure member, an array element,
On 10.10.2017 13:15, Gert Wollny wrote:
+ os << "[";
+ if (reg.reladdr)
+ os << *reg.reladdr << "+";
+ if (reg.reladdr2)
+ os << *reg.reladdr2 << "+";
This isn't how that works. reladdr2 is the relative address for 2D
register accesses; see has_index2 and index2D.
Actually,
Hi,
On 05.10.2017 18:15, Eero Tamminen wrote:
On 05.10.2017 01:16, Eric Anholt wrote:
Kenneth Graunke writes:
Found while trying to optimize an application.
Not observed to help performance on i965, but should at least reduce
the memory usage of such textures a bit.
I run benchmarks on it
Am Samstag, den 30.09.2017, 10:11 +0200 schrieb Wladimir J. van der Laan:
> If an RS blit is done with source exactly the same as destination, and
> the hardware supports this, do an in-place resolve. This only fills in
> tiles that have not been rendered to using information from the TS.
>
> This
Both patches:
Reviewed-by: Nicolai Hähnle
On 10.10.2017 05:25, Dave Airlie wrote:
From: Dave Airlie
This lowers ffma to a * b + c.
This seems like it should keep Marek happiest, so
we'd never get to the fma instruction emission code.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/ra
Both patches:
Reviewed-by: Nicolai Hähnle
On 09.10.2017 22:28, Dave Airlie wrote:
From: Dave Airlie
Only r600 target used now for compute IR.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe_common.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletio
Hi,
On 03.10.2017 08:20, Matt Turner wrote:
A typo caused us to copy src0's reg file to src1 rather than reading
src1's as intended. This caused us to fail to compact instructions like
mov(8) g4<1>D0D { align1 1Q };
because src1 was set to immediate rather than architect
ok another one too ...
On 10/10/2017 01:03 PM, Tapani Pälli wrote:
one error found below ..
On 10/10/2017 05:45 AM, Timothy Arceri wrote:
While modern pthread mutexes are very fast, they still incur a call to an
external DSO and overhead of the generality and features of pthread
mutexes.
Most
With this patch applied I can not reproduce anymore the regression
related to cross-channel variable interference in non-uniformly executed
loops exposed at
dEQP-VK.glsl.return.return_in_dynamic_loop_dynamic_vertex when applying
Curro's liveness patch
Tested-by: Jose Maria Casanova Crespo
On 05/
Hi Marek,
On 9 October 2017 at 18:05, Marek Olšák wrote:
> This implements __DRIimageExtension::validateUsage properly.
>
> It also modifies Addrlib and adds a new pipe_screen function.
Thanks for looking into this! I don't know the AMD bits well enough to
say much about them, but patches 3 and
> > + os << "[";
> > + if (reg.reladdr)
> > + os << *reg.reladdr << "+";
> > + if (reg.reladdr2)
> > + os << *reg.reladdr2 << "+";
>
> This isn't how that works. reladdr2 is the relative address for 2D
> register accesses; see has_index2 and index2D.
Actually, I don't like this
Hi Marek,
On 9 October 2017 at 18:05, Marek Olšák wrote:
> surf->is_linear = surf->u.legacy.level[0].mode ==
> RADEON_SURF_MODE_LINEAR_ALIGNED;
> + surf->is_displayable = surf->micro_tile_mode ==
> RADEON_MICRO_MODE_DISPLAY ||
> + surf->micro_tile_mode
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