---
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
src/amd/vulkan/radv_debug.c | 2 +-
src/amd/vulkan/radv_device.c | 4 +---
src/amd/vulkan/radv_image.c | 4 ++--
src/amd/vulkan/radv_meta_clear.c | 4 ++--
src/amd/vulkan/radv_pipeline.c | 4 ++--
src/amd/vulkan/radv_pipeline_cache.c | 2 +-
src/amd/vulkan/radv_private.h | 1 -
src/amd/vulkan/radv_shader.c | 8 ++++----
9 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 67e038a152..495fd67dbb 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -366,21 +366,21 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer)
++cmd_buffer->state.trace_id;
device->ws->cs_add_buffer(cs, device->trace_bo, 8);
radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
}
static void
radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
{
- if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
+ if (cmd_buffer->device->instance->debug_flags &
RADV_DEBUG_SYNC_SHADERS) {
enum radv_cmd_flush_bits flags;
/* Force wait for graphics/compute engines to be idle. */
flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
si_cs_emit_cache_flush(cmd_buffer->cs, false,
cmd_buffer->device->physical_device->rad_info.chip_class,
NULL, 0,
radv_cmd_buffer_uses_mec(cmd_buffer),
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index cb9509117e..b69c05b64f 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -592,21 +592,21 @@ radv_dump_dmesg(FILE *f)
pclose(p);
}
static void
radv_dump_enabled_options(struct radv_device *device, FILE *f)
{
uint64_t mask;
fprintf(f, "Enabled debug options: ");
- mask = device->debug_flags;
+ mask = device->instance->debug_flags;
while (mask) {
int i = u_bit_scan64(&mask);
fprintf(f, "%s, ", radv_get_debug_option_name(i));
}
fprintf(f, "\n");
fprintf(f, "Enabled perftest options: ");
mask = device->instance->perftest_flags;
while (mask) {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e07a573819..d414d8ca85 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1147,22 +1147,20 @@ VkResult radv_CreateDevice(
VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
if (!device)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
memset(device, 0, sizeof(*device));
device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
device->instance = physical_device->instance;
device->physical_device = physical_device;
- device->debug_flags = device->instance->debug_flags;
-
device->ws = physical_device->ws;
if (pAllocator)
device->alloc = *pAllocator;
else
device->alloc = physical_device->instance->alloc;
mtx_init(&device->shader_slab_mutex, mtx_plain);
list_inithead(&device->shader_slabs);
for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
@@ -3144,21 +3142,21 @@ radv_initialise_color_surface(struct radv_device
*device,
S_028C70_ENDIAN(endian);
if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
cb->cb_color_info |= S_028C70_COMPRESSION(1);
if (device->physical_device->rad_info.chip_class == SI) {
unsigned fmask_bankh =
util_logbase2(iview->image->fmask.bank_height);
cb->cb_color_attrib |=
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
}
if (iview->image->cmask.size &&
- !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
+ !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
if (device->physical_device->rad_info.chip_class >= VI) {
unsigned max_uncompressed_block_size = 2;
if (iview->image->info.samples > 1) {
if (iview->image->surface.bpe == 1)
max_uncompressed_block_size = 0;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f0645279aa..7c3e55b1b8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -148,21 +148,21 @@ radv_init_surface(struct radv_device *device,
}
}
if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
VK_IMAGE_USAGE_STORAGE_BIT)) ||
(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
!dcc_compatible_formats ||
(pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
device->physical_device->rad_info.chip_class < VI ||
- create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC))
+ create_info->scanout || (device->instance->debug_flags &
RADV_DEBUG_NO_DCC))
surface->flags |= RADEON_SURF_DISABLE_DCC;
if (create_info->scanout)
surface->flags |= RADEON_SURF_SCANOUT;
return 0;
}
static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
{
return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
}
@@ -906,21 +906,21 @@ radv_image_create(VkDevice _device,
radv_image_alloc_cmask(device, image);
}
}
/* Try to enable FMASK for multisampled images. */
if (radv_image_can_enable_fmask(image)) {
radv_image_alloc_fmask(device, image);
} else {
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
- !(device->debug_flags & RADV_DEBUG_NO_HIZ)) {
+ !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
radv_image_alloc_htile(image);
image->tc_compatible_htile = image->surface.flags &
RADEON_SURF_TC_COMPATIBLE_HTILE;
} else {
image->surface.htile_size = 0;
}
}
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
image->alignment = MAX2(image->alignment, 4096);
image->size = align64(image->size, image->alignment);
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 0f895f8c50..476a5913ae 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -676,21 +676,21 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_image_view *iview =
fb->attachments[pass_att].attachment;
VkClearDepthStencilValue clear_value =
clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
uint32_t clear_word;
if (!iview->image->surface.htile_size)
return false;
- if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+ if (cmd_buffer->device->instance->debug_flags &
RADV_DEBUG_NO_FAST_CLEARS)
return false;
if (!radv_layout_is_htile_compressed(iview->image, image_layout,
radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index)))
goto fail;
/* don't fast clear 3D */
if (iview->image->type == VK_IMAGE_TYPE_3D)
goto fail;
/* all layers are bound */
@@ -951,21 +951,21 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
VkImageLayout image_layout =
subpass->color_attachments[subpass_att].layout;
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_image_view *iview =
fb->attachments[pass_att].attachment;
VkClearColorValue clear_value = clear_att->clearValue.color;
uint32_t clear_color[2];
bool ret;
if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
return false;
- if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+ if (cmd_buffer->device->instance->debug_flags &
RADV_DEBUG_NO_FAST_CLEARS)
return false;
if (!radv_layout_can_fast_clear(iview->image, image_layout,
radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index)))
goto fail;
/* don't fast clear 3D */
if (iview->image->type == VK_IMAGE_TYPE_3D)
goto fail;
/* all layers are bound */
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 0d22bbe4bc..6219ad44ac 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2086,21 +2086,21 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
else
pipeline->graphics.vtx_emit_num = 2;
}
pipeline->graphics.vtx_reuse_depth = 30;
if (radv_pipeline_has_tess(pipeline) &&
pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing ==
TESS_SPACING_FRACTIONAL_ODD) {
pipeline->graphics.vtx_reuse_depth = 14;
}
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}
result = radv_pipeline_scratch_init(device, pipeline);
return result;
}
VkResult
radv_graphics_pipeline_create(
VkDevice _device,
@@ -2191,21 +2191,21 @@ static VkResult radv_compute_pipeline_create(
pipeline->need_indirect_descriptor_sets |=
pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
result = radv_pipeline_scratch_init(device, pipeline);
if (result != VK_SUCCESS) {
radv_pipeline_destroy(device, pipeline, pAllocator);
return result;
}
*pPipeline = radv_pipeline_to_handle(pipeline);
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}
return VK_SUCCESS;
}
VkResult radv_CreateComputePipelines(
VkDevice _device,
VkPipelineCache pipelineCache,
uint32_t count,
const VkComputePipelineCreateInfo* pCreateInfos,
const VkAllocationCallbacks* pAllocator,
diff --git a/src/amd/vulkan/radv_pipeline_cache.c
b/src/amd/vulkan/radv_pipeline_cache.c
index 43176b6fdf..625c58e66c 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -53,21 +53,21 @@ radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
cache->modified = false;
cache->kernel_count = 0;
cache->total_size = 0;
cache->table_size = 1024;
const size_t byte_size = cache->table_size *
sizeof(cache->hash_table[0]);
cache->hash_table = malloc(byte_size);
/* We don't consider allocation failure fatal, we just start with a
0-sized
* cache. */
if (cache->hash_table == NULL ||
- (device->debug_flags & RADV_DEBUG_NO_CACHE))
+ (device->instance->debug_flags & RADV_DEBUG_NO_CACHE))
cache->table_size = 0;
else
memset(cache->hash_table, 0, byte_size);
}
void
radv_pipeline_cache_finish(struct radv_pipeline_cache *cache)
{
for (unsigned i = 0; i < cache->table_size; ++i)
if (cache->hash_table[i]) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4d2b2c696b..548952faa9 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -506,21 +506,20 @@ struct radv_device {
VkAllocationCallbacks alloc;
struct radv_instance * instance;
struct radeon_winsys *ws;
struct radv_meta_state meta_state;
struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
int queue_count[RADV_MAX_QUEUE_FAMILIES];
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
- uint64_t debug_flags;
bool llvm_supports_spill;
bool has_distributed_tess;
uint32_t tess_offchip_block_dw_size;
uint32_t scratch_waves;
uint32_t gs_table_depth;
/* MSAA sample locations.
* The first index is the sample index.
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 535d0f4f58..d4bef9792e 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -167,21 +167,21 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir->options = &nir_options;
nir_validate_shader(nir);
assert(exec_list_length(&nir->functions) == 1);
struct exec_node *node = exec_list_get_head(&nir->functions);
entry_point = exec_node_data(nir_function, node, node);
} else {
uint32_t *spirv = (uint32_t *) module->data;
assert(module->size % 4 == 0);
- if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
radv_print_spirv(spirv, module->size, stderr);
uint32_t num_spec_entries = 0;
struct nir_spirv_specialization *spec_entries = NULL;
if (spec_info && spec_info->mapEntryCount > 0) {
num_spec_entries = spec_info->mapEntryCount;
spec_entries = malloc(num_spec_entries *
sizeof(*spec_entries));
for (uint32_t i = 0; i < num_spec_entries; i++) {
VkSpecializationMapEntry entry =
spec_info->pMapEntries[i];
const void *data = spec_info->pData +
entry.offset;
@@ -256,21 +256,21 @@ radv_shader_compile_to_nir(struct radv_device *device,
};
nir_lower_tex(nir, &tex_options);
nir_lower_vars_to_ssa(nir);
nir_lower_var_copies(nir);
nir_lower_global_vars_to_local(nir);
nir_remove_dead_variables(nir, nir_var_local);
radv_optimize_nir(nir);
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADERS)
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
nir_print_shader(nir, stderr);
return nir;
}
void *
radv_alloc_shader_memory(struct radv_device *device,
struct radv_shader_variant *shader)
{
mtx_lock(&device->shader_slab_mutex);
@@ -379,21 +379,21 @@ static struct radv_shader_variant *
shader_variant_create(struct radv_device *device,
struct radv_shader_module *module,
struct nir_shader *shader,
gl_shader_stage stage,
struct ac_nir_compiler_options *options,
bool gs_copy_shader,
void **code_out,
unsigned *code_size_out)
{
enum radeon_family chip_family =
device->physical_device->rad_info.family;
- bool dump_shaders = device->debug_flags & RADV_DEBUG_DUMP_SHADERS;
+ bool dump_shaders = device->instance->debug_flags &
RADV_DEBUG_DUMP_SHADERS;
enum ac_target_machine_options tm_options = 0;
struct radv_shader_variant *variant;
struct ac_shader_binary binary;
LLVMTargetMachineRef tm;
variant = calloc(1, sizeof(struct radv_shader_variant));
if (!variant)
return NULL;
options->family = chip_family;
@@ -451,21 +451,21 @@ radv_shader_variant_create(struct radv_device *device,
const struct ac_shader_variant_key *key,
void **code_out,
unsigned *code_size_out)
{
struct ac_nir_compiler_options options = {0};
options.layout = layout;
if (key)
options.key = *key;
- options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
+ options.unsafe_math = !!(device->instance->debug_flags &
RADV_DEBUG_UNSAFE_MATH);
options.supports_spill = device->llvm_supports_spill;
return shader_variant_create(device, module, shader, shader->stage,
&options, false, code_out, code_size_out);
}
struct radv_shader_variant *
radv_create_gs_copy_shader(struct radv_device *device,
struct nir_shader *shader,
void **code_out,
--
2.13.6
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