On 10/01/17 06:53 PM, Nayan Deshmukh wrote:
> On Sat, Jan 7, 2017 at 12:42 PM, Michel Dänzer wrote:
>> On 06/01/17 05:50 AM, Andy Furniss wrote:
>>> Christian König wrote:
Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh:
> dri3 allows us to send handle of a texture directly to X
> so th
W dniu 10.01.2017 o 18:48, Jason Ekstrand pisze:
Hi,
Can we add workaround to drirc and enable this only when needed?
Best Regards
Krzysztof Cybulski
I'll be honest, I'm not a fan... Given that D3D10 has one defined
behavior, D3D9 has another, and GL doesn't specify, I don't really
think we
Hi Matt,
Matt Turner writes:
> On Sun, Jan 8, 2017 at 10:53 PM, Matt Turner wrote:
>> On 01/05, Samuel Iglesias Gonsálvez wrote:
>>>
>>> From: "Juan A. Suarez Romero"
>>>
>>> When dealing with DF uniforms with just 1 component, we set stride 0 to
>>> use the value along the operation. However,
On 10/01/17 09:07 PM, Andy Furniss wrote:
> Andy Furniss wrote:
>
>> Though recent testing shows this is not true with DAL/DC on 3.7 -
>> todo test DC on new drm-next branch.
>
> todo done, DC for some reason on both amd-staging-4.7 and
> amd-staging-drm-next is "slower" = the tear region is 2 to
On 01/09, Juan A. Suarez Romero wrote:
From: Alejandro Piñeiro
Doubles need extra space, so we would need to do a remapping for vec4
too in order to take that into account. We reuse the already
existing remap_vs_attrs, but passing is_scalar, so they could
remap accordingly.
Signed-off-by: Alej
On Sun, Jan 8, 2017 at 10:53 PM, Matt Turner wrote:
> On 01/05, Samuel Iglesias Gonsálvez wrote:
>>
>> From: "Juan A. Suarez Romero"
>>
>> When dealing with DF uniforms with just 1 component, we set stride 0 to
>> use the value along the operation. However, when duplicating the
>> regioning param
https://bugs.freedesktop.org/show_bug.cgi?id=92634
Reuben changed:
What|Removed |Added
CC||reube...@yahoo.com
--
You are receiving this m
Currently its dependant on the user calling and checking the result
of list_empty() before using the result of list_is_singular().
---
src/util/list.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/list.h b/src/util/list.h
index e8a99ac..07eb9f3 100644
--- a/src/util/
On Tue, Jan 10, 2017 at 7:17 PM, Chad Versace
wrote:
> Loader interface v2 differs from v1 in that the first ICD entrypoint
> called by the loader is vk_icdNegotiateLoaderICDInterfaceVersion(), not
> vk_icdGetInstanceProcAddr(). The ICD must statically expose this
> entrypoint.
> ---
> src/intel
On Tue 10 Jan 2017, Jason Ekstrand wrote:
> I thought for sure we supported at least v2... In any case, go for it.
No. We only supported v1. And I just sent patches to support v2.
Dave, I tested that I didn't break the radv build. But you should
probably double-check for me.
Import from commit f2aeefec on branch 'master'
of https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers.
---
include/vulkan/vk_icd.h | 110 ++--
1 file changed, 78 insertions(+), 32 deletions(-)
diff --git a/include/vulkan/vk_icd.h b/include/
Loader interface v2 differs from v1 in that the first ICD entrypoint
called by the loader is vk_icdNegotiateLoaderICDInterfaceVersion(), not
vk_icdGetInstanceProcAddr(). The ICD must statically expose this
entrypoint.
---
src/intel/vulkan/anv_device.c | 43 +
I tested this by:
- Running vkcube on Wayland with an older Vulkan loader 1.0.30, as
shipped by Arch Linux.
- Running vkcube on Wayland with a Vulkan loader built from today's
master at commit 82a2c181e32f4bc.
- Running 'dEQP-VK.wsi.xlib.*'. All 33 tests passed.
I also checked that r
We can't import the latest vk_icd.h because the new header breaks the
Mesa build. This patch defines new casting macros,
ICD_DEFINE_NONDISP_HANDLE_CASTS() and ICD_FROM_HANDLE(), which can
handle both the old and new vk_icd.h, and will prevent the build from
breaking when we update the header.
In t
Ever since a long time ago when I messed around with fences, I ensure
that after a PUSH_SPACE call there is enough space to write a fence out
into the pushbuf.
However the PUSH_SPACE macro is not all-knowing, and so sometimes we
have to invoke nouveau_pushbuf_space manually with the relocs/pushes
The docs should be updated in patches 8, 10 and 11.
With that, 4-11 Reviewed-by: Jordan Justen
On 2017-01-09 09:09:58, Juan A. Suarez Romero wrote:
> Hi,
>
> This series implements the support for Haswell 64bit vertex attributes. With
> it,
> we can enable OpenGL 4.2 in Haswell.
>
> This work
These seem unlikely to be used.
Also remove irrelevant comment about SKL.
v2: forgot to rebase on master
Signed-off-by: Grazvydas Ignotas
---
no commit access
src/amd/vulkan/radv_private.h | 15 +--
src/amd/vulkan/radv_util.c| 19 ---
2 files changed, 1 insertio
In parse_identifier, it doesn't stop copying '*pcur'
untill encounter the NULL. As the 'ret' has a
fixed-size buffer, if the '*pcur' has a long string,
there will be a buffer overflow. This patch avoid this.
Signed-off-by: Li Qiang
---
src/gallium/auxiliary/tgsi/tgsi_text.c | 9 ++---
1 file
Patches 1 & 3 are:
Reviewed-by: Timothy Arceri
On Wed, 2017-01-11 at 01:29 +0100, Bas Nieuwenhuizen wrote:
> Port of faa1edeeb7bbe9321c79587e592dce812e8caa78
> "anv/pipeline: Call NIR passes using NIR_PASS_V"
>
> Signed-off-by: Bas Nieuwenhuizen
> ---
> src/amd/vulkan/radv_pipeline.c | 24 +++
These seem unlikely to be used.
Also remove irrelevant comment about SKL.
Signed-off-by: Grazvydas Ignotas
---
no commit access
src/amd/vulkan/radv_private.h | 15 +--
src/amd/vulkan/radv_util.c| 19 ---
2 files changed, 1 insertion(+), 33 deletions(-)
diff --gi
Unfortunately this one breaks at least (surprise!) texturecubemap
SaschaWillemsVulkan demo.
I recommend you try it yourself, there are even precompiled binaries
available (see README.md):
https://github.com/SaschaWillems/Vulkan
Gražvydas
On Tue, Jan 10, 2017 at 5:12 PM, Nicolai Hähnle wrote:
> F
I thought for sure we supported at least v2... In any case, go for it.
On Tue, Jan 10, 2017 at 2:39 PM, Chad Versace
wrote:
> I've begun working on updating vk_icd.h to the latest upstream version,
> and adding Anvil support for the new interface. Mesa today supports
> loader interface v1; the
Port of c5d664f9dc2d281c74844cef36ecb9f5862a8f6a
"anv/pipeline: Call nir_lower_constant_initializers"
Signed-off-by: Bas Nieuwenhuizen
Cc:
---
src/amd/vulkan/radv_pipeline.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_p
Port of faa1edeeb7bbe9321c79587e592dce812e8caa78
"anv/pipeline: Call NIR passes using NIR_PASS_V"
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_pipeline.c | 24 +++-
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src
Port of 43e0b0d4b255d910616c10e3e01bfec5db469e0e
"anv/pipeline: Only call remove_dead_variables once"
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_pipeline.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv
On 11 Jan. 2017 08:39, "Chad Versace" wrote:
I've begun working on updating vk_icd.h to the latest upstream version,
and adding Anvil support for the new interface. Mesa today supports
loader interface v1; the latest interface is v3.
I don't want to duplicate work that my already been done. So..
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index bf8c338..2f4837e 100644
--- a/src/mesa/drivers/dri/i965
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 768f8a8..bf8c338 100644
--- a/src/mesa/drivers/dri/i965/br
It's harmless to use ALIGN_NPOT() for uncompressed formats
because they have block width/height = 1.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_l
ping.
On Thu, Dec 22, 2016 at 11:14 AM, Ilia Mirkin wrote:
> Ping? Any further comments/feedback/reviews?
>
>
> On Dec 5, 2016 11:22 AM, "Ilia Mirkin" wrote:
>
> On Mon, Dec 5, 2016 at 11:11 AM, Robert Bragg wrote:
>>
>>
>> On Sun, Nov 27, 2016 at 7:23 PM, Ilia Mirkin wrote:
>>>
>>> The strate
I've begun working on updating vk_icd.h to the latest upstream version,
and adding Anvil support for the new interface. Mesa today supports
loader interface v1; the latest interface is v3.
I don't want to duplicate work that my already been done. So...
Has anyone already completed this on a privat
"Juan A. Suarez Romero" writes:
> On Mon, 2017-01-09 at 15:41 -0800, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > From: "Juan A. Suarez Romero"
>> >
>> > In IVB/VLV, for instructions dealing with DF, execsize will be
>> > duplicated in the final code.
>> >
>> > So take
Had some problems to figure out where the factor 2 came from, but in
the end, this series is
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 10, 2017 at 5:35 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> As remarked by the comment in the original code, the old algorithm fails when
> (tc + de
https://bugs.freedesktop.org/show_bug.cgi?id=98002
Luke changed:
What|Removed |Added
CC||lukebe...@hotmail.com
--
You are receiving this
Samuel Iglesias Gonsálvez writes:
> On Mon, 2017-01-09 at 16:18 -0800, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > From: Iago Toral Quiroga
>> >
>> > It seems to use 1 channel por DF, just like later hardware. The
>> > docs say things
>> > like:
>> >
>> > "Each DF ope
On 01/09/2017 10:03 PM, Roland Scheidegger wrote:
Am 06.01.2017 um 10:42 schrieb Samuel Pitoiset:
D3D always computes the absolute value while GLSL says that the
That should probably say "d3d9" - it is completely wrong for d3d10 and
later (which have it to be defined as a guaranteed NaN).
(Ot
The gen7 transform feedback routines store the SOL_OFFSET between
batches into its scratch buffer. Convert these from using opencoded
brw_store_register_mem32()
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/gen7_sol_state.c | 10 +++---
src/mesa/drivers/dri/i965/hsw_sol.c
Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.
Signed-off-by: Chris Wilson
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +++
1 file changed, 1
To reduce churn later, move the HW context variable from brw_context to
brw_batch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_context.c | 23 --
src/mesa/drivers/dri/i965/brw_context.h | 2 --
Or rather export a higher level brw_pipe_control_flush() that wraps the
brw_emit_pipe_control_flush() into a batch as appropriate for the
caller.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_pipe_control.c | 9 +
src/me
We have a few instances where we set a register to an immediate value
(MI_LOAD_REGISTER_IMM), so let's replace them with a simple routine.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_draw.c | 6 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +--
src/
Move the computation of the state offset into a smaller helper to reduce
churn later.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 62 --
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_stat
A simple helper to check whether the last batch buffer submitted to the
hardware is still busy. Extract it now to reduce churn later.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +
src/mesa/drivers/dri/i965/brw_cs.c| 5 ++---
src/mesa/drivers/dri/i965/brw_gs
When processing the packed fields, it is often much easier to pass around
the dword value (as would be seen by hardware) than it is manipulating
the bitfield. By aliasing the bitfield with a uint32_t member, we can
treat the value as either a collection of bits or a single value
depending upon the
Remove the old hashtable approach and switch over to the inline write
tracking with brw-batch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 70 ++-
src/mesa/drivers/dri/i965/brw_batch.h | 10 +---
src/mesa/drivers/dri/i965/brw_co
Just to reduce some later churn, pull out the flink wrapper.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 7 +++
src/mesa/drivers/dri/i965/brw_context.c | 11 +--
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
3 files changed, 13 insertions(+), 7 de
We can use our fence tracking mechanism for fine-grained waiting on
results.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c| 2 +
src/mesa/drivers/dri/i965/brw_context.h| 10 +-
src/m
Provide a common routine for doing conditional batch flushes.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 6 ++
src/mesa/drivers/dri/i965/brw_compute.c | 3 +--
src/mesa/drivers/dri/i965/brw_draw.c| 3 +--
src/mesa/drivers/dri/i965/genX_blorp_exe
There are only a handful of distinct cache domains (less than 16), and
internally the kernel simply doesn't differentiate between the GPU cache
domains - for recent kernels we just pass in whether the object is being
written to (for read/write busyness tracking) and whether it requires the
global G
Rather than split the render batch setup between two hooks, coalesce it
into a single callback. To simplify this, move some of the state
dirtying from the start to the finish hook hook.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 15 ++-
src/mesa/d
Refactor the aperture test, roll back and retry logic to a common idiom.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 18
src/mesa/drivers/dri/i965/brw_compute.c | 36 +++-
src/mesa/drivers/dri/i965/brw_draw.c | 33 --
Move the pipelined register access out of intel_batchbuffer into its
own utility file in preparation for replacing intel_batchbuffer. This
also gives us the opportunity to refactor a few similar routines for
writing registers, and so should prove useful in its own right.
Similarly there is a gener
The introduction of brw_bo_create() allows us to pass a new flag down
when creating a linear buffer to allow the allocator to return a
currently active buffer. (Previously all linear buffers were presumed to
be allocated for CPU access and so the allocator only returned an idle
buffer.)
Signed-off
Since we use fences internally for tracking buffer busyness within
brw_batch.c, we can expose those directly for GL/DRI2 sync objects.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 87 --
src/mesa/drivers/dri/i965/brw_batch.h | 22 -
src/mesa/drive
Since we always flush the intel_batchbuffer before calling
intel_front_flush(), simply more that call into intel_front_flush()
itself.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/mesa/driv
With mesa/drm commit cd2f91e18db087edf93fed828e568ee53b887860
Author: Kristian Høgsberg Kristensen
Date: Fri Jul 31 10:47:50 2015 -0700
intel: Drop aub dumping functionality
the drm_intel_aub routines are mere stubs and do nothing. Likewise
remove our invocations.
Signed-off-by: Chris Wil
Churn now to reduce churn later.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 34 +
src/mesa/drivers/dri/i965/brw_binding_tables.c | 3 +-
src/mesa/drivers/dri/i965/brw_context.c | 3 +-
src/mesa/drivers/dri/i965/brw_program.c
Rather than spend an instruction deciding whether we need to, just zero
out the single integer to reset the HW binding tables.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 6 --
src/mesa/drivers/dri/i965/brw_context.c| 3 +--
src/mesa/drivers/dri/i
We have many flushes outside of the batch buffer critical sections that
need wrapping. Introduce a simple function to wrap the brw_emit_mi_flush()
with the begin/end.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_clear.c| 4 +--
src/mesa/drivers/dri/i965/brw_context.
In order to track aperture usage correctly and flush the batch at safe
transition points, we need to wrap all batch buffer access in begin/end
introduced in the previous patch.
Note, this patch doesn't quite transform everything - we leave the small
flushes to a later refactor.
Signed-off-by: Chr
The flags field becomes more useful later as we store more bits in it,
but for now we can start it off with the pair of boolean state already
stored inside batch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +++--
src/mesa/drivers/dri/i965/brw_misc_state.c
Process the postdraw resolves (including setting the buffer dirty flag)
before any conditional batch flush as that flush will want to clear the
dirty flag.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_draw.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
To reduce later churn, extract drm_intel_bo_madvise() with a smaller
wrapper.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 5 +
src/mesa/drivers/dri/i965/brw_object_purgeable.c | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/
It is essential that the value we write into the batch buffer matches
the value we record in the relocation entry (and that value also
corresponds with the presumed offset the target buffer). To ensure this
is true we combine adding relocation entry to the batch buffer with
recording the target add
Just to ease the next intermediate patch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 1 +
src/mesa/drivers/dri/i965/brw_compute.c | 6 +--
src/mesa/drivers/dri/i965/brw_draw.c | 7 ++--
src/mesa/drivers/dri/i965/brw_state_batch.c | 6 +--
Simple non-functional change to ease later patches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 26 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 26 --
2 files changed, 26 insertions(+), 26 deletions(-)
di
Rather than passing the uint64_t value to write as a pair of high/lo
uint32_t values, place the burden on the callee to split the large value
into the dwords desired by the hardware.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +--
src/mesa/drivers/dri/i965/
To ease intermediate patches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_compute.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_draw.c | 4 ++--
src/mesa/driver
In preparation for a local batch manager with a new buffer object, first
reduce the churn by renaming the existing buffer objects:
s/drm_intel_bo/brw_bo/
We only have to be careful to leave the global screen drm_intel_bo as
they are.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/Mak
In order to reduce future churn, move the callbacks for starting and
finishing the batch from intel_batchbuffer to the brw_context.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 83 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 79 +
We only need the batch promotion if we need to modify privileged registers,
so only request it when we do register loads and stores.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 7 ++-
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/me
In preparation for the next patch, just transplant some functions
between header files.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 17 +
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 18 --
2 files changed, 17 insertions(+),
If we have to flush the batchbuffer early that has performance
implications, and if it is a result of user action we should report that
through the perf_debug interface.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 3 ++
src/mesa/drivers/dri/i965/brw_comput
To ease future transitions.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 32
src/mesa/drivers/dri/i965/brw_context.h | 32
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/src/mesa/driv
To reduce churn later, move the brw->render_cache dirty set into the
batch (i.e. brw->batch.render_cache).
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 7 +++
src/mesa/drivers/dri/i965/brw_context.h | 7 ---
src/mesa/drivers/dri/i965/intel_fbo.c | 12
Currently we signal the availabilty of the query result using an
unordered pipe-control write. As it is unordered, it may be executed
before the write of the query result itself - and so an observer may
read the query result too early. Fix this by requesting that the write
of the availablity flag i
Since brw_batch will become the dominate interface for brw_bo, move the
pointer now to reduce later churn.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 2 ++
src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c
In order to reduce later churn, move a few parameters from the general
brw_context into the intel_batchbuffer.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 20 +
src/mesa/drivers/dri/i965/brw_compute.c | 2 +-
src/mesa/drivers/dri/i965/br
To further reduce churn when replacing the buffer object implementation,
wrap the existing drm_intel_bo_reference/drm_intel_bo_unreference.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 12 ++
src/mesa/drivers/dri/i965/brw_context.c | 29
gen7_sol_state loads the SOL_OFFSET registers from its scratch buffer
by hand, switch it over to the common routine for emitting that command.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/gen7_sol_state.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --gi
In order to reduce future churn, rename the intel_batchbuffer struct.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_state_batch.c | 6 ++
src/mesa/drivers/dri/i9
Simple rename and parameter passing changes now to avoid doing so inside
a much larger patch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +
src/mesa/drivers/dri/i965/brw_context.c | 12 ++
src/mesa/drivers/dri/i965/brw_context.h |
Upcoming patches eliminate the intel_batchbuffer interface and one of
the minor changes that causes a lot of churn is the removal of the
header, along with the occassional need to now call intel_reg.h
themselves. This patch moves the individual includes into brw_context.h.
Signed-off-by: Chris Wil
Since the workaround bo is used strictly as a write-only buffer, we need
only allocate one per screen and use the same one from all contexts.
(The caveat here is during extension initialisation, where we write into
and read back register values from the buffer, but that is performed only
once for
If we don't have pipelined register access (e.g. Haswell before kernel
v4.2), then we can only implement EXT_transform_feedback by reseting the
SO offsets *between* batches. However, if we do have pipelined access to
the SO registers on gen7, we can simply emit an inline reset of the SO
registers w
If the buffer has been freed by the kernel under memory pressure, it is
invalid to try and access the backing storage for that buffer in the
future - the backing storage is not recreated automatically. As such we
need to mark the GL object as being freed for unretained buffers and so
recreate the o
Not much has changed in the couple of years since last posting, just a
lot of rebasing.
Still the major open question is how much locking do individual contexts
require amongst a shared set - can we rely of the upper layer providing
sufficient serialisation around access to brw_context?
The 40% i
before commit f871946594129500a67c05a6d9fe99db54b4bb64
image_loader_extension was always present in dri2_dpy->extensions,
after that commit it is only present for render nodes.
Its removal broke partial render based on buffer age on (at least)
raspberry pi.
Signed-off-by: Derek Foreman
---
I'm
On 17-01-09 16:42:19, Jason Ekstrand wrote:
Somehow I didn't actually get the original e-mail so I'm replying via
git-send-email...
On 01/02, Ben Widawsky wrote:
Modifiers will be obtains or guessed by the client and passed in during
image creation/import.
This requires bumping the DRIimage ve
I don't like adding workarounds to our codebase for someone else's
problem, generally, but specifically I think this is a bad idea
because the name MESA_DEBUG is already used (it's an environment
variable), and this is a completely separate meaning.
___
m
On Tuesday, January 10, 2017 9:06:08 AM PST Jason Ekstrand wrote:
> On Mon, Jan 9, 2017 at 11:37 PM, Kenneth Graunke
> wrote:
>
> > v2: Use info->tess.
> >
> > Signed-off-by: Kenneth Graunke
> > Reviewed-by: Dave Airlie [v1]
> > Reviewed-by: Iago Toral Quiroga [v1]
> > Reviewed-by: Jason Ekstr
On Tue, Jan 10, 2017 at 12:07 PM, Jan Vesely wrote:
> On Tue, 2017-01-10 at 16:43 +, Emil Velikov wrote:
>> On 10 January 2017 at 15:04, Vedran Miletić wrote:
>> > On 09/19/2016 08:39 PM, Vedran Miletić wrote:
>> > > On 09/07/2016 06:52 PM, Vedran Miletić wrote:
>> > > > LLVM and Mesa both de
On Tue, Jan 10, 2017 at 12:56 PM, Andy Furniss wrote:
> Alex Deucher wrote:
>>
>> On Tue, Jan 10, 2017 at 4:50 AM, Nayan Deshmukh
>> wrote:
>>>
>>> On Fri, Jan 6, 2017 at 2:20 AM, Andy Furniss wrote:
Christian König wrote:
>
>
> Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh
Reviewed-by: Jason Ekstrand
On Tue, Jan 10, 2017 at 9:57 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> With shaders using a lot of inputs/outputs, like this (from Gtk+) :
>
> layout(location = 0) in vec2 inPos;
> layout(location = 1) in float inGradientPos;
> layout(location =
With shaders using a lot of inputs/outputs, like this (from Gtk+) :
layout(location = 0) in vec2 inPos;
layout(location = 1) in float inGradientPos;
layout(location = 2) in flat int inRepeating;
layout(location = 3) in flat int inStopCount;
layout(location = 4) in flat vec4 inClipBounds;
layout(lo
Alex Deucher wrote:
On Tue, Jan 10, 2017 at 4:50 AM, Nayan Deshmukh
wrote:
On Fri, Jan 6, 2017 at 2:20 AM, Andy Furniss wrote:
Christian König wrote:
Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh:
dri3 allows us to send handle of a texture directly to X
so this patch allows a state tracke
On Tue, Jan 10, 2017 at 12:51 PM, Jason Ekstrand wrote:
> On Tue, Jan 10, 2017 at 9:48 AM, Jason Ekstrand
> wrote:
>>
>> I'll be honest, I'm not a fan... Given that D3D10 has one defined
>> behavior, D3D9 has another, and GL doesn't specify, I don't really think we
>> should be making a global ch
On 2017-01-09 09:10:01, Juan A. Suarez Romero wrote:
> From: Alejandro Piñeiro
>
> ---
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index 5dd
On Tue, Jan 10, 2017 at 9:48 AM, Jason Ekstrand
wrote:
> I'll be honest, I'm not a fan... Given that D3D10 has one defined
> behavior, D3D9 has another, and GL doesn't specify, I don't really think we
> should be making a global change to all drivers to do the D3D9 behavior
> just to fix one app.
I'll be honest, I'm not a fan... Given that D3D10 has one defined behavior,
D3D9 has another, and GL doesn't specify, I don't really think we should be
making a global change to all drivers to do the D3D9 behavior just to fix
one app. Sure, other apps probably have the same bug, but are we going t
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