In preparation for a local batch manager with a new buffer object, first
reduce the churn by renaming the existing buffer objects:
s/drm_intel_bo/brw_bo/
We only have to be careful to leave the global screen drm_intel_bo as
they are.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_batch.h | 42 +++++++++++++++
src/mesa/drivers/dri/i965/brw_compute.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.h | 69 ++++++++++++------------
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw.h | 4 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 +--
src/mesa/drivers/dri/i965/brw_object_purgeable.c | 4 +-
src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
src/mesa/drivers/dri/i965/brw_program.c | 4 +-
src/mesa/drivers/dri/i965/brw_program_cache.c | 2 +-
src/mesa/drivers/dri/i965/brw_queryobj.c | 4 +-
src/mesa/drivers/dri/i965/brw_sf_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/brw_sync.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 26 ++++-----
src/mesa/drivers/dri/i965/gen6_queryobj.c | 6 +--
src/mesa/drivers/dri/i965/gen7_sol_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_sol_state.c | 3 +-
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 4 +-
src/mesa/drivers/dri/i965/hsw_queryobj.c | 6 +--
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 18 +++----
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4 +-
src/mesa/drivers/dri/i965/intel_blit.c | 68 +++++++++++------------
src/mesa/drivers/dri/i965/intel_blit.h | 34 ++++++------
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 14 ++---
src/mesa/drivers/dri/i965/intel_buffer_objects.h | 16 +++---
src/mesa/drivers/dri/i965/intel_fbo.c | 4 +-
src/mesa/drivers/dri/i965/intel_fbo.h | 4 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 12 +++--
src/mesa/drivers/dri/i965/intel_pixel_draw.c | 2 +-
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.h | 6 +--
src/mesa/drivers/dri/i965/intel_tex.c | 6 +--
src/mesa/drivers/dri/i965/intel_tex_image.c | 3 +-
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +-
src/mesa/drivers/dri/i965/intel_upload.c | 4 +-
40 files changed, 226 insertions(+), 182 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_batch.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index dd546826d1..f38987504a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -93,6 +93,7 @@ i965_compiler_GENERATED_FILES = \
brw_nir_trig_workarounds.c
i965_FILES = \
+ brw_batch.h \
brw_binding_tables.c \
brw_blorp.c \
brw_blorp.h \
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h
b/src/mesa/drivers/dri/i965/brw_batch.h
new file mode 100644
index 0000000000..7268e26a85
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Chris Wilson <ch...@chris-wilson.co.uk>
+ */
+
+#ifndef BRW_BATCH_H
+#define BRW_BATCH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <intel_bufmgr.h>
+
+typedef drm_intel_bo brw_bo;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BRW_BATCH_H */
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index 8323d3c178..b2b41db2f9 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -37,7 +37,7 @@ static void
prepare_indirect_gpgpu_walker(struct brw_context *brw)
{
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
- drm_intel_bo *bo = brw->compute.num_work_groups_bo;
+ brw_bo *bo = brw->compute.num_work_groups_bo;
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
I915_GEM_DOMAIN_VERTEX, 0,
@@ -262,7 +262,7 @@ brw_dispatch_compute_indirect(struct gl_context *ctx,
GLintptr indirect)
struct brw_context *brw = brw_context(ctx);
static const GLuint indirect_group_counts[3] = { 0, 0, 0 };
struct gl_buffer_object *indirect_buffer = ctx->DispatchIndirectBuffer;
- drm_intel_bo *bo =
+ brw_bo *bo =
intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
indirect, 3 * sizeof(GLuint));
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 44c49f5f16..1ca927a685 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -169,7 +169,7 @@ intel_update_framebuffer(struct gl_context *ctx,
}
static bool
-intel_disable_rb_aux_buffer(struct brw_context *brw, const drm_intel_bo *bo)
+intel_disable_rb_aux_buffer(struct brw_context *brw, const brw_bo *bo)
{
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
bool found = false;
@@ -1598,7 +1598,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
const char *buffer_name)
{
struct gl_framebuffer *fb = drawable->driverPrivate;
- drm_intel_bo *bo;
+ brw_bo *bo;
if (!rb)
return;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 02114e0753..50c6255ab5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -36,6 +36,7 @@
#include <stdbool.h>
#include "main/macros.h"
#include "main/mtypes.h"
+#include "brw_batch.h"
#include "brw_structs.h"
#include "brw_compiler.h"
#include "intel_aub.h"
@@ -490,7 +491,7 @@ struct brw_cache {
struct brw_context *brw;
struct brw_cache_item **items;
- drm_intel_bo *bo;
+ brw_bo *bo;
GLuint size, n_items;
uint32_t next_offset;
@@ -522,7 +523,7 @@ enum shader_time_shader_type {
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */
- drm_intel_bo *bo;
+ brw_bo *bo;
uint32_t offset;
uint32_t size;
/** Byte stride between elements in the uploaded array */
@@ -542,7 +543,7 @@ struct brw_query_object {
struct gl_query_object Base;
/** Last query BO associated with this query. */
- drm_intel_bo *bo;
+ brw_bo *bo;
/** Last index in bo with query data for this object. */
int last_index;
@@ -559,9 +560,9 @@ enum brw_gpu_ring {
struct intel_batchbuffer {
/** Current batchbuffer being queued up. */
- drm_intel_bo *bo;
+ brw_bo *bo;
/** Last BO submitted to the hardware. Used for glFinish(). */
- drm_intel_bo *last_bo;
+ brw_bo *last_bo;
#ifdef DEBUG
uint16_t emit, total;
@@ -591,7 +592,7 @@ struct brw_transform_feedback_object {
struct gl_transform_feedback_object base;
/** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
- drm_intel_bo *offset_bo;
+ brw_bo *offset_bo;
/** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
bool zero_offsets;
@@ -604,7 +605,7 @@ struct brw_transform_feedback_object {
* @{
*/
uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
- drm_intel_bo *prim_count_bo;
+ brw_bo *prim_count_bo;
unsigned prim_count_buffer_index; /**< in number of uint64_t units */
/** @} */
@@ -643,7 +644,7 @@ struct brw_stage_state
* unless you're taking additional measures to synchronize thread execution
* across slot size changes.
*/
- drm_intel_bo *scratch_bo;
+ brw_bo *scratch_bo;
/**
* Scratch slot size allocated for each thread in the buffer object given
@@ -728,11 +729,11 @@ struct brw_context
drm_intel_context *hw_ctx;
/** BO for post-sync nonzero writes for gen6 workaround. */
- drm_intel_bo *workaround_bo;
+ brw_bo *workaround_bo;
uint8_t pipe_controls_since_last_cs_stall;
/**
- * Set of drm_intel_bo * that have been rendered to within this batchbuffer
+ * Set of brw_bo* that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
* isn't coherent with it (i.e. the sampler).
*/
@@ -750,7 +751,7 @@ struct brw_context
bool no_batch_wrap;
struct {
- drm_intel_bo *bo;
+ brw_bo *bo;
uint32_t next_offset;
} upload;
@@ -763,7 +764,7 @@ struct brw_context
bool front_buffer_dirty;
/** Framerate throttling: @{ */
- drm_intel_bo *throttle_batch[2];
+ brw_bo *throttle_batch[2];
/* Limit the number of outstanding SwapBuffers by waiting for an earlier
* frame of rendering to complete. This gives a very precise cap to the
@@ -878,7 +879,7 @@ struct brw_context
* Buffer and offset used for GL_ARB_shader_draw_parameters
* (for now, only gl_BaseVertex).
*/
- drm_intel_bo *draw_params_bo;
+ brw_bo *draw_params_bo;
uint32_t draw_params_offset;
/**
@@ -887,7 +888,7 @@ struct brw_context
* draw parameters.
*/
int gl_drawid;
- drm_intel_bo *draw_id_bo;
+ brw_bo *draw_id_bo;
uint32_t draw_id_offset;
} draw;
@@ -897,7 +898,7 @@ struct brw_context
* an indirect call, and num_work_groups_offset is valid. Otherwise,
* num_work_groups is set based on glDispatchCompute.
*/
- drm_intel_bo *num_work_groups_bo;
+ brw_bo *num_work_groups_bo;
GLintptr num_work_groups_offset;
const GLuint *num_work_groups;
} compute;
@@ -939,7 +940,7 @@ struct brw_context
const struct _mesa_index_buffer *ib;
/* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
- drm_intel_bo *bo;
+ brw_bo *bo;
uint32_t size;
GLuint type;
@@ -1027,7 +1028,7 @@ struct brw_context
* Pointer to the (intel_upload.c-generated) BO containing the uniforms
* for upload to the CURBE.
*/
- drm_intel_bo *curbe_bo;
+ brw_bo *curbe_bo;
/** Offset within curbe_bo of space for current curbe entry */
GLuint curbe_offset;
} curbe;
@@ -1133,7 +1134,7 @@ struct brw_context
* Buffer object used in place of multisampled null render targets on
* Gen6. See brw_emit_null_surface_state().
*/
- drm_intel_bo *multisampled_null_render_target_bo;
+ brw_bo *multisampled_null_render_target_bo;
uint32_t fast_clear_op;
float offset_clamp;
@@ -1145,7 +1146,7 @@ struct brw_context
/* RS hardware binding table */
struct {
- drm_intel_bo *bo;
+ brw_bo *bo;
uint32_t next_offset;
} hw_bt_pool;
@@ -1211,7 +1212,7 @@ struct brw_context
} l3;
struct {
- drm_intel_bo *bo;
+ brw_bo *bo;
const char **names;
int *ids;
enum shader_time_shader_type *types;
@@ -1304,8 +1305,8 @@ bool brw_is_query_pipelined(struct brw_query_object
*query);
/** gen6_queryobj.c */
void gen6_init_queryobj_functions(struct dd_function_table *functions);
-void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
-void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
+void brw_write_timestamp(struct brw_context *brw, brw_bo *bo, int idx);
+void brw_write_depth_count(struct brw_context *brw, brw_bo *bo, int idx);
/** hsw_queryobj.c */
void hsw_init_queryobj_functions(struct dd_function_table *functions);
@@ -1317,18 +1318,18 @@ bool brw_check_conditional_render(struct brw_context
*brw);
/** intel_batchbuffer.c */
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_store_register_mem32(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
+ brw_bo *bo, uint32_t reg, uint32_t offset);
void brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
+ brw_bo *bo, uint32_t reg, uint32_t offset);
void brw_load_register_imm32(struct brw_context *brw,
uint32_t reg, uint32_t imm);
void brw_load_register_imm64(struct brw_context *brw,
@@ -1337,9 +1338,9 @@ void brw_load_register_reg(struct brw_context *brw,
uint32_t src,
uint32_t dest);
void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
uint32_t dest);
-void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+void brw_store_data_imm32(struct brw_context *brw, brw_bo *bo,
uint32_t offset, uint32_t imm);
-void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+void brw_store_data_imm64(struct brw_context *brw, brw_bo *bo,
uint32_t offset, uint64_t imm);
/*======================================================================
@@ -1376,7 +1377,7 @@ brw_get_scratch_size(int size)
return MAX2(1024, util_next_power_of_two(size));
}
void brw_get_scratch_bo(struct brw_context *brw,
- drm_intel_bo **scratch_bo, int size);
+ brw_bo **scratch_bo, int size);
void brw_alloc_stage_scratch(struct brw_context *brw,
struct brw_stage_state *stage_state,
unsigned per_thread_size,
@@ -1440,12 +1441,12 @@ void brw_prepare_vertices(struct brw_context *brw);
/* brw_wm_surface_state.c */
void brw_init_surface_formats(struct brw_context *brw);
void brw_create_constant_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset);
void brw_create_buffer_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset);
@@ -1475,9 +1476,9 @@ bool brw_render_target_supported(struct brw_context *brw,
uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
/* intel_buffer_objects.c */
-int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
+int brw_bo_map(struct brw_context *brw, brw_bo *bo, int write_enable,
const char *bo_name);
-int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
+int brw_bo_map_gtt(struct brw_context *brw, brw_bo *bo,
const char *bo_name);
/* intel_extensions.c */
@@ -1740,7 +1741,7 @@ void brw_fini_pipe_control(struct brw_context *brw);
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- drm_intel_bo *bo, uint32_t offset,
+ brw_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 75e2578763..0805bac3d2 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -219,7 +219,7 @@ brw_emit_prim(struct brw_context *brw,
ADVANCE_BATCH();
} else if (prim->is_indirect) {
struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer;
- drm_intel_bo *bo = intel_bufferobj_buffer(brw,
+ brw_bo *bo = intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
prim->indirect_offset, 5 * sizeof(GLuint));
diff --git a/src/mesa/drivers/dri/i965/brw_draw.h
b/src/mesa/drivers/dri/i965/brw_draw.h
index 64ad9b5cd6..89256c4585 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.h
+++ b/src/mesa/drivers/dri/i965/brw_draw.h
@@ -27,14 +27,14 @@
#define BRW_DRAW_H
#include "main/mtypes.h" /* for struct gl_context... */
-#include "intel_bufmgr.h"
+#include "brw_batch.h"
struct brw_context;
uint32_t *
brw_emit_vertex_buffer_state(struct brw_context *brw,
unsigned buffer_nr,
- drm_intel_bo *bo,
+ brw_bo *bo,
unsigned start_offset,
unsigned end_offset,
unsigned stride,
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 88be736e81..21d2ae3b92 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -707,7 +707,7 @@ brw_prepare_shader_draw_parameters(struct brw_context *brw)
uint32_t *
brw_emit_vertex_buffer_state(struct brw_context *brw,
unsigned buffer_nr,
- drm_intel_bo *bo,
+ brw_bo *bo,
unsigned start_offset,
unsigned end_offset,
unsigned stride,
@@ -1052,7 +1052,7 @@ brw_upload_indices(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
GLuint ib_size;
- drm_intel_bo *old_bo = brw->ib.bo;
+ brw_bo *old_bo = brw->ib.bo;
struct gl_buffer_object *bufferobj;
GLuint offset;
GLuint ib_type_size;
@@ -1096,7 +1096,7 @@ brw_upload_indices(struct brw_context *brw)
ctx->Driver.UnmapBuffer(ctx, bufferobj, MAP_INTERNAL);
} else {
- drm_intel_bo *bo =
+ brw_bo *bo =
intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
offset, ib_size);
if (bo != brw->ib.bo) {
diff --git a/src/mesa/drivers/dri/i965/brw_object_purgeable.c
b/src/mesa/drivers/dri/i965/brw_object_purgeable.c
index d3dba8c0af..69c9d48881 100644
--- a/src/mesa/drivers/dri/i965/brw_object_purgeable.c
+++ b/src/mesa/drivers/dri/i965/brw_object_purgeable.c
@@ -38,7 +38,7 @@
#include "intel_mipmap_tree.h"
static GLenum
-intel_buffer_purgeable(drm_intel_bo *buffer)
+intel_buffer_purgeable(brw_bo *buffer)
{
int retained = 0;
@@ -101,7 +101,7 @@ intel_render_object_purgeable(struct gl_context * ctx,
}
static int
-intel_bo_unpurgeable(drm_intel_bo *buffer)
+intel_bo_unpurgeable(brw_bo *buffer)
{
int retained;
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index eb472e162f..658b8e8dd9 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -176,7 +176,7 @@ brw_emit_pipe_control_flush(struct brw_context *brw,
uint32_t flags)
*/
void
brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- drm_intel_bo *bo, uint32_t offset,
+ brw_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper)
{
if (brw->gen >= 8) {
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index 1c954aee31..fe5338b8b2 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -329,9 +329,9 @@ brw_add_texrect_params(struct gl_program *prog)
void
brw_get_scratch_bo(struct brw_context *brw,
- drm_intel_bo **scratch_bo, int size)
+ brw_bo **scratch_bo, int size)
{
- drm_intel_bo *old_bo = *scratch_bo;
+ brw_bo *old_bo = *scratch_bo;
if (old_bo && old_bo->size < size) {
drm_intel_bo_unreference(old_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c
b/src/mesa/drivers/dri/i965/brw_program_cache.c
index ad3ed8d7ba..6128860456 100644
--- a/src/mesa/drivers/dri/i965/brw_program_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_program_cache.c
@@ -170,7 +170,7 @@ static void
brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
{
struct brw_context *brw = cache->brw;
- drm_intel_bo *new_bo;
+ brw_bo *new_bo;
new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
if (brw->has_llc)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 4794e7dcf2..6e5527d692 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -45,7 +45,7 @@
* Emit PIPE_CONTROLs to write the current GPU timestamp into a buffer.
*/
void
-brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
+brw_write_timestamp(struct brw_context *brw, brw_bo *query_bo, int idx)
{
if (brw->gen == 6) {
/* Emit Sandybridge workaround flush: */
@@ -67,7 +67,7 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo
*query_bo, int idx)
* Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
*/
void
-brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
+brw_write_depth_count(struct brw_context *brw, brw_bo *query_bo, int idx)
{
uint32_t flags = PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_DEPTH_STALL;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c
b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 89406fc9cb..6d1f1998b6 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -134,7 +134,7 @@ static void upload_sf_unit( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
- drm_intel_bo *bo = brw->batch.bo;
+ brw_bo *bo = brw->batch.bo;
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 176557b7c4..0feeeb08dc 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -273,7 +273,7 @@ int brw_get_texture_swizzle(const struct gl_context *ctx,
void brw_emit_buffer_surface_state(struct brw_context *brw,
uint32_t *out_offset,
- drm_intel_bo *bo,
+ brw_bo *bo,
unsigned buffer_offset,
unsigned surface_format,
unsigned buffer_size,
diff --git a/src/mesa/drivers/dri/i965/brw_sync.c
b/src/mesa/drivers/dri/i965/brw_sync.c
index 37c19b1c1c..edb6a49cc6 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -45,7 +45,7 @@
struct brw_fence {
struct brw_context *brw;
/** The fence waits for completion of this batch. */
- drm_intel_bo *batch_bo;
+ brw_bo *batch_bo;
mtx_t mutex;
bool signalled;
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 5665735f43..c87b8fae7c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -74,7 +74,7 @@ brw_upload_pull_constants(struct brw_context *brw,
/* BRW_NEW_*_PROG_DATA | _NEW_PROGRAM_CONSTANTS */
uint32_t size = prog_data->nr_pull_params * 4;
- drm_intel_bo *const_bo = NULL;
+ brw_bo *const_bo = NULL;
uint32_t const_offset;
gl_constant_value *constants = intel_upload_space(brw, size, 64,
&const_bo, &const_offset);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ad5013f287..c93d11bf88 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -132,7 +132,7 @@ brw_emit_surface_state(struct brw_context *brw,
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
- drm_intel_bo *aux_bo;
+ brw_bo *aux_bo;
struct isl_surf *aux_surf = NULL, aux_surf_s;
uint64_t aux_offset = 0;
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
@@ -646,7 +646,7 @@ brw_update_texture_surface(struct gl_context *ctx,
void
brw_emit_buffer_surface_state(struct brw_context *brw,
uint32_t *out_offset,
- drm_intel_bo *bo,
+ brw_bo *bo,
unsigned buffer_offset,
unsigned surface_format,
unsigned buffer_size,
@@ -684,7 +684,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
struct intel_buffer_object *intel_obj =
intel_buffer_object(tObj->BufferObject);
uint32_t size = tObj->BufferSize;
- drm_intel_bo *bo = NULL;
+ brw_bo *bo = NULL;
mesa_format format = tObj->_BufferObjectFormat;
uint32_t brw_format = brw_format_for_mesa_format(format);
int texel_size = _mesa_get_format_bytes(format);
@@ -713,7 +713,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
*/
void
brw_create_constant_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset)
@@ -730,7 +730,7 @@ brw_create_constant_surface(struct brw_context *brw,
*/
void
brw_create_buffer_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset)
@@ -759,9 +759,9 @@ brw_update_sol_surface(struct brw_context *brw,
{
struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
uint32_t offset_bytes = 4 * offset_dwords;
- drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
- offset_bytes,
- buffer_obj->Size - offset_bytes);
+ brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
+ offset_bytes,
+ buffer_obj->Size - offset_bytes);
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
out_offset);
uint32_t pitch_minus_1 = 4*stride_dwords - 1;
@@ -896,7 +896,7 @@ brw_emit_null_surface_state(struct brw_context *brw,
* - Surface Format must be R8G8B8A8_UNORM.
*/
unsigned surface_type = BRW_SURFACE_NULL;
- drm_intel_bo *bo = NULL;
+ brw_bo *bo = NULL;
unsigned pitch_minus_1 = 0;
uint32_t multisampling_state = 0;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
@@ -1393,7 +1393,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct
gl_program *prog,
GLsizeiptr size = binding->BufferObject->Size - binding->Offset;
if (!binding->AutomaticSize)
size = MIN2(size, binding->Size);
- drm_intel_bo *bo =
+ brw_bo *bo =
intel_bufferobj_buffer(brw, intel_bo,
binding->Offset,
size);
@@ -1418,7 +1418,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct
gl_program *prog,
GLsizeiptr size = binding->BufferObject->Size - binding->Offset;
if (!binding->AutomaticSize)
size = MIN2(size, binding->Size);
- drm_intel_bo *bo =
+ brw_bo *bo =
intel_bufferobj_buffer(brw, intel_bo,
binding->Offset,
size);
@@ -1497,7 +1497,7 @@ brw_upload_abo_surfaces(struct brw_context *brw,
&ctx->AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding];
struct intel_buffer_object *intel_bo =
intel_buffer_object(binding->BufferObject);
- drm_intel_bo *bo = intel_bufferobj_buffer(
+ brw_bo *bo = intel_bufferobj_buffer(
brw, intel_bo, binding->Offset, intel_bo->Base.Size -
binding->Offset);
brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
@@ -1852,7 +1852,7 @@ brw_upload_cs_work_groups_surface(struct brw_context *brw)
const unsigned surf_idx =
cs_prog_data->binding_table.work_groups_start;
uint32_t *surf_offset = &brw->cs.base.surf_offset[surf_idx];
- drm_intel_bo *bo;
+ brw_bo *bo;
uint32_t bo_offset;
if (brw->compute.num_work_groups_bo == NULL) {
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 2920955821..534badbb99 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -76,7 +76,7 @@ set_query_availability(struct brw_context *brw, struct
brw_query_object *query,
static void
write_primitives_generated(struct brw_context *brw,
- drm_intel_bo *query_bo, int stream, int idx)
+ brw_bo *query_bo, int stream, int idx)
{
brw_emit_mi_flush(brw);
@@ -92,7 +92,7 @@ write_primitives_generated(struct brw_context *brw,
static void
write_xfb_primitives_written(struct brw_context *brw,
- drm_intel_bo *bo, int stream, int idx)
+ brw_bo *bo, int stream, int idx)
{
brw_emit_mi_flush(brw);
@@ -115,7 +115,7 @@ pipeline_target_to_index(int target)
}
static void
-emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo,
+emit_pipeline_stat(struct brw_context *brw, brw_bo *bo,
int stream, int target, int idx)
{
/* One source of confusion is the tessellation shader statistics. The
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index d894aeb979..d091eb6cec 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -51,7 +51,7 @@ upload_3dstate_so_buffers(struct brw_context *brw)
for (i = 0; i < 4; i++) {
struct intel_buffer_object *bufferobj =
intel_buffer_object(xfb_obj->Buffers[i]);
- drm_intel_bo *bo;
+ brw_bo *bo;
uint32_t start, end;
uint32_t stride;
diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c
b/src/mesa/drivers/dri/i965/gen8_sol_state.c
index f964c6f8c4..5fbb7c2344 100644
--- a/src/mesa/drivers/dri/i965/gen8_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c
@@ -69,8 +69,7 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
uint32_t start = xfb_obj->Offset[i];
assert(start % 4 == 0);
uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
- drm_intel_bo *bo =
- intel_bufferobj_buffer(brw, bufferobj, start, end - start);
+ brw_bo *bo = intel_bufferobj_buffer(brw, bufferobj, start, end - start);
assert(end <= bo->size);
BEGIN_BATCH(8);
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 0b3858ea98..2e6ee0cb8b 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -72,7 +72,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t
ss_offset,
{
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
- drm_intel_bo *bo = address.buffer;
+ brw_bo *bo = address.buffer;
drm_intel_bo_emit_reloc(brw->batch.bo, ss_offset,
bo, address.offset + delta,
@@ -185,7 +185,7 @@ genX(blorp_exec)(struct blorp_batch *batch,
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage,
RENDER_RING);
intel_batchbuffer_save_state(brw);
- drm_intel_bo *saved_bo = brw->batch.bo;
+ brw_bo *saved_bo = brw->batch.bo;
uint32_t saved_used = USED_BATCH(brw->batch);
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c
b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index 054f874b80..2b771a213c 100644
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -280,7 +280,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct
brw_query_object *query,
* Store immediate data into the user buffer using the requested size.
*/
static void
-store_query_result_imm(struct brw_context *brw, drm_intel_bo *bo,
+store_query_result_imm(struct brw_context *brw, brw_bo *bo,
uint32_t offset, GLenum ptype, uint64_t imm)
{
switch (ptype) {
@@ -298,7 +298,7 @@ store_query_result_imm(struct brw_context *brw,
drm_intel_bo *bo,
}
static void
-set_predicate(struct brw_context *brw, drm_intel_bo *query_bo)
+set_predicate(struct brw_context *brw, brw_bo *query_bo)
{
brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull);
@@ -322,7 +322,7 @@ set_predicate(struct brw_context *brw, drm_intel_bo
*query_bo)
* query has not finished yet.
*/
static void
-store_query_result_reg(struct brw_context *brw, drm_intel_bo *bo,
+store_query_result_reg(struct brw_context *brw, brw_bo *bo,
uint32_t offset, GLenum ptype, uint32_t reg,
const bool pipelined)
{
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 036cb1c854..aaa02d3df7 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -441,7 +441,7 @@ _intel_batchbuffer_flush(struct brw_context *brw,
*/
uint32_t
intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
- drm_intel_bo *buffer, uint32_t offset,
+ brw_bo *buffer, uint32_t offset,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
@@ -462,7 +462,7 @@ intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
uint64_t
intel_batchbuffer_reloc64(struct intel_batchbuffer *batch,
- drm_intel_bo *buffer, uint32_t offset,
+ brw_bo *buffer, uint32_t offset,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
@@ -493,7 +493,7 @@ intel_batchbuffer_data(struct brw_context *brw,
static void
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset,
int size)
@@ -525,7 +525,7 @@ load_sized_register_mem(struct brw_context *brw,
void
brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
@@ -535,7 +535,7 @@ brw_load_register_mem(struct brw_context *brw,
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
@@ -547,7 +547,7 @@ brw_load_register_mem64(struct brw_context *brw,
*/
void
brw_store_register_mem32(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+ brw_bo *bo, uint32_t reg, uint32_t offset)
{
assert(brw->gen >= 6);
@@ -573,7 +573,7 @@ brw_store_register_mem32(struct brw_context *brw,
*/
void
brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+ brw_bo *bo, uint32_t reg, uint32_t offset)
{
assert(brw->gen >= 6);
@@ -674,7 +674,7 @@ brw_load_register_reg64(struct brw_context *brw, uint32_t
src, uint32_t dest)
* Write 32-bits of immediate data to a GPU memory buffer.
*/
void
-brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+brw_store_data_imm32(struct brw_context *brw, brw_bo *bo,
uint32_t offset, uint32_t imm)
{
assert(brw->gen >= 6);
@@ -697,7 +697,7 @@ brw_store_data_imm32(struct brw_context *brw, drm_intel_bo
*bo,
* Write 64-bits of immediate data to a GPU memory buffer.
*/
void
-brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+brw_store_data_imm64(struct brw_context *brw, brw_bo *bo,
uint32_t offset, uint64_t imm)
{
assert(brw->gen >= 6);
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 59233ce3d2..04650a7d0f 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -70,13 +70,13 @@ void intel_batchbuffer_data(struct brw_context *brw,
enum brw_gpu_ring ring);
uint32_t intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
- drm_intel_bo *buffer,
+ brw_bo *buffer,
uint32_t offset,
uint32_t read_domains,
uint32_t write_domain,
uint32_t delta);
uint64_t intel_batchbuffer_reloc64(struct intel_batchbuffer *batch,
- drm_intel_bo *buffer,
+ brw_bo *buffer,
uint32_t offset,
uint32_t read_domains,
uint32_t write_domain,
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index d95de1f5bd..cb44a87b99 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -477,11 +477,11 @@ alignment_valid(struct brw_context *brw, unsigned offset,
uint32_t tiling)
static bool
can_fast_copy_blit(struct brw_context *brw,
- drm_intel_bo *src_buffer,
+ brw_bo *src_buffer,
int16_t src_x, int16_t src_y,
uintptr_t src_offset, uint32_t src_pitch,
uint32_t src_tiling, uint32_t src_tr_mode,
- drm_intel_bo *dst_buffer,
+ brw_bo *dst_buffer,
int16_t dst_x, int16_t dst_y,
uintptr_t dst_offset, uint32_t dst_pitch,
uint32_t dst_tiling, uint32_t dst_tr_mode,
@@ -575,26 +575,26 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
*/
bool
intelEmitCopyBlit(struct brw_context *brw,
- GLuint cpp,
- GLshort src_pitch,
- drm_intel_bo *src_buffer,
- GLuint src_offset,
- uint32_t src_tiling,
- uint32_t src_tr_mode,
- GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
- GLuint dst_offset,
- uint32_t dst_tiling,
- uint32_t dst_tr_mode,
- GLshort src_x, GLshort src_y,
- GLshort dst_x, GLshort dst_y,
- GLshort w, GLshort h,
- GLenum logic_op)
+ GLuint cpp,
+ GLshort src_pitch,
+ brw_bo *src_buffer,
+ GLuint src_offset,
+ uint32_t src_tiling,
+ uint32_t src_tr_mode,
+ GLshort dst_pitch,
+ brw_bo *dst_buffer,
+ GLuint dst_offset,
+ uint32_t dst_tiling,
+ uint32_t dst_tr_mode,
+ GLshort src_x, GLshort src_y,
+ GLshort dst_x, GLshort dst_y,
+ GLshort w, GLshort h,
+ GLenum logic_op)
{
GLuint CMD, BR13, pass = 0;
int dst_y2 = dst_y + h;
int dst_x2 = dst_x + w;
- drm_intel_bo *aper_array[3];
+ brw_bo *aper_array[3];
bool dst_y_tiled = dst_tiling == I915_TILING_Y;
bool src_y_tiled = src_tiling == I915_TILING_Y;
bool use_fast_copy_blit = false;
@@ -767,16 +767,16 @@ intelEmitCopyBlit(struct brw_context *brw,
bool
intelEmitImmediateColorExpandBlit(struct brw_context *brw,
- GLuint cpp,
- GLubyte *src_bits, GLuint src_size,
- GLuint fg_color,
- GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
- GLuint dst_offset,
- uint32_t dst_tiling,
- GLshort x, GLshort y,
- GLshort w, GLshort h,
- GLenum logic_op)
+ GLuint cpp,
+ GLubyte *src_bits, GLuint src_size,
+ GLuint fg_color,
+ GLshort dst_pitch,
+ brw_bo *dst_buffer,
+ GLuint dst_offset,
+ uint32_t dst_tiling,
+ GLshort x, GLshort y,
+ GLshort w, GLshort h,
+ GLenum logic_op)
{
int dwords = ALIGN(src_size, 8) / 4;
uint32_t opcode, br13, blit_cmd;
@@ -855,11 +855,11 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
*/
void
intel_emit_linear_blit(struct brw_context *brw,
- drm_intel_bo *dst_bo,
- unsigned int dst_offset,
- drm_intel_bo *src_bo,
- unsigned int src_offset,
- unsigned int size)
+ brw_bo *dst_bo,
+ unsigned int dst_offset,
+ brw_bo *src_bo,
+ unsigned int src_offset,
+ unsigned int size)
{
struct gl_context *ctx = &brw->ctx;
GLuint pitch, height;
@@ -920,7 +920,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
{
uint32_t BR13, CMD;
int pitch, cpp;
- drm_intel_bo *aper_array[2];
+ brw_bo *aper_array[2];
pitch = mt->pitch;
cpp = mt->cpp;
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
b/src/mesa/drivers/dri/i965/intel_blit.h
index 6925795656..e8d1c8c679 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -32,12 +32,12 @@ bool
intelEmitCopyBlit(struct brw_context *brw,
GLuint cpp,
GLshort src_pitch,
- drm_intel_bo *src_buffer,
+ brw_bo *src_buffer,
GLuint src_offset,
uint32_t src_tiling,
uint32_t src_tr_mode,
GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
+ brw_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
uint32_t dst_tr_mode,
@@ -69,21 +69,21 @@ bool intel_miptree_copy(struct brw_context *brw,
bool
intelEmitImmediateColorExpandBlit(struct brw_context *brw,
- GLuint cpp,
- GLubyte *src_bits, GLuint src_size,
- GLuint fg_color,
- GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
- GLuint dst_offset,
- uint32_t dst_tiling,
- GLshort x, GLshort y,
- GLshort w, GLshort h,
- GLenum logic_op);
+ GLuint cpp,
+ GLubyte *src_bits, GLuint src_size,
+ GLuint fg_color,
+ GLshort dst_pitch,
+ brw_bo *dst_buffer,
+ GLuint dst_offset,
+ uint32_t dst_tiling,
+ GLshort x, GLshort y,
+ GLshort w, GLshort h,
+ GLenum logic_op);
void intel_emit_linear_blit(struct brw_context *brw,
- drm_intel_bo *dst_bo,
- unsigned int dst_offset,
- drm_intel_bo *src_bo,
- unsigned int src_offset,
- unsigned int size);
+ brw_bo *dst_bo,
+ unsigned int dst_offset,
+ brw_bo *src_bo,
+ unsigned int src_offset,
+ unsigned int size);
#endif
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index fde45d8f41..dac3329e75 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -46,7 +46,7 @@
*/
int
brw_bo_map(struct brw_context *brw,
- drm_intel_bo *bo, int write_enable,
+ brw_bo *bo, int write_enable,
const char *bo_name)
{
if (likely(!brw->perf_debug) || !drm_intel_bo_busy(bo))
@@ -63,7 +63,7 @@ brw_bo_map(struct brw_context *brw,
}
int
-brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo, const char *bo_name)
+brw_bo_map_gtt(struct brw_context *brw, brw_bo *bo, const char *bo_name)
{
if (likely(!brw->perf_debug) || !drm_intel_bo_busy(bo))
return drm_intel_gem_bo_map_gtt(bo);
@@ -93,7 +93,7 @@ mark_buffer_inactive(struct intel_buffer_object *intel_obj)
intel_obj->gpu_active_end = 0;
}
-/** Allocates a new drm_intel_bo to store the data for the buffer object. */
+/** Allocates a new brw_bo to store the data for the buffer object. */
static void
alloc_buffer_object(struct brw_context *brw,
struct intel_buffer_object *intel_obj)
@@ -284,8 +284,8 @@ brw_buffer_subdata(struct gl_context *ctx,
(long)offset, (long)offset + size, (long)(size/1024),
intel_obj->gpu_active_start,
intel_obj->gpu_active_end);
- drm_intel_bo *temp_bo =
- drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64);
+ brw_bo *temp_bo =
+ drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64);
drm_intel_bo_subdata(temp_bo, 0, size, data);
@@ -580,7 +580,7 @@ brw_unmap_buffer(struct gl_context *ctx,
* Anywhere that uses buffer objects in the pipeline should be using this to
* mark the range of the buffer that is being accessed by the pipeline.
*/
-drm_intel_bo *
+brw_bo *
intel_bufferobj_buffer(struct brw_context *brw,
struct intel_buffer_object *intel_obj,
uint32_t offset, uint32_t size)
@@ -614,7 +614,7 @@ brw_copy_buffer_subdata(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct intel_buffer_object *intel_src = intel_buffer_object(src);
struct intel_buffer_object *intel_dst = intel_buffer_object(dst);
- drm_intel_bo *src_bo, *dst_bo;
+ brw_bo *src_bo, *dst_bo;
if (size == 0)
return;
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.h
b/src/mesa/drivers/dri/i965/intel_buffer_objects.h
index 7fe08a6399..f7fa34d565 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.h
@@ -39,9 +39,9 @@ struct gl_buffer_object;
struct intel_buffer_object
{
struct gl_buffer_object Base;
- drm_intel_bo *buffer; /* the low-level buffer manager's buffer handle */
+ brw_bo *buffer; /* the low-level buffer manager's buffer handle */
- drm_intel_bo *range_map_bo[MAP_COUNT];
+ brw_bo *range_map_bo[MAP_COUNT];
/**
* Alignment offset from the range_map_bo temporary mapping to the returned
@@ -83,22 +83,22 @@ struct intel_buffer_object
/* Get the bm buffer associated with a GL bufferobject:
*/
-drm_intel_bo *intel_bufferobj_buffer(struct brw_context *brw,
- struct intel_buffer_object *obj,
- uint32_t offset,
- uint32_t size);
+brw_bo *intel_bufferobj_buffer(struct brw_context *brw,
+ struct intel_buffer_object *obj,
+ uint32_t offset,
+ uint32_t size);
void intel_upload_data(struct brw_context *brw,
const void *data,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ brw_bo **out_bo,
uint32_t *out_offset);
void *intel_upload_space(struct brw_context *brw,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ brw_bo **out_bo,
uint32_t *out_offset);
void intel_upload_finish(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 30033c369b..a07f33242b 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -1057,7 +1057,7 @@ brw_render_cache_set_clear(struct brw_context *brw)
}
void
-brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo)
+brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo)
{
_mesa_set_add(brw->render_cache, bo);
}
@@ -1075,7 +1075,7 @@ brw_render_cache_set_add_bo(struct brw_context *brw,
drm_intel_bo *bo)
* different caches within a batchbuffer, it's all our responsibility.
*/
void
-brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo)
+brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo)
{
if (!_mesa_set_search(brw->render_cache, bo))
return;
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h
b/src/mesa/drivers/dri/i965/intel_fbo.h
index e6f6156022..094eb61915 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -236,8 +236,8 @@ intel_renderbuffer_upsample(struct brw_context *brw,
struct intel_renderbuffer *irb);
void brw_render_cache_set_clear(struct brw_context *brw);
-void brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo);
-void brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo
*bo);
+void brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo);
+void brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo);
unsigned
intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 073ae886ea..f611c8b3df 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -758,7 +758,7 @@ intel_miptree_create(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
- drm_intel_bo *bo,
+ brw_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
@@ -822,7 +822,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t width, uint32_t height,
uint32_t pitch)
{
@@ -2501,7 +2501,7 @@ intel_miptree_map_raw(struct brw_context *brw, struct
intel_mipmap_tree *mt)
*/
intel_miptree_all_slices_resolve_color(brw, mt, 0);
- drm_intel_bo *bo = mt->bo;
+ brw_bo *bo = mt->bo;
if (drm_intel_bo_references(brw->batch.bo, bo))
intel_batchbuffer_flush(brw);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 476c46b135..b3a140244d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -31,7 +31,7 @@
* The hardware has a fixed layout of a texture depending on parameters such
* as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
* mipmap levels. The individual level/layer slices are each 2D rectangles of
- * pixels at some x/y offset from the start of the drm_intel_bo.
+ * pixels at some x/y offset from the start of the brw_bo.
*
* Original OpenGL allowed texture miplevels to be specified in arbitrary
* order, and a texture may change size over time. Thus, each
@@ -52,6 +52,8 @@
#include "intel_resolve_map.h"
#include <GL/internal/dri_interface.h>
+#include "brw_batch.h"
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -279,7 +281,7 @@ struct intel_miptree_aux_buffer
* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
* @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
*/
- drm_intel_bo *bo;
+ brw_bo *bo;
/**
* Offset into bo where the surface starts.
@@ -352,7 +354,7 @@ struct intel_mipmap_tree
* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
* @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
*/
- drm_intel_bo *bo;
+ brw_bo *bo;
/**
* Pitch in bytes.
@@ -711,7 +713,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct
brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
- drm_intel_bo *bo,
+ brw_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
@@ -723,7 +725,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- drm_intel_bo *bo,
+ brw_bo *bo,
uint32_t width, uint32_t height,
uint32_t pitch);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index 17f6592e30..892ad748ef 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -57,7 +57,7 @@ do_blit_drawpixels(struct gl_context * ctx,
struct brw_context *brw = brw_context(ctx);
struct intel_buffer_object *src = intel_buffer_object(unpack->BufferObj);
GLuint src_offset;
- drm_intel_bo *src_buffer;
+ brw_bo *src_buffer;
DBG("%s\n", __func__);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 345a9d9ccf..05186ce4e2 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -81,7 +81,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
int dst_pitch;
/* The miptree's buffer. */
- drm_intel_bo *bo;
+ brw_bo *bo;
int error = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h
b/src/mesa/drivers/dri/i965/intel_screen.h
index 0fb83e724f..d80632a46d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -42,6 +42,9 @@ struct intel_screen
int deviceID;
struct gen_device_info devinfo;
+ dri_bufmgr *bufmgr;
+ drm_intel_bo *workaround_bo;
+
__DRIscreen *driScrnPriv;
uint64_t max_gtt_map_object_size;
@@ -73,9 +76,6 @@ struct intel_screen
#define KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3 (1<<3)
#define KERNEL_ALLOWS_COMPUTE_DISPATCH (1<<4)
- dri_bufmgr *bufmgr;
- drm_intel_bo *workaround_bo;
-
/**
* A unique ID for shader programs.
*/
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c
b/src/mesa/drivers/dri/i965/intel_tex.c
index 12a346838f..8140d1adf7 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -333,9 +333,9 @@ intel_set_texture_storage_for_buffer_object(struct
gl_context *ctx,
assert(intel_texobj->mt == NULL);
- drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
- buffer_offset,
- row_stride * image->Height);
+ brw_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
+ buffer_offset,
+ row_stride * image->Height);
intel_texobj->mt =
intel_miptree_create_for_bo(brw, bo,
image->TexFormat,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 34e59c921d..34ab787327 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -178,7 +178,6 @@ intel_set_texture_image_mt(struct brw_context *brw,
struct gl_texture_image *image,
GLenum internal_format,
struct intel_mipmap_tree *mt)
-
{
struct gl_texture_object *texobj = image->TexObject;
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
@@ -466,7 +465,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
int dst_pitch;
/* The miptree's buffer. */
- drm_intel_bo *bo;
+ brw_bo *bo;
int error = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 7899efc04e..f981e46fce 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -83,7 +83,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
int src_pitch;
/* The miptree's buffer. */
- drm_intel_bo *bo;
+ brw_bo *bo;
int error = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_upload.c
b/src/mesa/drivers/dri/i965/intel_upload.c
index 9e0f0c02e2..82d9ef6e15 100644
--- a/src/mesa/drivers/dri/i965/intel_upload.c
+++ b/src/mesa/drivers/dri/i965/intel_upload.c
@@ -82,7 +82,7 @@ void *
intel_upload_space(struct brw_context *brw,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ brw_bo **out_bo,
uint32_t *out_offset)
{
uint32_t offset;
@@ -124,7 +124,7 @@ intel_upload_data(struct brw_context *brw,
const void *data,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ brw_bo **out_bo,
uint32_t *out_offset)
{
void *dst = intel_upload_space(brw, size, alignment, out_bo, out_offset);
--
2.11.0
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