We only need the batch promotion if we need to modify privileged registers,
so only request it when we do register loads and stores.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.c | 7 ++++++-
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_compute.c | 1 +
src/mesa/drivers/dri/i965/brw_draw.c | 1 +
src/mesa/drivers/dri/i965/brw_pipelined_register.c | 10 ++++++++++
src/mesa/drivers/dri/i965/gen7_l3_state.c | 3 +++
src/mesa/drivers/dri/i965/hsw_queryobj.c | 1 +
src/mesa/drivers/dri/i965/hsw_sol.c | 1 +
src/mesa/drivers/dri/i965/intel_blit.c | 1 +
9 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.c
b/src/mesa/drivers/dri/i965/brw_batch.c
index e4d0d4c8b2..47f6290ef2 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_batch.c
@@ -651,6 +651,8 @@ int brw_batch_init(struct brw_batch *batch,
batch->no_hw = screen->no_hw;
batch->gen = devinfo->gen;
+ if (devinfo->gen == 7)
+ batch->length_flag = BATCH_ENABLE_MMIO;
batch->needs_pipecontrol_ggtt_wa = devinfo->gen == 6;
batch->reloc_size = 512;
batch->exec_size = 256;
@@ -1161,7 +1163,10 @@ static uint32_t __brw_batch_finish(struct brw_batch
*batch,
}
batch->map[batch->emit.nbatch] = 0xa << 23;
- return 4*((batch->emit.nbatch + 2) & ~1);
+ if (batch->flags & batch->length_flag)
+ return 4*((batch->emit.nbatch + 2) & ~1);
+ else
+ return 0;
}
static void
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h
b/src/mesa/drivers/dri/i965/brw_batch.h
index c8fa0fa531..f8b98023ba 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -109,7 +109,9 @@ typedef struct brw_batch {
uint32_t flags;
#define BATCH_DIRTY (1 << 31)
#define BATCH_HAS_STATE_BASE (1 << 30)
+#define BATCH_ENABLE_MMIO (1 << 29)
uint32_t base_flags;
+ uint32_t length_flag;
enum brw_gpu_ring ring;
uint32_t hw_ctx;
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index 0c5f76ab00..ae08e7fa62 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -62,6 +62,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
OUT_BATCH(0u);
OUT_BATCH(MI_PREDICATE_SRC1 + 4);
OUT_BATCH(0u);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_x_size into SRC0 */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 5ebecff87e..f573c210f1 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -217,6 +217,7 @@ brw_emit_prim(struct brw_context *brw,
OUT_BATCH(0);
OUT_BATCH(GEN7_3DPRIM_START_INSTANCE);
OUT_BATCH(0);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
} else if (prim->is_indirect) {
struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer;
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
index 128f2e0eb3..2b62797e15 100644
--- a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
@@ -45,6 +45,7 @@ load_sized_register_mem(struct brw_context *brw,
OUT_BATCH(reg + i * 4);
OUT_RELOC64(bo, domains, offset + i * 4);
}
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3 * size);
@@ -53,6 +54,7 @@ load_sized_register_mem(struct brw_context *brw,
OUT_BATCH(reg + i * 4);
OUT_RELOC(bo, domains, offset + i * 4);
}
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
}
@@ -91,12 +93,14 @@ brw_store_register_mem32(struct brw_context *brw,
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
}
@@ -122,6 +126,7 @@ brw_store_register_mem64(struct brw_context *brw,
OUT_BATCH(reg + sizeof(uint32_t));
OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true),
offset + sizeof(uint32_t));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
} else {
BEGIN_BATCH(6);
@@ -131,6 +136,7 @@ brw_store_register_mem64(struct brw_context *brw,
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset + sizeof(uint32_t));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
}
@@ -147,6 +153,7 @@ brw_load_register_imm32(struct brw_context *brw, uint32_t
reg, uint32_t imm)
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(reg);
OUT_BATCH(imm);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
@@ -164,6 +171,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t
reg, uint64_t imm)
OUT_BATCH(imm & 0xffffffff);
OUT_BATCH(reg + 4);
OUT_BATCH(imm >> 32);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
@@ -179,6 +187,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t
src, uint32_t dest)
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
OUT_BATCH(src);
OUT_BATCH(dest);
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
@@ -197,6 +206,7 @@ brw_load_register_reg64(struct brw_context *brw, uint32_t
src, uint32_t dest)
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
OUT_BATCH(src + sizeof(uint32_t));
OUT_BATCH(dest + sizeof(uint32_t));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 59c3dd33fd..8a8667e197 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -129,6 +129,7 @@ setup_l3_config(struct brw_context *brw, const struct
gen_l3_config *cfg)
SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
} else {
@@ -172,6 +173,7 @@ setup_l3_config(struct brw_context *brw, const struct
gen_l3_config *cfg)
SET_FIELD(cfg->n[GEN_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
if (can_do_hsw_l3_atomics(brw->screen)) {
@@ -185,6 +187,7 @@ setup_l3_config(struct brw_context *brw, const struct
gen_l3_config *cfg)
OUT_BATCH(HSW_ROW_CHICKEN3);
OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
(has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
}
diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c
b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index d15a554270..8ce9711c99 100644
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -339,6 +339,7 @@ store_query_result_reg(struct brw_context *brw, brw_bo *bo,
OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset + 4 * i);
}
}
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c
b/src/mesa/drivers/dri/i965/hsw_sol.c
index 04f5bbf595..8803a9f88c 100644
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -179,6 +179,7 @@ hsw_begin_transform_feedback(struct gl_context *ctx, GLenum
mode,
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(0);
}
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 0e865797c3..50f8326531 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -130,6 +130,7 @@ set_blitter_tiling(struct brw_context *brw,
OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
(dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
(src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
+ brw->batch.flags |= BATCH_ENABLE_MMIO;
return __map;
}
#define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
--
2.11.0
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