To reduce churn later, move the HW context variable from brw_context to
brw_batch.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_context.c | 23 ++++--------------
src/mesa/drivers/dri/i965/brw_context.h | 2 --
src/mesa/drivers/dri/i965/brw_queryobj.c | 4 ++--
src/mesa/drivers/dri/i965/brw_reset.c | 8 +++----
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 34 +++++++++++++++++++++------
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4 ++--
10 files changed, 44 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h
b/src/mesa/drivers/dri/i965/brw_batch.h
index 6c207b8a9b..38d83bc92b 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -90,6 +90,8 @@ typedef struct brw_batch {
bool always_flush;
bool disable_throttling;
+ drm_intel_context *hw_ctx;
+
/**
* Set of brw_bo* that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index f680371f76..641a2f533e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1062,23 +1062,10 @@ brwCreateContext(gl_api api,
intel_fbo_init(brw);
- intel_batchbuffer_init(&brw->batch, screen->bufmgr, brw->has_llc);
-
- if (brw->gen >= 6) {
- /* Create a new hardware context. Using a hardware context means that
- * our GPU state will be saved/restored on context switch, allowing us
- * to assume that the GPU is in the same state we left it in.
- *
- * This is required for transform feedback buffer offsets, query objects,
- * and also allows us to reduce how much state we have to emit.
- */
- brw->hw_ctx = drm_intel_gem_context_create(brw->batch.bufmgr);
-
- if (!brw->hw_ctx) {
- fprintf(stderr, "Gen6+ requires Kernel 3.6 or later.\n");
- intelDestroyContext(driContextPriv);
- return false;
- }
+ if (!intel_batchbuffer_init(&brw->batch,
+ screen->bufmgr, brw->gen, brw->has_llc)) {
+ intelDestroyContext(driContextPriv);
+ return false;
}
if (brw_init_pipe_control(brw, devinfo)) {
@@ -1183,8 +1170,6 @@ intelDestroyContext(__DRIcontext * driContextPriv)
gen7_reset_hw_bt_pool_offsets(brw);
brw_bo_put(brw->hw_bt_pool.bo);
- drm_intel_gem_context_destroy(brw->hw_ctx);
-
if (ctx->swrast_context) {
_swsetup_DestroyContext(&brw->ctx);
_tnl_DestroyContext(&brw->ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index e602c413c2..e1141ab568 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -695,8 +695,6 @@ struct brw_context
brw_batch batch;
bool no_batch_wrap;
- drm_intel_context *hw_ctx;
-
/** BO for post-sync nonzero writes for gen6 workaround. */
brw_bo *workaround_bo;
uint8_t pipe_controls_since_last_cs_stall;
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index a55751c0d3..52a99ab918 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -422,7 +422,7 @@ brw_emit_query_begin(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
struct brw_query_object *query = brw->query.obj;
- if (brw->hw_ctx)
+ if (brw->batch.hw_ctx)
return;
/* Skip if we're not doing any queries, or we've already recorded the
@@ -449,7 +449,7 @@ brw_emit_query_end(struct brw_context *brw)
{
struct brw_query_object *query = brw->query.obj;
- if (brw->hw_ctx)
+ if (brw->batch.hw_ctx)
return;
if (!brw->query.begin_emitted)
diff --git a/src/mesa/drivers/dri/i965/brw_reset.c
b/src/mesa/drivers/dri/i965/brw_reset.c
index df734e5f0f..69b21d1cff 100644
--- a/src/mesa/drivers/dri/i965/brw_reset.c
+++ b/src/mesa/drivers/dri/i965/brw_reset.c
@@ -43,7 +43,7 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
* DRM_IOCTL_I915_GET_RESET_STATS is not supported), this function should
* not be accessible.
*/
- assert(brw->hw_ctx != NULL);
+ assert(brw->batch.hw_ctx);
/* A reset status other than NO_ERROR was returned last time. I915 returns
* nonzero active/pending only if reset has been encountered and completed.
@@ -52,8 +52,8 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
if (brw->reset_count != 0)
return GL_NO_ERROR;
- err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
- &pending);
+ err = drm_intel_get_reset_stats(brw->batch.hw_ctx,
+ &reset_count, &active, &pending);
if (err)
return GL_NO_ERROR;
@@ -85,7 +85,7 @@ brw_check_for_reset(struct brw_context *brw)
uint32_t pending;
int err;
- err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
+ err = drm_intel_get_reset_stats(brw->batch.hw_ctx, &reset_count, &active,
&pending);
if (err)
return;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 1f45da07bc..232558ade6 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -390,7 +390,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
* right away rather than doing it via state atoms. This saves a small
* amount of overhead on every draw call.
*/
- if (!brw->hw_ctx)
+ if (!brw->batch.hw_ctx)
return;
if (brw->gen == 6)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 6e12789ea5..c46eb72206 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -52,7 +52,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!mt && brw->no_depth_or_stencil) {
- assert(brw->hw_ctx);
+ assert(brw->batch.hw_ctx);
return;
}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index cfc9e7ab6e..3cd4e87fda 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -53,7 +53,7 @@ emit_depth_packets(struct brw_context *brw,
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
- assert(brw->hw_ctx);
+ assert(brw->batch.hw_ctx);
return;
}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index d62fd06a72..230d1763dc 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -39,9 +39,9 @@
static void
intel_batchbuffer_reset(struct brw_batch *batch, bool has_llc);
-void
+int
intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
- bool has_llc)
+ int gen, bool has_llc)
{
batch->bufmgr = bufmgr;
@@ -52,6 +52,24 @@ intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr
*bufmgr,
batch->map = batch->cpu_map;
batch->map_next = batch->cpu_map;
}
+
+ if (gen >= 6) {
+ /* Create a new hardware context. Using a hardware context means that
+ * our GPU state will be saved/restored on context switch, allowing us
+ * to assume that the GPU is in the same state we left it in.
+ *
+ * This is required for transform feedback buffer offsets, query objects,
+ * and also allows us to reduce how much state we have to emit.
+ */
+ batch->hw_ctx = drm_intel_gem_context_create(bufmgr);
+
+ if (!batch->hw_ctx) {
+ fprintf(stderr, "Gen6+ requires Kernel 3.6 or later.\n");
+ return false;
+ }
+ }
+
+ return true;
}
static void
@@ -107,6 +125,8 @@ intel_batchbuffer_free(struct brw_batch *batch)
brw_bo_put(batch->throttle_batch[1]);
brw_bo_put(batch->throttle_batch[0]);
+
+ drm_intel_gem_context_destroy(batch->hw_ctx);
}
void
@@ -197,7 +217,7 @@ brw_new_batch(struct brw_context *brw)
* would otherwise be stored in the context (which for all intents and
* purposes means everything).
*/
- if (brw->hw_ctx == NULL)
+ if (!brw->batch.hw_ctx)
brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
brw->ctx.NewDriverState |= BRW_NEW_BATCH;
@@ -348,13 +368,13 @@ do_flush_locked(struct brw_context *brw)
if (unlikely(INTEL_DEBUG & DEBUG_AUB))
brw_annotate_aub(brw);
- if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) {
+ if (batch->hw_ctx == NULL || batch->ring != RENDER_RING) {
ret = drm_intel_bo_mrb_exec(batch->bo, 4 * USED_BATCH(*batch),
NULL, 0, 0, flags);
- } else {
- ret = drm_intel_gem_bo_context_exec(batch->bo, brw->hw_ctx,
+ } else {
+ ret = drm_intel_gem_bo_context_exec(batch->bo, batch->hw_ctx,
4 * USED_BATCH(*batch), flags);
- }
+ }
}
throttle(brw);
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index eb8be9657c..df57bcaf25 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -45,8 +45,8 @@ struct brw_context;
enum brw_gpu_ring;
void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
-void intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
- bool has_llc);
+int intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
+ int gen, bool has_llc);
void intel_batchbuffer_free(struct brw_batch *batch);
void intel_batchbuffer_save_state(struct brw_context *brw);
void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
--
2.11.0
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