[Mesa-dev] [Bug 92985] Mac OS X build error "ar: no archive members specified"

https://bugs.freedesktop.org/show_bug.cgi?id=92985 Bug ID: 92985 Summary: Mac OS X build error "ar: no archive members specified" Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Mac OS X (All)

Re: [Mesa-dev] [PATCH v2 17/42] glsl ubo/ssbo: Add lower_buffer_access class

On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote: > This class has code that will be shared by lower_ubo_reference and > lower_shared_reference. (lower_shared_reference will be used to > support compute shader shared variables.) > > v2: > * Add lower_buffer_access.h to makefile (Emil) > *

Re: [Mesa-dev] [PATCH 5/5] i965/nir: use vectorization for non-scalar stages

On Mon, Nov 16, 2015 at 11:00 AM, Jason Ekstrand wrote: > On Sat, Nov 14, 2015 at 6:59 PM, Connor Abbott wrote: >> Shader-db results on bdw with INTEL_DEBUG=vec4: >> >> total instructions in shared programs: 1634044 -> 1612936 (-1.29%) >> instructions in affected programs: 802502 -> 781394 (-2.63

Re: [Mesa-dev] [PATCH v2 15/42] glsl ubo/ssbo: Use enum to track current buffer access type

Reviewed-by: Iago Toral Quiroga On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote: > v2: > * Rename ssbo_get_array_length to ssbo_unsized_array_length_access (Iago) > * Use always use this-> when referencing buffer_access_type (Iago) > > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias

Re: [Mesa-dev] [PATCH] mesa: error out in indirect draw when vertex bindings mismatch

On 11/18/2015 01:31 AM, Fredrik Höglund wrote: On Tuesday 17 November 2015, Tapani Pälli wrote: On 11/16/2015 08:55 AM, Tapani Pälli wrote: On 11/13/2015 07:18 PM, Fredrik Höglund wrote: On Friday 13 November 2015, Tapani Pälli wrote: Patch adds additional mask for tracking which vertex buff

[Mesa-dev] [PATCH v2 34/42] glsl: Check for SSBO variable in check_for_ssbo_store

The compiler probably already blocks this earlier on, but we should be checking for an SSBO here. Signed-off-by: Jordan Justen Cc: Samuel Iglesias Gonsalvez Cc: Iago Toral Quiroga --- src/glsl/lower_ubo_reference.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/

[Mesa-dev] [PATCH v2 22/42] glsl: Don't lower_variable_index_to_cond_assign for shared variables

Signed-off-by: Jordan Justen --- src/glsl/lower_variable_index_to_cond_assign.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/glsl/lower_variable_index_to_cond_assign.cpp b/src/glsl/lower_variable_index_to_cond_assign.cpp index 1ab3afe..a1ba934 100644 --- a/src/glsl/lower_variable

[Mesa-dev] [PATCH v2 09/42] i965: Implement selection of the closest L3 configuration based on a vector of weights.

From: Francisco Jerez The input of the L3 set-up code is a vector giving the approximate desired relative size of each partition. This implements logic to compare the input vector against the table of validated configurations for the device and pick the closest compatible one. --- src/mesa/driv

[Mesa-dev] [PATCH v2 08/42] i965/hsw: Enable L3 atomics.

From: Francisco Jerez Improves performance of the arb_shader_image_load_store-atomicity piglit test by over 25x (which isn't a real benchmark it's just heavy on atomics -- the improvement in a microbenchmark I wrote a while ago seemed to be even greater). The drawback is one needs to be extra-ca

[Mesa-dev] [PATCH v2 14/42] i965: Hook up L3 partitioning state atom.

From: Francisco Jerez --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- src/mesa/drivers/dri/i965/brw_state_upload.c | 4 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index cc011f7.

[Mesa-dev] [PATCH v2 29/42] i965: Enable shared local memory for CS shared variables

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_cs.c| 2 ++ src/mesa/drivers/dri/i965/brw_defines.h | 2 ++ src/mesa/drivers/dri/i965/gen7_cs_state.c | 12 3 files changed, 16 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/driver

[Mesa-dev] [PATCH v2 24/42] nir: Translate glsl shared var load intrinsic to nir intrinsic

Signed-off-by: Jordan Justen --- src/glsl/nir/glsl_to_nir.cpp | 29 + src/glsl/nir/nir_intrinsics.h | 1 + 2 files changed, 30 insertions(+) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 6d24341..a59d09c 100644 --- a/src/glsl/nir/gls

[Mesa-dev] [PATCH v2 19/42] glsl ubo/ssbo: Move common code into lower_buffer_access::setup_buffer_access

This code will also be usable by the pass to lower shared variables. Note, that *const_offset is adjusted by setup_buffer_access so it must be initialized before calling setup_buffer_access. v2: * Add comment for lower_buffer_access::setup_buffer_access Signed-off-by: Jordan Justen Cc: Samuel

[Mesa-dev] [PATCH v2 41/42] docs: Mark ARB_compute_shader as done for i965

Signed-off-by: Jordan Justen --- docs/GL3.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index b768eea..cb4415f 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -152,7 +152,7 @@ GL 4.3, GLSL 4.30: GL_ARB_arrays_of_arrays

[Mesa-dev] [PATCH v2 27/42] i965/fs: Handle nir shared variable load intrinsic

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_defines.h | 2 ++ src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33 2 files changed, 35 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h ind

[Mesa-dev] [PATCH v2 26/42] i965: Disable vector splitting on shared variables

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp index cab5af3..2c7e0dc 100644 --- a/src/mesa/dr

[Mesa-dev] [PATCH v2 37/42] glsl: Disable several optimizations on shared variables

Shared variables can be accessed by other threads within the same local workgroup. This prevents us from performing certain optimizations with shared variables. Signed-off-by: Jordan Justen --- src/glsl/opt_constant_propagation.cpp | 3 ++- src/glsl/opt_constant_variable.cpp| 3 ++- src/glsl

[Mesa-dev] [PATCH v2 12/42] i965: Add debug flag to print out the new L3 state during transitions.

From: Francisco Jerez --- src/mesa/drivers/dri/i965/gen7_l3_state.c | 17 + src/mesa/drivers/dri/i965/intel_debug.c | 1 + src/mesa/drivers/dri/i965/intel_debug.h | 1 + 3 files changed, 19 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/dr

[Mesa-dev] [PATCH v2 28/42] i965/fs: Handle nir shared variable store intrinsic function

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 54 1 file changed, 54 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index e9336fd..c8c6370 100644 --- a/src/mesa/drivers

[Mesa-dev] [PATCH v2 11/42] i965: Implement L3 state atom.

From: Francisco Jerez The L3 state atom calculates the target L3 partition weights when the program bound to some shader stage is modified, and in case they are far enough from the current partitioning it makes sure that the L3 state is re-emitted. --- src/mesa/drivers/dri/i965/brw_context.h |

[Mesa-dev] [PATCH v2 21/42] glsl: Add default matrix ordering in lower_buffer_access

For compute shader shared variable we will set a default of column major. Signed-off-by: Jordan Justen --- src/glsl/lower_buffer_access.cpp | 5 +++-- src/glsl/lower_buffer_access.h | 10 ++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/glsl/lower_buffer_access.c

[Mesa-dev] [PATCH v2 10/42] i965: Calculate appropriate L3 partition weights for the current pipeline state.

From: Francisco Jerez This calculates a rather conservative partitioning of the L3 cache based on the shaders currently bound to the pipeline and whether they use SLM, atomics, images or scratch space. The result is intended to be fine-tuned later on based on other pipeline state. --- src/mesa/

[Mesa-dev] [PATCH v2 35/42] glsl: Translate atomic intrinsic functions on shared variables

When an intrinsic atomic operation is used on a shared variable, we translate it to a new 'share variable' specific intrinsic function call. For example, add call to __intrinsic_atomic_add when used on a shared variable will be translated to a call to __intrinsic_atomic_add_shared. Signed-off-by:

[Mesa-dev] [PATCH v2 31/42] glsl: Allow atomic functions to be used with shared variables

Signed-off-by: Jordan Justen Reviewed-by: Timothy Arceri --- src/glsl/ast_function.cpp | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp index 466ece6..da1167a 100644 --- a/src/glsl/ast_function.cpp +++ b

[Mesa-dev] [PATCH v2 02/42] i965: Keep track of whether LRI is allowed in the context struct.

From: Francisco Jerez This stores the result of can_do_pipelined_register_writes() in the context struct so we can find out later whether LRI can be used to program the L3 configuration. v2: * Split change of gen check in can_do_pipelined_register_writes (jljusten) Reviewed-by: Jordan Justen

[Mesa-dev] [PATCH v2 04/42] i965: Define state flag to signal that the URB size has been altered.

From: Francisco Jerez This will make sure that we recalculate the URB layout anytime the URB size is modified by the L3 partitioning code. Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_state_upload.c | 1 + src/mesa/drivers/dr

[Mesa-dev] [PATCH v2 32/42] glsl: Replace atomic_ssbo and ssbo_atomic with atomic

The atomic functions can also be used with shared variables in compute shaders. When lowering the intrinsic in lower_ubo_reference, we still create an SSBO specific intrinsic since SSBO accesses can be indirectly addressed, whereas all compute shader shared variable live in a single shared variabl

[Mesa-dev] [PATCH v2 25/42] nir: Translate glsl shared var store intrinsic to nir intrinsic

Signed-off-by: Jordan Justen --- src/glsl/nir/glsl_to_nir.cpp | 33 + src/glsl/nir/nir_intrinsics.h | 3 ++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index a59d09c..a832570 100644 -

[Mesa-dev] [PATCH v2 40/42] i965: Enable ARB_compute_shader extension on supported hardware

Enable ARB_compute_shader on gen7+, on hardware that supports the OpenGL 4.3 requirements of a local group size of 1024. With SIMD16 support, this is limited to Ivy Bridge and Haswell. Broadwell will work with a local group size up to 896 on SIMD16 meaning programs that use this size or lower sho

[Mesa-dev] [PATCH v2 15/42] glsl ubo/ssbo: Use enum to track current buffer access type

v2: * Rename ssbo_get_array_length to ssbo_unsized_array_length_access (Iago) * Use always use this-> when referencing buffer_access_type (Iago) Signed-off-by: Jordan Justen Cc: Samuel Iglesias Gonsalvez Cc: Iago Toral Quiroga --- src/glsl/lower_ubo_reference.cpp | 26 +--

[Mesa-dev] [PATCH v2 03/42] i965: Adjust gen check in can_do_pipelined_register_writes

From: Francisco Jerez Allow for pipelined register writes for gen < 7. v2: * Split from another patch and adjust comment (jljusten) Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/intel_extensions.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/

[Mesa-dev] [PATCH v2 36/42] glsl: Buffer atomics are supported for compute shaders

Signed-off-by: Jordan Justen --- src/glsl/builtin_functions.cpp | 70 +++--- 1 file changed, 38 insertions(+), 32 deletions(-) diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp index 3e767e8..bd4c5a3 100644 --- a/src/glsl/builtin_fun

[Mesa-dev] [PATCH v2 18/42] glsl ubo/ssbo: Move is_dereferenced_thing_row_major into lower_buffer_access

Signed-off-by: Jordan Justen Cc: Samuel Iglesias Gonsalvez Cc: Iago Toral Quiroga Reviewed-by: Iago Toral Quiroga --- src/glsl/lower_buffer_access.cpp | 90 src/glsl/lower_buffer_access.h | 2 + src/glsl/lower_ubo_reference.cpp | 90 -

[Mesa-dev] [PATCH v2 23/42] glsl: Add lowering pass for shared variable references

In this lowering pass, shared variables are decomposed into intrinsic calls. v2: * Send mem_ctx as a parameter (Iago) Signed-off-by: Jordan Justen --- src/glsl/Makefile.sources | 1 + src/glsl/ir_optimization.h | 1 + src/glsl/linker.cpp | 4 + src/glsl

[Mesa-dev] [PATCH v2 13/42] i965: Work around L3 state leaks during context switches.

From: Francisco Jerez This is going to require some rather intrusive kernel changes to fix properly, in the meantime (and forever on at least pre-v4.1 kernels) we'll have to restore the hardware defaults at the end of every batch in which the L3 configuration was changed to avoid interfering with

[Mesa-dev] [PATCH v2 16/42] glsl ubo/ssbo: Split buffer access to insert_buffer_access

This allows the code in emit_access to be generic enough to also be for lowering shared variables. Signed-off-by: Jordan Justen Cc: Samuel Iglesias Gonsalvez Cc: Iago Toral Quiroga Reviewed-by: Iago Toral Quiroga --- src/glsl/lower_ubo_reference.cpp | 78 ++

[Mesa-dev] [PATCH v2 05/42] i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.

From: Francisco Jerez According to the hardware docs a DC flush is sufficient to make CS_STALL happy, there's no need to add STALL_AT_SCOREBOARD whenever it's present. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 4 +++- 1 file changed, 3 insertions(+), 1 del

[Mesa-dev] [PATCH v2 39/42] i965/nir: Implement shared variable atomic operations

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs.h | 2 ++ src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 60 2 files changed, 62 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index cbfc07f

[Mesa-dev] [PATCH v2 17/42] glsl ubo/ssbo: Add lower_buffer_access class

This class has code that will be shared by lower_ubo_reference and lower_shared_reference. (lower_shared_reference will be used to support compute shader shared variables.) v2: * Add lower_buffer_access.h to makefile (Emil) * Remove static is_dereferenced_thing_row_major from lower_buffer_acc

[Mesa-dev] [PATCH v2 07/42] i965: Implement programming of the L3 configuration.

From: Francisco Jerez --- src/mesa/drivers/dri/i965/gen7_l3_state.c | 95 +++ 1 file changed, 95 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 8f9ba5b..48bca29 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [PATCH v2 42/42] docs: Add ARB_compute_shader to 11.1.0 release notes

Signed-off-by: Jordan Justen --- docs/relnotes/11.1.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html index 6654311..c89b822 100644 --- a/docs/relnotes/11.1.0.html +++ b/docs/relnotes/11.1.0.html @@ -47,6 +47,7 @@ Note: some of the ne

[Mesa-dev] [PATCH v2 20/42] glsl: Remove mem_ctx as member variable in lower_ubo_reference_visitor

Signed-off-by: Jordan Justen Cc: Iago Toral Quiroga --- src/glsl/lower_ubo_reference.cpp | 64 +--- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp index 5082da8..2808ac1 10064

[Mesa-dev] [PATCH v2 01/42] i965: Define symbolic constants for some useful L3 cache control registers.

From: Francisco Jerez Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/intel_reg.h | 53 +++ 1 file changed, 53 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index a261c2b..0b167d5 100644 --- a/

[Mesa-dev] [PATCH v2 33/42] glsl: Check for SSBO variable in SSBO atomic lowering

When an atomic function is called, we need to check to see if it is for an SSBO variable before lowering it to the SSBO specific intrinsic function. v2: * is_in_buffer_block => is_in_shader_storage_block (Iago) Signed-off-by: Jordan Justen Cc: Samuel Iglesias Gonsalvez Cc: Iago Toral Quiroga

[Mesa-dev] [PATCH v2 38/42] nir: Add nir intrinsics for shared variable atomic operations

Signed-off-by: Jordan Justen --- src/glsl/nir/glsl_to_nir.cpp | 53 +++ src/glsl/nir/nir_intrinsics.h | 25 2 files changed, 78 insertions(+) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 83724d3..a7ee

[Mesa-dev] [PATCH v2 00/42] Computer shader shared variables

git://people.freedesktop.org/~jljusten/mesa cs-shared-variables-v2 http://patchwork.freedesktop.org/bundle/jljusten/cs-shared-variables-v2 11 of the 42 patches have a Reviewed-by Patches 1 - 14: * curro's "i965: L3 cache partitioning." (sent Sept 6) I split one patch and changed a comment.

[Mesa-dev] [PATCH v2 30/42] i965: Lower shared variable references to intrinsic calls

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_shader.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index c4a567f..1365609 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/

[Mesa-dev] [PATCH v2 06/42] i965: Import tables enumerating the set of validated L3 configurations.

From: Francisco Jerez It should be possible to use additional L3 configurations other than the ones listed in the tables of validated allocations ("BSpec » 3D-Media-GPGPU Engine » L3 Cache and URB [IVB+] » L3 Cache and URB [*] » L3 Allocation and Programming"), but it seems sensible for now to ha

Re: [Mesa-dev] [PATCH 1/5] util/set: don't compare against deleted entries

On Mon, Nov 16, 2015 at 6:56 PM, Timothy Arceri wrote: > On Sat, 2015-11-14 at 21:59 -0500, Connor Abbott wrote: >> Not sure how this wasn't already caught by valgrind, but it fixes an >> issue with the vectorizer. > > Can you give a more detailed description of the problem that is fixed? I'm > as

Re: [Mesa-dev] [PATCH 0/7] DRI3 support for EGL (v4)

2015-11-18 8:04 GMT+08:00 Martin Peres : > > > On 18/11/15 01:37, Mike Lothian wrote: >> >> >> Hi >> >> Out of interest have any of you tested this on Plasma5? When I set OpenGL >> & EGL in kwin and I'm using DRI3 compositing is disabled (it wasn't before) >> >> This is on Kabini using the latest m

Re: [Mesa-dev] [PATCH] i965: Add assertion for src_stencil payload size

On Monday, November 16, 2015 06:20:57 PM Ben Widawsky wrote: > This helps address a coverity warning and prevents future questions about this > code. > > Reported-by: Coverity (via Ilia) > Cc: Matt Turner > Cc: Ilia Mirkin > Signed-off-by: Ben Widawsky > --- > src/mesa/drivers/dri/i965/brw_fs.

[Mesa-dev] [PATCH] [v3] i965/skl: skip fast clears for certain surface formats

Some of the information originally in this commit message is now in the patch before this. SKL adds compressible render targets and as a result mutates some of the programming for fast clears and resolves. There is a new internal surface type called the CCS. The old AUX_MCS bit becomes AUX_CCS_D.

[Mesa-dev] [PATCH 7/7] [v2] i965/gen9: Support fast clears for 32b float

SKL supports the ability to do fast clears and resolves of 32b RGBA as both integer and floats. This patch only enables float color clears because we haven't yet enabled integer color clears, (HW support for that was added in BDW). Two formats are explicitly disabled because they fail piglit tests

[Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

Background: Prior to Skylake and since Ivybridge Intel hardware has had the ability to use a MCS (Multisample Control Surface) as auxiliary data in "compression" operations on the surface. This reduces memory bandwidth. This hardware was either used for MSAA compression, and fast clear operations.

Re: [Mesa-dev] [PATCH 05/36] i965: Import tables enumerating the set of validated L3 configurations.

On Sat, Nov 14, 2015 at 01:43:41PM -0800, Jordan Justen wrote: > From: Francisco Jerez > > It should be possible to use additional L3 configurations other than > the ones listed in the tables of validated allocations ("BSpec » > 3D-Media-GPGPU Engine » L3 Cache and URB [IVB+] » L3 Cache and URB [

Re: [Mesa-dev] [PATCH 0/7] DRI3 support for EGL (v4)

On 18/11/15 01:37, Mike Lothian wrote: Hi Out of interest have any of you tested this on Plasma5? When I set OpenGL & EGL in kwin and I'm using DRI3 compositing is disabled (it wasn't before) This is on Kabini using the latest mesa, xorg and radeon drivers from got Cheers Mike Hey Mik

Re: [Mesa-dev] [PATCH] nir: Store the size of the TCS output patch in nir_shader_info.

Seems reasonable, Reviewed-by: Jason Ekstrand On Tue, Nov 17, 2015 at 3:16 PM, Kenneth Graunke wrote: > Signed-off-by: Kenneth Graunke > --- > src/glsl/nir/glsl_to_nir.cpp | 4 > src/glsl/nir/nir.h | 5 + > 2 files changed, 9 insertions(+) > > diff --git a/src/glsl/nir/glsl

Re: [Mesa-dev] [PATCH 0/7] DRI3 support for EGL (v4)

Hi Out of interest have any of you tested this on Plasma5? When I set OpenGL & EGL in kwin and I'm using DRI3 compositing is disabled (it wasn't before) This is on Kabini using the latest mesa, xorg and radeon drivers from got Cheers Mike On Tue, 17 Nov 2015, 3:31 p.m. Martin Peres wrote: >

Re: [Mesa-dev] [PATCH] mesa: error out in indirect draw when vertex bindings mismatch

On Tuesday 17 November 2015, Tapani Pälli wrote: > > On 11/16/2015 08:55 AM, Tapani Pälli wrote: > > > > > > On 11/13/2015 07:18 PM, Fredrik Höglund wrote: > >> On Friday 13 November 2015, Tapani Pälli wrote: > >>> Patch adds additional mask for tracking which vertex buffer bindings > >>> are set.

[Mesa-dev] [PATCH] nir: Store the size of the TCS output patch in nir_shader_info.

Signed-off-by: Kenneth Graunke --- src/glsl/nir/glsl_to_nir.cpp | 4 src/glsl/nir/nir.h | 5 + 2 files changed, 9 insertions(+) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 6d24341..c4b53f3 100644 --- a/src/glsl/nir/glsl_to_nir.cpp +++ b/src/g

Re: [Mesa-dev] [PATCH 2/2] intel/kbl: Add Kabylake PCI ids

I don't know what the accepted solution is, but generally libdrm patches should go to dri-de...@lists.freedesktop.org. Since not everyone reads dri-devel regularly I usually send to both lists. I don't know if it matters much anymore. On Mon, Nov 16, 2015 at 04:25:12PM -0800, Sarah Sharp wrote: >

[Mesa-dev] [Bug 92983] [vmwgfx] SIGABRT vmw_screen_ioctl.c:461

https://bugs.freedesktop.org/show_bug.cgi?id=92983 Bug ID: 92983 Summary: [vmwgfx] SIGABRT vmw_screen_ioctl.c:461 Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Key

Re: [Mesa-dev] [PATCH v2 1/2] mesa: Add KBL PCI IDs and platform information.

On Tue, Nov 17, 2015 at 11:40:53AM -0800, Sarah Sharp wrote: > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken > directly from the Linux kernel patches, which are under review: > > http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html > http://cgit.freedesktop.o

Re: [Mesa-dev] [PATCH v2] i965: Implement ARB_pipeline_statistics_query tessellation counters.

On Tue, Nov 17, 2015 at 11:28:25AM -0800, Kristian Høgsberg wrote: > On Tue, Nov 17, 2015 at 11:25 AM, Kenneth Graunke > wrote: > > We basically just need to uncomment Ben's code. > > Reviewed-by: Kristian Høgsberg > Reviewed-by: Ben Widawsky ___

Re: [Mesa-dev] [PATCH] mesa/uniform_query: use IROUND for doubles as well as floats

On Tue, Nov 17, 2015 at 4:00 PM, Dave Airlie wrote: > From: Dave Airlie > > For the case where we convert a double to an int, we should > round the same as we do for floats. > > This fixes GL41-CTS.gpu_shader_fp64.state_query > > Signed-off-by: Dave Airlie > --- > src/mesa/main/uniform_query.cp

[Mesa-dev] [PATCH] mesa/uniform_query: use IROUND for doubles as well as floats

From: Dave Airlie For the case where we convert a double to an int, we should round the same as we do for floats. This fixes GL41-CTS.gpu_shader_fp64.state_query Signed-off-by: Dave Airlie --- src/mesa/main/uniform_query.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/

[Mesa-dev] [PATCH v3] llvmpipe: disable VSX in ppc due to LLVM PPC bug

This patch disables the use of VSX instructions, as they cause some piglit tests to fail For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7 With this patch, ppc64le reaches parity with x86-64 as far as piglit test suite is concerned. v2: - Added check that we have at least LLV

Re: [Mesa-dev] [Mesa-stable] [PATCH v2] llvmpipe: disable vsx in ppc due to LLVM PPC bug

Am 17.11.2015 um 21:27 schrieb Oded Gabbay: > On Tue, Nov 17, 2015 at 9:40 PM, Jan Vesely wrote: >> >> >> On Tue, Nov 17, 2015 at 12:37 PM, Oded Gabbay wrote: >>> >>> On Tue, Nov 17, 2015 at 6:15 PM, Emil Velikov >>> wrote: On 17 November 2015 at 16:02, Oded Gabbay wrote: > This patch

Re: [Mesa-dev] [Mesa-stable] [PATCH v2] llvmpipe: disable vsx in ppc due to LLVM PPC bug

On Tue, Nov 17, 2015 at 9:40 PM, Jan Vesely wrote: > > > On Tue, Nov 17, 2015 at 12:37 PM, Oded Gabbay wrote: >> >> On Tue, Nov 17, 2015 at 6:15 PM, Emil Velikov >> wrote: >> > On 17 November 2015 at 16:02, Oded Gabbay wrote: >> >> This patch makes sure that if we use altivec (VMX) instructions

Re: [Mesa-dev] [PATCH v3 12/14] glsl: add support for complie-time constant expressions

On Tue, 2015-11-17 at 19:02 +, Emil Velikov wrote: > On 14 November 2015 at 13:42, Timothy Arceri wrote: > > From: Timothy Arceri > > > > This patch replaces the old interger constant qualifiers with either > > the new ast_layout_expression type if the qualifier requires merging > > or ast_e

[Mesa-dev] [PATCH v2 1/2] mesa: Add KBL PCI IDs and platform information.

Add PCI IDs for the Intel Kabylake platforms. The IDs are taken directly from the Linux kernel patches, which are under review: http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2 The Kabylake PCI IDs take

Re: [Mesa-dev] [Mesa-stable] [PATCH v2] llvmpipe: disable vsx in ppc due to LLVM PPC bug

On Tue, Nov 17, 2015 at 12:37 PM, Oded Gabbay wrote: > On Tue, Nov 17, 2015 at 6:15 PM, Emil Velikov > wrote: > > On 17 November 2015 at 16:02, Oded Gabbay wrote: > >> This patch makes sure that if we use altivec (VMX) instructions, we > don't > >> use VSX instructions as well, as this cause pi

Re: [Mesa-dev] [PATCH v2] i965: Implement ARB_pipeline_statistics_query tessellation counters.

On Tue, Nov 17, 2015 at 11:25 AM, Kenneth Graunke wrote: > We basically just need to uncomment Ben's code. Reviewed-by: Kristian Høgsberg > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/gen6_queryobj.c | 16 > 1 file changed, 8 insertions(+), 8 deletions(-)

Re: [Mesa-dev] [PATCH] i965: Create new files for HS/DS/TE state upload code.

On Tue, Nov 17, 2015 at 11:20 AM, Kenneth Graunke wrote: > For now, this just splits the existing code to disable these stages into > separate atoms/files. We can then replace it with real code. Nice, bye bye gen7/8_disable.c. This commit is a milestone. Reviewed-by: Kristian Høgsberg > Signe

[Mesa-dev] [PATCH v2] i965: Implement ARB_pipeline_statistics_query tessellation counters.

We basically just need to uncomment Ben's code. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/gen6_queryobj.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) Still totally untested, but now less blatantly broken... diff --git a/src/mesa/drivers/dri/i965/ge

Re: [Mesa-dev] [PATCH] i965: Add enums for 3DSTATE_TE field values.

On Tue, Nov 17, 2015 at 11:16 AM, Kenneth Graunke wrote: > 3DSTATE_TE has partitioning, output topology, and domain fields, > each of which has several enumerated values. We'll also need to > switch on the domain, so enums (rather than #defines) seem like a > natural fit. > > I chose to put these

[Mesa-dev] [PATCH] i965: Create new files for HS/DS/TE state upload code.

For now, this just splits the existing code to disable these stages into separate atoms/files. We can then replace it with real code. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources | 6 +- src/mesa/drivers/dri/i965/brw_state.h| 6 +- src/mesa/drivers/d

[Mesa-dev] [PATCH] i965: Add enums for 3DSTATE_TE field values.

3DSTATE_TE has partitioning, output topology, and domain fields, each of which has several enumerated values. We'll also need to switch on the domain, so enums (rather than #defines) seem like a natural fit. I chose to put these in brw_compiler.h because they'll be stored in struct brw_tes_prog_d

Re: [Mesa-dev] [PATCH 07/11] i965: Move postprocess_nir to codegen time

On 17 November 2015 at 15:12, Jason Ekstrand wrote: > On Tue, Nov 17, 2015 at 7:09 AM, Jason Ekstrand wrote: >> On Tue, Nov 17, 2015 at 4:04 AM, Emil Velikov >> wrote: >>> Hi Jason, >>> >>> On 12 November 2015 at 01:26, Jason Ekstrand wrote: --- src/mesa/drivers/dri/i965/brw_fs.cpp

Re: [Mesa-dev] ARB_enhanced_layout compile-time-constants V3

Hi Tim, On 14 November 2015 at 13:42, Timothy Arceri wrote: > This series adds support for compile time constants and also adds > subroutine index qualifier support which was missing for > ARB_explicit_uniform_location. > > This series applies on top of a clean-up series[3] > > V3: > - Some refa

Re: [Mesa-dev] [PATCH v3 12/14] glsl: add support for complie-time constant expressions

On 14 November 2015 at 13:42, Timothy Arceri wrote: > From: Timothy Arceri > > This patch replaces the old interger constant qualifiers with either > the new ast_layout_expression type if the qualifier requires merging > or ast_expression if the qualifier can't have mulitple declarations > or if

Re: [Mesa-dev] [Mesa-stable] [PATCH v2] llvmpipe: disable vsx in ppc due to LLVM PPC bug

On Tue, Nov 17, 2015 at 6:15 PM, Emil Velikov wrote: > On 17 November 2015 at 16:02, Oded Gabbay wrote: >> This patch makes sure that if we use altivec (VMX) instructions, we don't >> use VSX instructions as well, as this cause piglit tests to fail >> >> For more details, see: https://llvm.org/bu

Re: [Mesa-dev] [PATCH v3 06/14] glsl: move stream layout qualifier validation

On 14 November 2015 at 13:42, Timothy Arceri wrote: > From: Timothy Arceri > > We are moving this out of the parser in preparation for compile > time constant support. > > The reason a validation function is used rather than an apply > function like what is used with bindings is because glsl allo

Re: [Mesa-dev] [PATCH v3 04/14] glsl: remove duplicate validation for index layout qualifier

On 14 November 2015 at 13:42, Timothy Arceri wrote: > From: Timothy Arceri > > The minimum value for index is validated in the ast code and Nitpick: One might want to say "apply_explicit_location" instead of "int the ast code". Not a big deal though. -Emil ___

[Mesa-dev] [PATCH] xmlconfig: Add support for DragonFly

Hi, Emil has recently convinced me to send DragonFly support patches present in our ports tree, so here's the first one. -- Francois Tigeot >From c4a53d4ea3568f0eb727f3be8d5597371f15339d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Tigeot?= Date: Tue, 17 Nov 2015 18:54:01 +0100 Su

Re: [Mesa-dev] ast clean-up and fixes

On 13 November 2015 at 01:13, Timothy Arceri wrote: > This is a bunch of clean ups and some small fixes I noticed while > getting ready to add arb_enhanced_layouts support. > > No regressions after runnning on Intels CI system. > For the series: (1 v2) Reviewed-by: Emil Velikov Not the best per

Re: [Mesa-dev] [PATCH 3/8] glsl: rename function that processes struct and iface members

On 13 November 2015 at 01:13, Timothy Arceri wrote: > From: Timothy Arceri > Perhaps a small message - "As of last commit this function handles only the struct/iface members." or alike. Not a big deal either way: Reviewed-by: Emil Velikov -Emil ___ m

Re: [Mesa-dev] [PATCH 2/8] glsl: move block validation outside function that validates members

On 13 November 2015 at 01:13, Timothy Arceri wrote: > From: Timothy Arceri > > --- > src/glsl/ast_to_hir.cpp | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp > index f4c53b4..60f415d 100644 > --- a/src/gls

Re: [Mesa-dev] [PATCH 1/2] mesa: Add KBL PCI IDs and platform information.

On Mon, Nov 16, 2015 at 04:40:20PM -0800, Matt Turner wrote: > On Mon, Nov 16, 2015 at 4:24 PM, Sarah Sharp > wrote: > > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken > > directly from the Linux kernel patches, which are under review: > > > > http://lists.freedesktop.org/archive

Re: [Mesa-dev] [PATCH v2] i965: Prevent fast clears for MSRTs on SKL

Chad Versace writes: > Neil, do you have a bug open for this? What kind of bug do you mean? I don't think it would make sense to open a Freedesktop bug because it doesn't cause any problems as fast clears aren't enabled at all yet for SKL. > Reviewed-by: Chad Versace Thanks for the review. R

Re: [Mesa-dev] [Mesa-stable] [PATCH v2] llvmpipe: disable vsx in ppc due to LLVM PPC bug

On 17 November 2015 at 16:02, Oded Gabbay wrote: > This patch makes sure that if we use altivec (VMX) instructions, we don't > use VSX instructions as well, as this cause piglit tests to fail > > For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7 > > With this patch, ppc64le rea

[Mesa-dev] [PATCH v2] llvmpipe: disable vsx in ppc due to LLVM PPC bug

This patch makes sure that if we use altivec (VMX) instructions, we don't use VSX instructions as well, as this cause piglit tests to fail For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7 With this patch, ppc64le reaches parity with x86-64 as far as piglit test suite is conce

Re: [Mesa-dev] [PATCH] llvmpipe: disable vsx in ppc due to LLVM PPC bug

On 17/11/15 15:15, Oded Gabbay wrote: On Tue, Nov 17, 2015 at 4:42 PM, Roland Scheidegger wrote: Am 17.11.2015 um 15:19 schrieb Oded Gabbay: This patch makes sure that if we use altivec (VMX) instructions, we don't use VSX instructions as well, as this cause piglit tests to fail For more deta

Re: [Mesa-dev] [PATCH 0/7] DRI3 support for EGL (v4)

On 10/11/15 20:26, Axel Davy wrote: Hi, I did take a look, and it looks good to me. I'm happy you implemented DRI_PRIME support as well. About it, do you need testers to check everything works ? A mistake about it I noticed is that you don't disable EGL_KHR_image_pixmap when is_different_gp

Re: [Mesa-dev] [PATCH] llvmpipe: disable vsx in ppc due to LLVM PPC bug

On Tue, Nov 17, 2015 at 4:42 PM, Roland Scheidegger wrote: > Am 17.11.2015 um 15:19 schrieb Oded Gabbay: >> This patch makes sure that if we use altivec (VMX) instructions, we don't >> use VSX instructions as well, as this cause piglit tests to fail >> >> For more details, see: https://llvm.org/bu

Re: [Mesa-dev] [PATCH 07/11] i965: Move postprocess_nir to codegen time

On Tue, Nov 17, 2015 at 7:09 AM, Jason Ekstrand wrote: > On Tue, Nov 17, 2015 at 4:04 AM, Emil Velikov > wrote: >> Hi Jason, >> >> On 12 November 2015 at 01:26, Jason Ekstrand wrote: >>> --- >>> src/mesa/drivers/dri/i965/brw_fs.cpp | 11 +-- >>> src/mesa/drivers/dri/i965/b

[Mesa-dev] [Bug 92980] Push access to mesa request

https://bugs.freedesktop.org/show_bug.cgi?id=92980 Brian Paul changed: What|Removed |Added Component|Other |Account Modification |

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On Mon, Nov 16, 2015 at 11:44 AM, Ilia Mirkin wrote: > On Mon, Nov 16, 2015 at 11:42 AM, Samuel Iglesias Gonsálvez > wrote: >> >> >> On 16/11/15 17:34, Ilia Mirkin wrote: >>> On Mon, Nov 16, 2015 at 11:29 AM, Samuel Iglesias Gonsálvez >>> wrote: On 16/11/15 13:07, Tapani Pälli wro

Re: [Mesa-dev] [PATCH 07/11] i965: Move postprocess_nir to codegen time

On Tue, Nov 17, 2015 at 4:04 AM, Emil Velikov wrote: > Hi Jason, > > On 12 November 2015 at 01:26, Jason Ekstrand wrote: >> --- >> src/mesa/drivers/dri/i965/brw_fs.cpp | 11 +-- >> src/mesa/drivers/dri/i965/brw_nir.c | 1 - >> src/mesa/drivers/dri/i965/brw_vec

Re: [Mesa-dev] [PATCH] llvmpipe: disable vsx in ppc due to LLVM PPC bug

Am 17.11.2015 um 15:19 schrieb Oded Gabbay: > This patch makes sure that if we use altivec (VMX) instructions, we don't > use VSX instructions as well, as this cause piglit tests to fail > > For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7 > > With this patch, ppc64le reaches

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