On Mon, Nov 16, 2015 at 04:40:20PM -0800, Matt Turner wrote: > On Mon, Nov 16, 2015 at 4:24 PM, Sarah Sharp > <sarah.a.sh...@linux.intel.com> wrote: > > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken > > directly from the Linux kernel patches, which are under review: > > > > http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html > > http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2 > > > > Please note that if this patch is backported, the following fixes will > > need to be added before this patch: > > > > commit 28ed1e08e8ba98e "i965/skl: Remove early platform support" > > commit c1e38ad37042b0e "i965/skl: Use larger URB size where available." > > > > Thanks to Ben for fixing a bug around setting urb.size, and being > > patient with my questions about what the various fields mean. > > > > Signed-off-by: Sarah Sharp <sarah.a.sh...@linux.intel.com> > > Suggested-by: Ben Widawsky <benjamin.widaw...@intel.com> > > Tested-by: Rodrigo Vivi <rodrigo.v...@intel.com> (KBL-GT2) > > --- > > > > include/pci_ids/i965_pci_ids.h | 22 +++++++++++ > > src/mesa/drivers/dri/i965/brw_device_info.c | 60 > > +++++++++++++++++++++++++++++ > > 2 files changed, 82 insertions(+) > > > > diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h > > index 8a42599..ea3cc08 100644 > > --- a/include/pci_ids/i965_pci_ids.h > > +++ b/include/pci_ids/i965_pci_ids.h > > @@ -124,6 +124,28 @@ CHIPSET(0x1921, skl_gt2, "Intel(R) Skylake ULT GT2F") > > CHIPSET(0x1926, skl_gt3, "Intel(R) Skylake ULT GT3") > > CHIPSET(0x192A, skl_gt3, "Intel(R) Skylake SRV GT3") > > CHIPSET(0x192B, skl_gt3, "Intel(R) Skylake Halo GT3") > > +CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5") > > +CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5") > > +CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5") > > +CHIPSET(0x5906, kbl_gt1, "Intel(R) Kabylake GT1") > > +CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1") > > +CHIPSET(0x5902, kbl_gt1, "Intel(R) Kabylake GT1") > > +CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1") > > +CHIPSET(0x590A, kbl_gt1, "Intel(R) Kabylake GT1") > > +CHIPSET(0x5916, kbl_gt2, "Intel(R) Kabylake GT2") > > +CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F") > > +CHIPSET(0x591E, kbl_gt2, "Intel(R) Kabylake GT2") > > +CHIPSET(0x5912, kbl_gt2, "Intel(R) Kabylake GT2") > > +CHIPSET(0x591B, kbl_gt2, "Intel(R) Kabylake GT2") > > +CHIPSET(0x591A, kbl_gt2, "Intel(R) Kabylake GT2") > > +CHIPSET(0x591D, kbl_gt2, "Intel(R) Kabylake GT2") > > +CHIPSET(0x5926, kbl_gt3, "Intel(R) Kabylake GT3") > > +CHIPSET(0x592B, kbl_gt3, "Intel(R) Kabylake GT3") > > +CHIPSET(0x592A, kbl_gt3, "Intel(R) Kabylake GT3") > > +CHIPSET(0x5932, kbl_gt4, "Intel(R) Kabylake GT4") > > +CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4") > > +CHIPSET(0x593A, kbl_gt4, "Intel(R) Kabylake GT4") > > +CHIPSET(0x593D, kbl_gt4, "Intel(R) Kabylake GT4") > > CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherryview)") > > CHIPSET(0x22B1, chv, "Intel(R) HD Graphics (Cherryview)") > > CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") > > This doesn't apply, because it hasn't been rebased onto commit dde33fc.
Ok, I'll rebase and resend. > I find it odd that GT1.5 comes before GT1 and that there's a GT2F in > the middle of the GT2s. Can we move GT1.5 between 1 and 2? I don't > know where GT2F should go. That was the order the kernel patch listed in them; I just used a sed script to get it into the format needed for Mesa. I'm happy to re-arrange them (and I agree the order doesn't make sense), but it was much easier to visually make sure the kernel and the mesa patch matched when they were both in the same order. Sarah Sharp _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
