Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
> If a clock node named 'usb_x1' exists and set to non-zero, then we can
> assume we want it use it.
>
> Signed-off-by: Chris Brandt
Thank you for the
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> Document the USB_X1 input and add clock-names to identify
> functional and USB_X1 clocks.
>
> Signed-off-by: Chris Brandt
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda
Best regards,
Yoshihiro Shimoda
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> When not using OTG, the PHY will need to know if it should function as
> host or peripheral by checking dr_mode in the PHY node (not the parent
> controller node).
>
> Signed-off-by: Chris Brandt
Thank you for the pat
On Tue, May 14, 2019 at 4:57 PM Chris Brandt wrote:
> Document the USB_X1 input and add clock-names to identify
> functional and USB_X1 clocks.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
> --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
> +++ b/Documenta
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> Document the optional dr_mode property
>
> Signed-off-by: Chris Brandt
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda
Best regards,
Yoshihiro Shimoda
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> Document RZ/A2 (R7S9210) SoC bindings.
>
> Signed-off-by: Chris Brandt
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda
Best regards,
Yoshihiro Shimoda
On Tue, May 14, 2019 at 4:56 PM Chris Brandt wrote:
> Add USB clock node. If present, this clock input must be 48MHz.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There'
Hi Chris,
On Tue, May 14, 2019 at 4:57 PM Chris Brandt wrote:
> The RZ/A2M EVB has a 48MHz clock attached to USB_X1.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
> --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
> +++ b/arch/arm/boot/dts/r7s9210-rz
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> Move options from 'flags' field in private structure to param structure
> where other options are already being kept.
>
> Signed-off-by: Chris Brandt
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda
Best reg
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> For some SoC, CNEN must be set for USB Device mode operation.
>
> Signed-off-by: Chris Brandt
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda
Best regards,
Yoshihiro Shimoda
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> Some SoC have a CFIFO register that is byte addressable. This means
> when the CFIFO access is set to 32-bit, you can write 8-bit values to
> addresses CFIFO+0, CFIFO+1, CFIFO+2, CFIFO+3.
>
> Signed-off-by: Chris Brandt
On Wed, May 15, 2019 at 09:38:32AM +0200, Geert Uytterhoeven wrote:
> On Tue, May 14, 2019 at 4:56 PM Chris Brandt wrote:
> > Add USB clock node. If present, this clock input must be 48MHz.
> >
> > Signed-off-by: Chris Brandt
> > Reviewed-by: Simon Horman
>
> Reviewed-by: Geert Uytterhoeven
T
Hi Chris-san,
Thank you for the patch!
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> The RZ/A2 is similar to the R-Car Gen3 with some small differences.
>
> Signed-off-by: Chris Brandt
> ---
> v3:
> * Removed check for CONFIG_GENERIC_PHY
> * rebase on top of Shimoda-san (v2)
On Wed, May 15, 2019 at 09:43:02AM +0200, Geert Uytterhoeven wrote:
> Hi Chris,
>
> On Tue, May 14, 2019 at 4:57 PM Chris Brandt wrote:
> > The RZ/A2M EVB has a 48MHz clock attached to USB_X1.
> >
> > Signed-off-by: Chris Brandt
> > Reviewed-by: Simon Horman
>
> Reviewed-by: Geert Uytterhoeven
Hi Chris-san,
> From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
>
> Add support for r7s9210 (RZ/A2M) SoC
>
> Signed-off-by: Chris Brandt
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda
Best regards,
Yoshihiro Shimoda
On Tue, May 14, 2019 at 09:55:58AM -0500, Chris Brandt wrote:
> Move options from 'flags' field in private structure to param structure
> where other options are already being kept.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Tue, May 14, 2019 at 09:55:59AM -0500, Chris Brandt wrote:
> For some SoC, CNEN must be set for USB Device mode operation.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
Hello,
can I still help with this problem? It's very important for us. Thank you.
starosta
Dne 6.5.2019 v 9:10 starost...@gmail.com napsal(a):
New test on kernel Linux version 5.1.0-050100-generic. Same problem,
system crash after a few seconds.
Full kern.log: https://paste.ee/p/EmLsw
I can do
Hi Chris-san again,
> From: Yoshihiro Shimoda, Sent: Wednesday, May 15, 2019 4:48 PM
>
> Hi Chris-san,
>
> > From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM
> >
> > Some SoC have a CFIFO register that is byte addressable. This means
> > when the CFIFO access is set to 32-bit, you can wr
On Tue, May 14, 2019 at 09:55:56AM -0500, Chris Brandt wrote:
> Document the optional dr_mode property
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Tue, May 14, 2019 at 09:55:57AM -0500, Chris Brandt wrote:
> Document RZ/A2 (R7S9210) SoC bindings.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Tue, May 14, 2019 at 09:55:54AM -0500, Chris Brandt wrote:
> Document the USB_X1 input and add clock-names to identify
> functional and USB_X1 clocks.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
Hi Chris,
On Tue, May 14, 2019 at 4:58 PM Chris Brandt wrote:
> Add EHCI and OHCI host support for RZ/A2.
>
> Signed-off-by: Chris Brandt
> --- a/arch/arm/boot/dts/r7s9210.dtsi
> +++ b/arch/arm/boot/dts/r7s9210.dtsi
> + usb2_phy0: usb-phy@e8218200 {
> + comp
On Tue, May 14, 2019 at 4:58 PM Chris Brandt wrote:
> Add support for r7s9210 (RZ/A2M) SoC
>
> Signed-off-by: Chris Brandt
> ---
> Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/renesas_usbh
On Tue, May 14, 2019 at 09:55:55AM -0500, Chris Brandt wrote:
> When not using OTG, the PHY will need to know if it should function as
> host or peripheral by checking dr_mode in the PHY node (not the parent
> controller node).
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Tue, May 14, 2019 at 09:55:53AM -0500, Chris Brandt wrote:
> The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
> If a clock node named 'usb_x1' exists and set to non-zero, then we can
> assume we want it use it.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Tue, May 14, 2019 at 4:58 PM Chris Brandt wrote:
> Add USB Device support for RZ/A2.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In per
On Tue, May 14, 2019 at 09:56:00AM -0500, Chris Brandt wrote:
> Some SoC have a CFIFO register that is byte addressable. This means
> when the CFIFO access is set to 32-bit, you can write 8-bit values to
> addresses CFIFO+0, CFIFO+1, CFIFO+2, CFIFO+3.
>
> Signed-off-by: Chris Brandt
Reviewed-by:
On Tue, May 14, 2019 at 09:56:01AM -0500, Chris Brandt wrote:
> The RZ/A2 is similar to the R-Car Gen3 with some small differences.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Tue, May 14, 2019 at 09:56:02AM -0500, Chris Brandt wrote:
> Add support for r7s9210 (RZ/A2M) SoC
>
> Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
On Wed, May 15, 2019 at 06:57:17AM +, Yoshihiro Shimoda wrote:
> Hi Simon-san,
>
> > From: Simon Horman, Sent: Monday, May 13, 2019 9:01 PM
> >
> > On Mon, May 13, 2019 at 11:40:29AM +0900, Yoshihiro Shimoda wrote:
> > > This patch adds a specific struct "usbhs_of_data" to add a new SoC
> > >
Hi Chris,
On Tue, May 14, 2019 at 4:58 PM Chris Brandt wrote:
> Enable USB Host support for both the Type-C connector on the CPU board
> and the Type-A plug on the sub board.
>
> Both boards are also capable of USB Device operation as well after the
> appropriate Device Tree modifications.
>
> Si
Hi Chris
> +static int usbhs_rza2_hardware_exit(struct platform_device *pdev)
> +{
> + struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
> +
> + if (priv->phy) {
> + phy_put(priv->phy);
> + priv->phy = NULL;
> + }
> +
> + return 0;
> +}
phy_put() will d
Hi
> @@ -110,6 +115,7 @@ struct rcar_gen3_chan {
> bool extcon_host;
> bool is_otg_channel;
> bool uses_otg_pins;
> + bool uses_usb_x1;
> };
It seems we can start to think about bit-field around here ?
Thank you for your help !!
Best regards
---
Kuninori Morimoto
Hello!
On 15.05.2019 10:35, Geert Uytterhoeven wrote:
Document the USB_X1 input and add clock-names to identify
functional and USB_X1 clocks.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+++ b/Documentation
On Tue, May 14, 2019 at 4:58 PM Chris Brandt wrote:
> Add EHCI and OHCI host support for RZ/A2.
>
> Signed-off-by: Chris Brandt
> --- a/arch/arm/boot/dts/r7s9210.dtsi
> +++ b/arch/arm/boot/dts/r7s9210.dtsi
> @@ -329,6 +329,72 @@
> + usb2_phy0: usb-phy@e8218200 {
> +
Hi Sergei,
On Wed, May 15, 2019 at 10:39 AM Sergei Shtylyov
wrote:
> On 15.05.2019 10:35, Geert Uytterhoeven wrote:
> >> Document the USB_X1 input and add clock-names to identify
> >> functional and USB_X1 clocks.
> >>
> >> Signed-off-by: Chris Brandt
> >
> > Reviewed-by: Geert Uytterhoeven
> >
On Mi, 2019-05-15 at 09:54 +0200, starost...@gmail.com wrote:
> Hello,
> can I still help with this problem? It's very important for us. Thank you.
Your first step would be t verify whether your kernel has the
fix coming in the patch Joerg mentioned.
Regards
Oliver
On Tue, 2019-05-14 at 13:12 -0500, Rob Herring wrote:
> On Tue, May 14, 2019 at 04:47:19PM +0800, Chunfeng Yun wrote:
> > It's used to support dual role switch via GPIO when use Type-B
> > receptacle, typically the USB ID pin is connected to an input
> > GPIO pin
> >
> > Signed-off-by: Chunfeng Yu
As I wrote, I made new test on kernel Linux version 5.1.0-050100-generic
amd64:
https://kernel.ubuntu.com/~kernel-ppa/mainline/v5.1/
Same problem, system crash after a few seconds. Full kern.log:
https://paste.ee/p/EmLsw
Unfortunately, I can't judge if the patch is there, but I found, that
th
On 14.05.2019 17:42, Christoph Hellwig wrote:
>> @@ -136,6 +137,10 @@ void *hcd_buffer_alloc(
>> if (size <= pool_max[i])
>> return dma_pool_alloc(hcd->pool[i], mem_flags, dma);
>> }
>> +
>> +if (hcd->driver->flags & HCD_LOCAL_MEM)
>> +return g
Hello,
On 14.05.2019 21:29, Fredrik Noring wrote:
> Thanks Robin!
>
>>> For HCs that have local memory, replace the current DMA API usage
>>> with a genalloc generic allocator to manage the mappings for these
>>> devices.
>>> This is in preparation for dropping the existing "coherent" dma
>>> mem
Dne 15.5.2019 v 11:46 Oliver Neukum napsal(a):
Most helpful. First, try to replicate this with the iommu disabled.
I am trying this with "iommu disabled" in bios, but system crash too:
https://paste.ee/p/wUgHl
Secondly, make a proper bugreport mentioning the affected kernel
version (5.1)
How
This series adds USB 3.0 support for the CAT874 platform, including a
new driver for the TI HD3SS3220 USB Type-C DRP port controller.
This patch series supports:
1) Host hotplug operation
2) Device hot plug operation
3) USB type-C data_role switch
(Tested with 2 RZ/G2E boards connected with a T
Driver for TI HD3SS3220 USB Type-C DRP port controller.
The driver currently registers the port and supports data role swapping.
Signed-off-by: Biju Das
Reviewed-by: Heikki Krogerus
---
V5-->V6
* No change
Note: This patch depend on [1]
[1]: [v5,4/6] usb: roles: add API to get usb_rol
Update the DT bindings documentation to support usb role switch
for USB Type-C connector using USB role switch class framework.
Signed-off-by: Biju Das
---
V5-->V6
* Updated description
* Added usb-role-switch-property
V4-->V5
* No Change
V3-->V4
* No Change
V2-->V3
* Added optional
The RZ/G2E cat874 board has a type-c connector connected to hd3ss3220 usb
type-c drp port controller. This patch adds dual role switch support for
the type-c connector using the usb role switch class framework.
Signed-off-by: Biju Das
---
V5-->V6
* Added graph api's to find the role supported
Add device tree binding document for TI HD3SS3220 Type-C DRP port
controller driver.
Signed-off-by: Biju Das
Reviewed-by: Rob Herring
---
V5-->V6
* No change.
V4-->V5
* No Change.
V3-->V4
* No Change.
V2-->V3
* Added Rob's Reviewed by tag.
V1-->V2
* Added connector node.
* updated th
Hello,
syzbot found the following crash on:
HEAD commit:43151d6c usb-fuzzer: main usb gadget fuzzer driver
git tree: https://github.com/google/kasan.git usb-fuzzer
console output: https://syzkaller.appspot.com/x/log.txt?x=16a000a0a0
kernel config: https://syzkaller.appspot.com/x/.
Hello,
syzbot found the following crash on:
HEAD commit:43151d6c usb-fuzzer: main usb gadget fuzzer driver
git tree: https://github.com/google/kasan.git usb-fuzzer
console output: https://syzkaller.appspot.com/x/log.txt?x=16ae9974a0
kernel config: https://syzkaller.appspot.com/x/.
From: syzbot
Date: Wed, May 15, 2019 at 2:37 PM
To: , ,
, ,
, ,
, ,
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:43151d6c usb-fuzzer: main usb gadget fuzzer driver
> git tree: https://github.com/google/kasan.git usb-fuzzer
> console output: https://syzkaller.appspo
On Wed, May 15, 2019 at 09:57:12AM +, Laurentiu Tudor wrote:
> Glad I could help. On the remoteproc_virtio.c case, I had a cursory look
> and found out that the dma_declare_coherent_memory() usage was
> introduced quite recently, by this patch:
> https://git.kernel.org/pub/scm/linux/kernel/gi
Hi Shimoda-san,
> From: Yoshihiro Shimoda
> Sent: Wednesday, May 15, 2019 3:53 AM
> > +#include "rza.h"
> > +
> > +
>
> I should have realized this on v2 patch though, this double blank lines
> should be a line. After fixed it,
OK, I will remove it and resend.
Chris
Hi Geert,
On Wed, May 15, 2019, Geert Uytterhoeven wrote:
> > + - "renesas,usbhs-r7s9210" for r7s72100 (RZ/A2) compatible device
>
> for r7s9210 ...
Thank you!
Chris
From: Laurentiu Tudor
For HCs that have local memory, replace the current DMA API usage
with a genalloc generic allocator to manage the mappings for these
devices.
This is in preparation for dropping the existing "coherent" dma
mem declaration APIs. Current implementation was relying on a short
c
From: Laurentiu Tudor
In preparation for dropping the existing "coherent" dma mem declaration
APIs, replace the current dma_declare_coherent_memory() based mechanism
with the creation of a genalloc pool that will be used in the OHCI
subsystem as replacement for the DMA APIs.
For context, see thr
From: Laurentiu Tudor
In preparation for dropping the existing "coherent" dma mem declaration
APIs, replace the current dma_declare_coherent_memory() based mechanism
with the creation of a genalloc pool that will be used in the OHCI
subsystem as replacement for the DMA APIs.
For context, see thr
From: Laurentiu Tudor
For HCs that have local memory, replace the current DMA API usage
with a genalloc generic allocator to manage the mappings for these
devices.
This is in preparation for dropping the existing "coherent" dma
mem declaration APIs. Current implementation was relying on a short
c
Hi Geert,
On Wed, May 15, 2019, Geert Uytterhoeven wrote:
> > + reg = <0xe8218200 0x10>;
>
> What about the other registers?
> On R-Car Gen3, size is 0x700.
> Same for usb2_phy1.
Ahhh, good catch.
Chris
Hi Geert,
On Wed, May 15, 2019, Geert Uytterhoeven wrote:
> > +/* USB-0 as Host */
> > +/* NOTE: Requires JP3 to be fitted */
>
> This not applies to the dr_mode property below, right?
> So perhaps it should be moved there...
>
> > +&usb2_phy0 {
> > + pinctrl-names = "default";
> > +
Dne 15.5.2019 v 15:54 Oliver Neukum napsal(a):
1. Determine whether the bug depends on the use of an IOMMU
No, bug not depends on the use of an IOMMU. System crash on both cases.
2.Send a new report to the corresponding mailing list
Which mailing list is correct?
starosta
Hi Morimoto-san,
> > + if (priv->phy) {
> > + phy_put(priv->phy);
> > + priv->phy = NULL;
> > + }
> > +
> > + return 0;
> > +}
>
> phy_put() will do nothing if priv->phy was NULL.
> We can remove if() here ?
OK. I will remove 'if'.
#I copied Shimoda-san's code from rca
Hi Chris,
On Wed, May 15, 2019 at 4:03 PM Chris Brandt wrote:
> On Wed, May 15, 2019, Geert Uytterhoeven wrote:
> > > +/* USB-0 as Host */
> > > +/* NOTE: Requires JP3 to be fitted */
> >
> > This not applies to the dr_mode property below, right?
> > So perhaps it should be moved there...
> >
> >
Hi Geert,
On Wed, May 15, 2019 1, Geert Uytterhoeven wrote:
> > > Does resistor R78 need to be mounted, too?
> >
> > By default, R78 and R79 are not populated on these boards, and both Host
> > and Function work fine without board modification, so I would say
> > populating R78 is not a requiremen
Added support for Telit LE910Cx 0x1260 and 0x1261 compositions.
Signed-off-by: Daniele Palmas
---
lsusb output for the compositions:
Bus 003 Device 004: ID 1bc7:1260 Telit Wireless Solutions
Device Descriptor:
bLength18
bDescriptorType 1
bcdUSB 2.00
Add support for r7s9210 (RZ/A2M) SoC
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v3:
* added reviewed-by
v2:
* fixed typo from copy/paste of RZ/A1 line
---
Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
1
Some SoC have a CFIFO register that is byte addressable. This means
when the CFIFO access is set to 32-bit, you can write 8-bit values to
addresses CFIFO+0, CFIFO+1, CFIFO+2, CFIFO+3.
Signed-off-by: Chris Brandt
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v3:
* added reviewed-
NOTE 1:
This series requires the follow patch from Shimoda-san.
[PATCH v2] usb: renesas_usbhs: Use specific struct instead of USBHS_TYPE_*
enums
NOTE 2:
The first 2 patches from the V3 series (add USB_X1 clock) were removed from this
V4 series because Simon already applied them.
For the m
Add USB Device support for RZ/A2.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v3:
* added reviewed-by
v2:
* changed to generic name usb@xxx
* Add space between compatible strings
---
arch/arm/boot/dts/r7s9210.dtsi | 24
1 file changed, 24 insertio
Document the USB_X1 input and add clock-names to identify
functional and USB_X1 clocks.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v4:
* 'Name' to 'Names'
* "fclk" to "fck"
* added review
The RZ/A2 is similar to the R-Car Gen3 with some small differences.
Signed-off-by: Chris Brandt
Reviewed-by: Simon Horman
---
v4:
* Removed extra blank line
* Removed 'if' from exit function
* added reviewed-by
v3:
* Removed check for CONFIG_GENERIC_PHY
* rebase on top of Shimoda-san (v2) p
When not using OTG, the PHY will need to know if it should function as
host or peripheral by checking dr_mode in the PHY node (not the parent
controller node).
Signed-off-by: Chris Brandt
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v4:
* added reviewed-by
v3:
* changed 'if' t
The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
If a clock node named 'usb_x1' exists and set to non-zero, then we can
assume we want it use it.
Signed-off-by: Chris Brandt
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v4:
* added reviewed-by
v3:
* avoid magi
For some SoC, CNEN must be set for USB Device mode operation.
Signed-off-by: Chris Brandt
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v3:
* added reviewed-by
v2:
* options are now held in param
---
drivers/usb/renesas_usbhs/common.c | 6 ++
drivers/usb/renesas_usbhs/comm
Document RZ/A2 (R7S9210) SoC bindings.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v2:
* added reviewed-by
---
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 10 ++
1 file changed, 6 insertions(+),
Add EHCI and OHCI host support for RZ/A2.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v4:
* "fclk" to "fck"
* changed phy reg size 0x10 -> 0x700
* added reviewed-by
v3:
* add usb_x1 as a clock source
* add clock-names
v2:
* changed to generic name usb@xxx
* Add space
Document the optional dr_mode property
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v2:
* added reviewed-by
---
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 3 +++
1 file changed, 3 insertions(+)
diff --g
Move options from 'flags' field in private structure to param structure
where other options are already being kept.
Signed-off-by: Chris Brandt
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
v2:
* added reviewed-by
---
drivers/usb/renesas_usbhs/common.c | 23 +++-
Enable USB Host support for both the Type-C connector on the CPU board
and the Type-A plug on the sub board.
Both boards are also capable of USB Device operation as well after the
appropriate Device Tree modifications.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v3:
* moved
Hello!
On 05/15/2019 03:09 PM, Biju Das wrote:
> Add device tree binding document for TI HD3SS3220 Type-C DRP port
> controller driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Rob Herring
> ---
> V5-->V6
> * No change.
> V4-->V5
> * No Change.
> V3-->V4
> * No Change.
> V2-->V3
> *
Hello,
syzbot found the following crash on:
HEAD commit:43151d6c usb-fuzzer: main usb gadget fuzzer driver
git tree: https://github.com/google/kasan.git usb-fuzzer
console output: https://syzkaller.appspot.com/x/log.txt?x=162ca944a0
kernel config: https://syzkaller.appspot.com/x/.
Hi Lauretniu,
> I think that any recent kernel will do, so I'd say your current branch
> should be fine.
The kernel oopses with "unable to handle kernel paging request at virtual
address 000aba0b" in hcd_alloc_coherent via usb_hcd_map_urb_for_dma. This
relates to patch 2/3 that I didn't quite un
On Wed, 2019-05-15 at 13:09 +0100, Biju Das wrote:
> The RZ/G2E cat874 board has a type-c connector connected to hd3ss3220 usb
> type-c drp port controller. This patch adds dual role switch support for
> the type-c connector using the usb role switch class framework.
>
> Signed-off-by: Biju Das
>
On Tegra210, usb2 only otg/peripheral ports dont work in device mode.
They need an assosciated usb3 port to work in device mode. Identify
an unused usb3 port and assign it as a fake USB3 port to USB2 only
port whose mode is otg/peripheral.
Based on work by BH Hsieh .
Signed-off-by: Nagarjuna Kris
Configure the port capabilities based on usb_dr_mode settings.
Based on work by JC Kuo .
Signed-off-by: Nagarjuna Kristam
---
drivers/phy/tegra/xusb-tegra210.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra210.c
b/driver
This is the third verion of series "Tegra XUSB gadget driver support"
Patches 1-3 are phy driver changes to add support for device
mode.
Patches 4-7 are changes related to XUSB device mode
controller driver.
Patch 8 is to enable XUDC driver in defconfig
Test Steps(USB 2.0):
- Enable "USB Gadget p
Add device-tree binding documentation for the XUSB device mode controller
present on Tegra210 SoC. This controller supports the USB 3.0
specification.
Signed-off-by: Nagarjuna Kristam
---
.../devicetree/bindings/usb/nvidia,tegra-xudc.txt | 101 +
1 file changed, 101 insertio
Tegra210 has one XUSB device mode controller, which can be operated
HS and SS modes. Add DT support for XUSB device mode controller.
Signed-off-by: Nagarjuna Kristam
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/b
Tegra XUSB device control driver needs to control vbus override
during its operations, add API for the support.
Signed-off-by: Nagarjuna Kristam
---
drivers/phy/tegra/xusb-tegra210.c | 59 +++
drivers/phy/tegra/xusb.c | 22 +++
drivers/phy
Enable XUSB device mode driver for USB0 slot on Jetson TX1.
Signed-off-by: Nagarjuna Kristam
---
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
b/arch/arm64/boot/dts/nvidia/tegra21
Enable support for Nvidia XUSB device mode controller driver.
Signed-off-by: Nagarjuna Kristam
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b605b7f..bf1437c 100644
--- a/arch/arm64/configs/d
This patch adds UDC driver for tegra XUSB 3.0 device mode controller.
XUSB device mode controller supports SS, HS and FS modes
Based on work by:
Mark Kuo
Andrew Bresticker
Signed-off-by: Nagarjuna Kristam
---
drivers/usb/gadget/udc/Kconfig | 10 +
drivers/usb/gadget/udc/Makefile
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