On Tue, May 14, 2019 at 09:55:53AM -0500, Chris Brandt wrote: > The RZ/A2 has an optional dedicated 48MHz clock input for the PLL. > If a clock node named 'usb_x1' exists and set to non-zero, then we can > assume we want it use it. > > Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Simon Horman <horms+rene...@verge.net.au>
