Hi Chris-san, > From: Chris Brandt, Sent: Tuesday, May 14, 2019 11:56 PM > > The RZ/A2 has an optional dedicated 48MHz clock input for the PLL. > If a clock node named 'usb_x1' exists and set to non-zero, then we can > assume we want it use it. > > Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Thank you for the patch! Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda...@renesas.com> Best regards, Yoshihiro Shimoda
