For some SoC, CNEN must be set for USB Device mode operation.

Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda...@renesas.com>
Reviewed-by: Simon Horman <horms+rene...@verge.net.au>
---
v3:
 * added reviewed-by
v2:
 * options are now held in param
---
 drivers/usb/renesas_usbhs/common.c | 6 ++++++
 drivers/usb/renesas_usbhs/common.h | 1 +
 include/linux/usb/renesas_usbhs.h  | 1 +
 3 files changed, 8 insertions(+)

diff --git a/drivers/usb/renesas_usbhs/common.c 
b/drivers/usb/renesas_usbhs/common.c
index 1de7a44f3415..734fb4e542c5 100644
--- a/drivers/usb/renesas_usbhs/common.c
+++ b/drivers/usb/renesas_usbhs/common.c
@@ -114,6 +114,12 @@ void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int 
enable)
        u16 mask = DCFM | DRPD | DPRPU | HSE | USBE;
        u16 val  = HSE | USBE;
 
+       /* CNEN bit is required for function operation */
+       if (usbhs_get_dparam(priv, has_cnen)) {
+               mask |= CNEN;
+               val  |= CNEN;
+       }
+
        /*
         * if enable
         *
diff --git a/drivers/usb/renesas_usbhs/common.h 
b/drivers/usb/renesas_usbhs/common.h
index 1fbffb7bbc8f..de74ebd1a347 100644
--- a/drivers/usb/renesas_usbhs/common.h
+++ b/drivers/usb/renesas_usbhs/common.h
@@ -104,6 +104,7 @@ struct usbhs_priv;
 
 /* SYSCFG */
 #define SCKE   (1 << 10)       /* USB Module Clock Enable */
+#define CNEN   (1 << 8)        /* Single-ended receiver operation Enable */
 #define HSE    (1 << 7)        /* High-Speed Operation Enable */
 #define DCFM   (1 << 6)        /* Controller Function Select */
 #define DRPD   (1 << 5)        /* D+ Line/D- Line Resistance Control */
diff --git a/include/linux/usb/renesas_usbhs.h 
b/include/linux/usb/renesas_usbhs.h
index 17fae6e504cc..9097a38fcda8 100644
--- a/include/linux/usb/renesas_usbhs.h
+++ b/include/linux/usb/renesas_usbhs.h
@@ -190,6 +190,7 @@ struct renesas_usbhs_driver_param {
        u32 has_sudmac:1; /* for SUDMAC */
        u32 has_usb_dmac:1; /* for USB-DMAC */
        u32 runtime_pwctrl:1;
+       u32 has_cnen:1;
 #define USBHS_USB_DMAC_XFER_SIZE       32      /* hardcode the xfer size */
 };
 
-- 
2.16.1

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