== Series Details ==
Series: drm/i915: Hoist some stuff out from intel_display.c (rev3)
URL : https://patchwork.freedesktop.org/series/144803/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16138 -> Patchwork_144803v3
Summar
== Series Details ==
Series: drm/i915: Hoist some stuff out from intel_display.c (rev3)
URL : https://patchwork.freedesktop.org/series/144803/
State : warning
== Summary ==
Error: dim checkpatch failed
79a4ae90acfe drm/i915: Move modeset_retry stuff into intel_connector.c
6f3f585a7efe drm/i915
== Series Details ==
Series: drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
URL : https://patchwork.freedesktop.org/series/144909/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16138 -> Patchwork_144909v1
== Series Details ==
Series: drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
URL : https://patchwork.freedesktop.org/series/144909/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
with ECC enabled. We need to identify this scenario and add a new
case in xelpdp_get_dram_info() to handle it. In addition, the
derating value needs to be adjusted accordingly to compensate for
the limited bandwidth.
Bspec: 64602
C
On Fri, Feb 14, 2025 at 05:18:49PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ddi: Fix/simplify port enabling/disabling (rev2)
> URL : https://patchwork.freedesktop.org/series/144122/
> State : failure
Patchset is merged to drm-intel-next, thanks for the reviews.
The f
On Fri, Feb 14, 2025 at 10:15:25PM +0200, Imre Deak wrote:
> On Fri, Feb 14, 2025 at 05:18:49PM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/ddi: Fix/simplify port enabling/disabling (rev2)
> > URL : https://patchwork.freedesktop.org/series/144122/
> > State : failur
== Series Details ==
Series: series starting with [1/3] drm/xe/display: Move display runtime suspend
to a later point
URL : https://patchwork.freedesktop.org/series/144901/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16136 -> Patchwork_144901v1
=
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Thursday, February 13, 2025 3:26 PM
> To: Murthy, Arun R ; dri-
> de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: RE: [PATCH v5 2/3] drm/plane: mo
== Series Details ==
Series: series starting with [1/3] drm/xe/display: Move display runtime suspend
to a later point
URL : https://patchwork.freedesktop.org/series/144901/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be check
Hi Vinay,
Reviewing this since it's also in Riana's engine activity series. Mostly
recommendations.
On Tue, Feb 04, 2025 at 06:10:55PM -0800, Vinay Belgaumkar wrote:
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
v3: Review comments (Lucas)
Cc: Ria
== Series Details ==
Series: drm/i915: Hoist some stuff out from intel_display.c (rev2)
URL : https://patchwork.freedesktop.org/series/144803/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16136 -> Patchwork_144803v2
Summar
== Series Details ==
Series: drm/i915: Hoist some stuff out from intel_display.c (rev2)
URL : https://patchwork.freedesktop.org/series/144803/
State : warning
== Summary ==
Error: dim checkpatch failed
f9ce417809fb drm/i915: Move modeset_retry stuff into intel_connector.c
5e212998282f drm/i915
== Series Details ==
Series: series starting with [v3,1/2] drm/edid: Implement DisplayID Type IX & X
timing blocks parsing
URL : https://patchwork.freedesktop.org/series/144887/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16136 -> Patchwork_144887v1
Move dsm register/unregister calls from the drivers to under
intel_display_driver register/unregister.
v2: Rebase only
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_driver.c | 4
drivers/gpu/drm/i915/i915_driver.c
== Series Details ==
Series: series starting with [v3,1/2] drm/edid: Implement DisplayID Type IX & X
timing blocks parsing
URL : https://patchwork.freedesktop.org/series/144887/
State : warning
== Summary ==
Error: dim checkpatch failed
6652ef3c4e6a drm/edid: Implement DisplayID Type IX & X t
On the regular igfx runtime pm sequence where d3cold is not
possible, the proper calls to power display are required.
Align with i915.
v2: Rebase only.
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/xe/display/xe_display.c | 6 ++
1 file changed, 6 insertions
On runtime suspend (regardless of d3cold), there's no need
to perform the display power sequences before we disable the GT
and IRQ.
In a matter of fact, the i915 runtime suspend needs to
disable power, which asserts that IRQs are disabled.
So, before the runtime_pm sequences can be reconciled, it
== Series Details ==
Series: Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12 (rev2)
URL : https://patchwork.freedesktop.org/series/144678/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16136 -> Patchwork_144678v2
== Series Details ==
Series: Introduce drm sharpness property (rev8)
URL : https://patchwork.freedesktop.org/series/138754/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16136 -> Patchwork_138754v8
Summary
---
**FAIL
== Series Details ==
Series: Introduce drm sharpness property (rev8)
URL : https://patchwork.freedesktop.org/series/138754/
State : warning
== Summary ==
Error: dim checkpatch failed
01aefcb25d32 drm: Introduce sharpness strength property
2a5374b660b1 drm/i915/display: Compute the scaler filte
== Series Details ==
Series: Introduce drm sharpness property (rev8)
URL : https://patchwork.freedesktop.org/series/138754/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, 14 Feb 2025, Egor Vorontsov wrote:
> Some newer high refresh rate consumer monitors (including those by Samsung)
> make use of DisplayID 2.1 timing blocks in their EDID data, notably for
> their highest refresh rate modes. Such modes won't be available as of now.
>
> Implement partial supp
Using le16 instead of u8[2].
Suggested-by: Jani Nikula
Signed-off-by: Egor Vorontsov
---
drivers/gpu/drm/drm_displayid_internal.h | 18 +++
drivers/gpu/drm/drm_edid.c | 28
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/driver
Some newer high refresh rate consumer monitors (including those by Samsung)
make use of DisplayID 2.1 timing blocks in their EDID data, notably for
their highest refresh rate modes. Such modes won't be available as of now.
Implement partial support for such blocks in order to enable native
support
Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this
is performance optimization.
Bspec: 46132
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/int
I put writing of this bit in gt_tuning_settings(). Not sure if it is correct
place or should this be in gen12_gt_workarounds_init()..or somewhere
totally different place.
v2: move writing of bit to gen12_ctx_workarounds_init() where it seems to
fit better. Renamed register from XEHP_* to GEN8_*
/
On Fri, 14 Feb 2025, Imre Deak wrote:
> This v2 of [1], addressing the review comments from Jani and adding Rbs.
> This version contains only the first half of the patchset, leaving the
> rest for a follow-up, since programming DDI_BUF_CTL via RMW contained in
> the latter part needs more thought.
== Series Details ==
Series: drm/i915/ddi: Fix/simplify port enabling/disabling (rev2)
URL : https://patchwork.freedesktop.org/series/144122/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16134 -> Patchwork_144122v2
Summary
== Series Details ==
Series: drm/i915/ddi: Fix/simplify port enabling/disabling (rev2)
URL : https://patchwork.freedesktop.org/series/144122/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/inclu
Load the lut values during pipe enable.
v2: Add the display version check
v3: Fix build issue
v4: Rebase
v5: Add HAS_CASF macro. [Ankit]
Add scaler_id check while reading state. [Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Naga Venkata Srikanth V
---
drivers/gpu/drm/i915/display/intel_c
== Series Details ==
Series: drm/i915/ddi: Fix/simplify port enabling/disabling (rev2)
URL : https://patchwork.freedesktop.org/series/144122/
State : warning
== Summary ==
Error: dim checkpatch failed
9bfd2ee16337 drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
dc37836b346f drm/i91
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
v2: Replace i915/dev_priv with display[Jani]
v3: Create separate file for defining register[Jani]
Add display->drm in debug prints[Jani]
v4: Rebase
v5: Fix build issue
v6: Remove erraneous condi
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is also not enabled,
then set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Add the panel fitting check before enabling sharpness
v3: Reframe commit message
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all values and then dividing each value with a sum.
Write the scaler registers for sharpness.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 2 +
drivers/gpu/drm/i915/display/skl_scaler.c | 45 +++
drivers/gpu/drm/i915/display/skl_scaler.h | 1 +
3 files chan
Introduces the new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
Many a times images are blurred or upscaled content is also not as
crisp as original rendered image. Traditional sharpening techniques often
apply a uniform level of enhancement across entire image, which sometimes
result in over-sharpening of some areas and potential loss of natural details.
I
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state (rev3)
URL : https://patchwork.freedesktop.org/series/144102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16134 -> Patchwork_144102v3
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state (rev3)
URL : https://patchwork.freedesktop.org/series/144102/
State : warning
== Summary ==
Error: dim checkpatch failed
81afe0ccad86 drm/i915/display: Drop crtc_state from C10/C20 pll programming
-:60: WARN
A port can be disabled only via a modeset (or during HW state
sanitization) when the port is enabled. Thus it's not required to check
the port's enabled state before disabling it. In any case if the port
happened to be disabled, the following disabling would be just a nop and
waiting for the buffer
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
Align the DDI_BUF_CTL register flag definitions with how this is done
elsewhere.
v2: Robustify macro calls with parens. (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_reg.h | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
d
Make the PORT_WIDTH macro of the XELPDP_PORT_CTL1 register work the same
way as those used for the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL
registers: accept a width parameter and convert it to the given
register's encoding.
v2: Robustify macro calls with parens. (Jani)
Reviewed-by: Jani Nikula
Si
The prefix of the mtl_ddi_enable_d2d() / mtl_ddi_disable_d2d_link()
names show already what are the relevant platforms, so the corresponding
platform check is a detail that can be hidden in the functions, do so.
While at it rename mtl_ddi_disable_d2d_link() to mtl_ddi_disable_d2d()
for symmetry wi
Add a helper to enable a port instead of open-coding it.
While at it rename intel_disable_ddi_buf() to intel_ddi_buf_disable()
for consistency.
v2: (Jani)
- s/intel_enable_ddi_buf/intel_ddi_buf_enable
- s/intel_disable_ddi_buf/intel_ddi_buf_disable
Reviewed-by: Jani Nikula
Signed-off-by: Imre D
The functions disabling a port for MTL+ and earlier platforms only
differ by an extra step on MTL+ (to disable the D2D link) and the point
at which the port's idle state is waited for. Combine the two functions
accounting for the above differences, removing the duplication.
Reviewed-by: Jani Nikul
In the past intel_digital_port::dp.prepare_link_retrain() could be
called directly (vs. from a modeset) to retrain an enabled link. In that
case the port had to be first disabled and then re-enabled. That changed
with commit 2885d283cce5 ("drm/i915/dp: Retrain SST links via a modeset
commit"), afte
When waiting for a port to get active/idle there is no point in the
complexity of specifying an exact timeout and for that the suitable wait
API instead of just using the maximum timeout. The sequence in
particular is not performance critical at all either and due to
scheduling it's not guaranteed
Add the missing PHY lane stagger delay programming for ICL-ADL
platforms on TypeC DP outputs.
v2: (Jani)
- Clarify code comment about lane stagger programming.
- Robustify macro calls with parens.
Bspec: 7534, 49533
Reviewed-by: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/dis
The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.
Cc: # v6.5+
Fixes:
Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
where this had an off-by-one error.
Cc: # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in
DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gp
This v2 of [1], addressing the review comments from Jani and adding Rbs.
This version contains only the first half of the patchset, leaving the
rest for a follow-up, since programming DDI_BUF_CTL via RMW contained in
the latter part needs more thought.
Cc: Jani Nikula
Cc: Mika Kahola
[1] https:
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
For PLL programming for C10 and C20 we don't need to
carry crtc_state but instead use only necessary parts
of the crtc_state i.e. pll_state.
This change is needed to PTL wa 14023648281 where we would
need to otherwise pass an artificial crtc_state with majority
of the struct members initialized as
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, February 5, 2025 1:44 PM
> To: Garg, Nemesa ; intel-gfx@lists.freedesktop.org;
> intel...@lists.freedesktop.org
> Subject: Re: [PATCH 3/6] drm/i915/display: Configure the scaler
>
>
>
> On 1/13/2025 4:19 PM, Nemesa Garg
Hi Andi,
On Wednesday, 12 February 2025 16:32:18 CET Andi Shyti wrote:
> Hi Janusz,
>
> On Tue, Feb 11, 2025 at 01:12:37PM +0100, Janusz Krzysztofik wrote:
> > On Monday, 10 February 2025 14:01:19 CET Andi Shyti wrote:
> > > On Thu, Feb 06, 2025 at 07:07:38PM +0100, Janusz Krzysztofik wrote:
> >
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev9)
URL : https://patchwork.freedesktop.org/series/134383/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16134 -> Patchwork_134383v9
Summ
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev9)
URL : https://patchwork.freedesktop.org/series/134383/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/in
On 2/13/2025 1:55 PM, Suraj Kandpal wrote:
Testing HDCP 1.4 becomes tough since the only way our code comes to
HDCP 1.4 pathway is if the monitor only supports HDCP 1.4 which
becomes tough to find sometimes.
Setting this debug_fs entry will force use to use the HDCP 1.4 path
so that more robust
For platforms for which vrr timing generator is always set, VRR_CTL
enable bit does not need to toggle, so modify the vrr_{enable/disable}
for this.
At the moment the helper intel_vrr_always_use_vrr_tg() return false for
all cases. This will be set later when all other bits are in place.
Signed-of
Add fixed refresh rate mode in crtc_state dump.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 1 -
drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
3 files changed, 3 insertions(+)
Update the intel_set_transcoder_timings_lrr() function to use
fixed refresh rate timings for platforms which always use
VRR timing generator.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i91
Currently VRR timing generator is used only when VRR is enabled by
userspace for sinks that support VRR. From MTL+ gradually move away from
the older timing generator and use VRR timing generator for both variable
and fixed timings.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/
LRR and Vmax can be computed only if VRR is supported and vrr.in_range
is set. Currently we proceed with vrr timings only for VRR supporting
panels and return otherwise. For using VRR TG with fix timings, need to
continue even for panels that do not support VRR.
To achieve this, refactor the condi
During modeset enable sequence, program the fixed timings,
and turn on the VRR Timing Generator (VRR TG) for platforms
that always use VRR TG.
Later if vrr timings are required, vrr_enable() will switch
to the real VRR timings.
With this we dont want to reset TRANS_CTL_VRR Enable bit while updati
Do not program transcoder registers for VRR for the secondary pipe of
the joiner. Remove check to skip VRR for joiner case.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/
To have fixed refresh rate with VRR timing generator the
guardband/pipeline full can't be programmed on the fly. So we need to
ensure that the values satisfy both the fixed and variable refresh
rates.
Since we compute these value based on vmin, lets set the vmin to
crtc_vtotal for both fixed and v
As per bspec 49268: Disable PSR before disabling VRR.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.
Wa_14015406119 is required for PSR1/2 while working with fixed refresh
rate with VRR timing generator.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_displa
Add support for using VRR Timing generator for HDMI panels.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/inte
MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
refresh rate.
Currently for link training we depend on flipline to decide whether we
want to ignore the msa timings. With fixed refresh rate we will still
fill the flipline in all cases whether panel supports VRR or not.
C
Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
generator is used with variable timings.
Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
when vmax == vmin == flipline (fixed refresh rate timing).
Signed-off-by: Ankit Nautiyal
---
drivers/gp
Switching between variable and fixed timings is possible as for that we
just need to flip between VRR timings. However for CMRR along with the
timings, few other bits also need to be changed on the fly, which might
cause issues. So disable CMRR for now, till we have variable and fixed
timings sorte
Currently we always compute the timings as if vrr is enabled.
With this approach the state checker becomes complicated when we
introduce fixed refresh rate mode with vrr timing generator.
To avoid the complications, instead of always computing vrr timings, we
compute vrr timings based on uapi.vrr_
Currently we do not support VRR with HDMI so skip vrr compute
config step for DP with HDMI sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers
Make helpers to compute vmin and vmax.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 39 +++-
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
ind
Separate out functions for computing cmrr and vrr timings.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++-
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/di
The comment about fixed average vtotal is incorrect.
Remove it.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index cac4931902
Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax must be equal
(TRANS_VRR_FLIPLINE = TRANS_VRR_VMAX). Beyond that, there are some
dependencies between the VRR timin
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, February 14, 2025 1:01 PM
> To: Kandpal, Suraj ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/psr: Fix drm_WARN_ON in intel_psr_disable
>
> On Fri, 2025-02-14 at 04:27 +,
> -Original Message-
> From: dri-devel On Behalf Of
> Kandpal, Suraj
> Sent: Friday, February 14, 2025 3:32 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: dmitry.barysh...@linaro.org
> Subject: RE: [PATCH
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, January 28, 2025 9:21 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Kandpal, Suraj ; dmitry.barysh...@linaro.org;
> Murthy, Arun R
> Subject: [PATCH v8 09/14
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, January 28, 2025 9:21 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Kandpal, Suraj ; dmitry.barysh...@linaro.org;
> Murthy, Arun R
> Subject: [PATCH v8 08/14
== Series Details ==
Series: drm/i915: Add drm_panic support (rev5)
URL : https://patchwork.freedesktop.org/series/141935/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
LD [M] drivers/gpu/drm/i915/i915.o
L
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, January 28, 2025 9:21 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Kandpal, Suraj ; dmitry.barysh...@linaro.org;
> Murthy, Arun R
> Subject: [PATCH v8 06/14
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, January 28, 2025 9:21 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Kandpal, Suraj ; dmitry.barysh...@linaro.org;
> Murthy, Arun R
> Subject: [PATCH v8 04/14
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, January 28, 2025 9:21 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Kandpal, Suraj ; dmitry.barysh...@linaro.org;
> Murthy, Arun R
> Subject: [PATCH v8 03/14
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, 12 February 2025 16.49
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org;
> intel-
> x...@lists.freedesktop.org; jani.nik...@linux.intel.com
> Subject: Re: [PATCH v2 2/2] drm/i915/display: Allow display PHYs to reset
> power
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, 12 February 2025 16.40
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org;
> intel-
> x...@lists.freedesktop.org; jani.nik...@linux.intel.com
> Subject: Re: [PATCH v2 2/2] drm/i915/display: Allow display PHYs to reset
> power
>
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, 12 February 2025 16.39
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org;
> jani.nik...@linux.intel.com
> Subject: Re: [PATCH v2 2/2] drm/i915/display: Allow display PHYs to reset
> power
>
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 22 ++-
1 file changed, 21 i
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 69 ++-
.../drm/i915/display
On Lunar Lake, if the panic occurs when fbcon is active, the panic
screen is only partially visible on the screen. Adding this
intel_frontbuffer_flush() call solves the issue.
It's probably not safe to do that in the panic handler, but that's
still better than nothing.
Signed-off-by: Jocelyn Falem
This adds drm_panic support for a wide range of Intel GPU. I've
tested it only on 4 laptops, Haswell (with 128MB of eDRAM),
Comet Lake, Alder Lake, and Lunar Lake.
For hardware using DPT, it's not possible to disable tiling, as you
will need to reconfigure the way the GPU is accessing the
framebuff
Prepare the work for drm_panic support. This is used to map the
current framebuffer, so the CPU can overwrite it with the panic
message.
Signed-off-by: Jocelyn Falempe
---
v5:
* Use iosys_map for intel_bo_panic_map().
drivers/gpu/drm/i915/display/intel_bo.c| 5
drivers/gpu/drm/i915/
drm_panic draws in linear framebuffer, so it's easier to re-use the
current framebuffer, and disable tiling in the panic handler, to show
the panic screen.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_displa
drm_panic draws in linear framebuffer, so it's easier to re-use the
current framebuffer, and disable tiling in the panic handler, to show
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
* Add int
This is a draft of drm_panic support for i915.
I've tested it on the 4 intel laptops I have at my disposal.
* Haswell with 128MB of eDRAM.
* Comet Lake.
* Alder Lake (with DPT, and Y-tiling).
* Lunar Lake (with DPT, and 4-tiling, and using the Xe driver.
I tested panic in both fbdev console a
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