[PATCH v2 01/11] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Imre Deak]

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <sta...@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in 
DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9600c2a346d4c..5d3d54922d629 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -805,8 +805,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder 
*encoder,
                /* select data lane width */
                tmp = intel_de_read(display,
                                    TRANS_DDI_FUNC_CTL(display, dsi_trans));
-               tmp &= ~DDI_PORT_WIDTH_MASK;
-               tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+               tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+               tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
                /* select input pipe */
                tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
-- 
2.44.2