[PATCH v5 8/8] drm/i915/display: Add drm_panic support for 4-tiling with DPT

[Jocelyn Falempe]

On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.

Signed-off-by: Jocelyn Falempe <jfale...@redhat.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 22 ++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4cb12fdc21fe4..2a319cd319566 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1241,6 +1241,25 @@ static void intel_ytile_set_pixel(struct 
drm_scanout_buffer *sb, unsigned int x,
        iosys_map_wr(&sb->map[0], offset, u32, color);
 }
 
+static void intel_4tile_set_pixel(struct drm_scanout_buffer *sb, unsigned int 
x, unsigned int y,
+                                 u32 color)
+{
+       u32 offset;
+       unsigned int swizzle;
+       unsigned int width_in_blocks = DIV_ROUND_UP(sb->width, 32);
+
+       /* Block offset */
+       offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * 
YTILE_SIZE;
+
+       x = x % YTILE_WIDTH;
+       y = y % YTILE_HEIGHT;
+
+       /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */
+       swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | 
((x & 0x10) << 3) | ((y & 0x18) << 5);
+       offset += swizzle * 4;
+       iosys_map_wr(&sb->map[0], offset, u32, color);
+}
+
 static void intel_panic_flush(struct drm_plane *plane)
 {
        struct intel_plane_state *plane_state = 
to_intel_plane_state(plane->state);
@@ -1275,7 +1294,6 @@ static void (*intel_get_tiling_func(u64 
fb_modifier))(struct drm_scanout_buffer
        case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
        case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
                return intel_ytile_set_pixel;
-       case I915_FORMAT_MOD_X_TILED:
        case I915_FORMAT_MOD_4_TILED:
        case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
        case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
@@ -1285,6 +1303,8 @@ static void (*intel_get_tiling_func(u64 
fb_modifier))(struct drm_scanout_buffer
        case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
        case I915_FORMAT_MOD_4_TILED_BMG_CCS:
        case I915_FORMAT_MOD_4_TILED_LNL_CCS:
+               return intel_4tile_set_pixel;
+       case I915_FORMAT_MOD_X_TILED:
        case I915_FORMAT_MOD_Yf_TILED:
        case I915_FORMAT_MOD_Yf_TILED_CCS:
        default:
-- 
2.47.1