Currently VRR timing generator is used only when VRR is enabled by
userspace for sinks that support VRR. From MTL+ gradually move away from
the older timing generator and use VRR timing generator for both variable
and fixed timings.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4151fcd0f978..d0b18102ef2c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -346,7 +346,7 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
vmin = intel_vrr_compute_vmin(crtc_state);
- if (vmin >= vmax)
+ if (vmin >= vmax && !intel_vrr_always_use_vrr_tg(display))
return;
crtc_state->vrr.vmin = vmin;
@@ -361,7 +361,7 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
*/
crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display);
- if (crtc_state->uapi.vrr_enabled)
+ if (crtc_state->uapi.vrr_enabled && vmin < vmax)
intel_vrr_compute_vrr_timings(crtc_state);
else if (is_cmrr_frac_required(crtc_state) && is_edp)
intel_vrr_compute_cmrr_timings(crtc_state);
@@ -545,7 +545,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display
*display)
if (!HAS_VRR(display))
return false;
- /* #TODO return true for platforms supporting fixed_rr */
+ if (DISPLAY_VER(display) >= 14)
+ return true;
+
return false;
}
--
2.45.2
