[PATCH v3] RISC-V: Fix code gen for reduction with length 0 [PR118182]

`.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold_left_plus_m`) is expecting the return value will be the start value even if the length is 0. However current code gen in RISC-V backend is not meet that semantic, it will result a random garbage value if length is 0. Let example by current code gen for

Re: [PATCH v2] RISC-V: Fix code gen for reduction with length 0 [PR118182]

sorry for my stupid mistake, forgot v2, it's just same as v1 and see v3 On Mon, Dec 23, 2024 at 11:15 PM Kito Cheng wrote: > > --- > gcc/config/riscv/autovec-opt.md | 16 ++-- > gcc/config/riscv/autovec.md | 30 +++ > gcc/config/riscv/riscv-v.cc

Re: [PATCH] RISC-V: Fix code gen for reduction with length 0 [PR118182]

On Mon, Dec 23, 2024 at 10:35 PM Robin Dapp wrote: > > > +;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs), but for > > auto vectorizer > > +(define_insn "@pred_av_" > > + [(set (match_operand: 0 "register_operand" "=vr") > > + (unspec: > > + [(unspec: > >

Re: [PATCH v2 2/4] RISC-V: Add Zicfilp ISA extension.

OK with few minor comments > This patch only support landing pad value is 1. Should be 0? > --- /dev/null > +++ b/gcc/config/riscv/riscv-zicfilp.cc > @@ -0,0 +1,169 @@ > +/* Branch Target Identification for RISCV architecture. > + Copyright (C) 2019-2024 Free Software Foundation, Inc. 2025 >

Re: [PATCH v3 3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension

OK with one minor comment: > diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h > index 9060c940a44..c1cfa9bf28a 100644 > --- a/gcc/config/riscv/linux.h > +++ b/gcc/config/riscv/linux.h > @@ -61,6 +61,8 @@ along with GCC; see the file COPYING3. If not see > -dynamic-linker "

Re: [PATCH v5 1/4] RISC-V: Add Zicfiss ISA extension.

(_Unwind_Frames_Extra): Define. > (_Unwind_Frames_Increment): Define. > > gcc/testsuite/ChangeLog: > * gcc/testsuite/gcc.target/riscv/ssp-1.c: New test. > * gcc/testsuite/gcc.target/riscv/ssp-2.c: New test. > > Co-Developed-by: Greg McGary , >

Re: [PATCH v3 1/2] RISC-V: Update Xsfvfnrclip implementation.

committed, thanks :) On Fri, Dec 13, 2024 at 8:39 PM Jiawei wrote: > > Update implementation of Xsfvfnrclip, using return type as iterator. > > gcc/ChangeLog: > > * config/riscv/genrvv-type-indexer.cc (expand_floattype): New func. > (main): New type. > * config/riscv/riscv

Re: [PATCH v3 2/2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases

committed, thanks :) On Fri, Dec 13, 2024 at 8:39 PM Jiawei wrote: > > From: Liao Shihua > > Update Sifive Xsfvqmacc and Xsfvfnrclip extension's testcases. > > version log: > Update synchronize LMUL settings with return type. > > gcc/ChangeLog: > > * config/riscv/vector.md: New a

Re: [PATCH v4] RISC-V: Fix code gen for reduction with length 0 [PR118182]

committed to trunk On Mon, Jan 6, 2025 at 6:06 PM Kito Cheng wrote: > > `.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold_left_plus_m`) is expecting the > return value will be the start value even if the length is 0. > > However current code gen in RISC-V backend is not meet that se

Re: [PATCH v3 1/4] RISC-V: Add Zicfiss ISA extension.

OK with one minor comment On Wed, Jan 15, 2025 at 3:57 PM Monk C > --- /dev/null > +++ b/libgcc/config/riscv/shadow-stack-unwind.h > @@ -0,0 +1,74 @@ > +/* _Unwind_Frames_Extra with shadow stack. > + Copyright (C) 2016-2024 Free Software Foundation, Inc. 2025 rather than 2016-2024.

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

On Mon, Mar 24, 2025 at 11:35 PM Robin Dapp wrote: > > > This does not only happen on ELEN=32 and VLEN=32, it happened on all > > ELEN=32 arch, and one of our internal configurations hit this... > > Wait, is there something I keep missing? There must be I guess. > > Disregarding the SEW=8 case be

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

On Mon, Mar 24, 2025 at 6:53 PM Robin Dapp wrote: > > Hi Kito, > > > So valid range fractional LMUL for SEW=8, 16 32 are: > > > > mf8 = [8, (1/8)*32] = [8, 4] = [], no SEW is valid with mf8 for ELEN = 32 > > mf4 = [8, (1/4)*32] = [8, 8] = only SEW 8 with mf4 is valid > > mf2 = [8, (1/2)*32] = [8,

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

Hi Robin: Just got few more clarifications from Andrew about the behavior for the valid* LMUL for ELEN=32, * valid may not be a precise word, anyway, the spec guarantees that it should be implemented. Spec[1] say: --- When LMUL < SEWMIN/ELEN, there is no guarantee an implementation would have

Re: [PATCH] RISC-V: Remove the priority in FMV ASM name mangling

Will it only cause issues with this patch https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678918.html or will it cause problems with the current trunk as well? If the latter one, could you provide a case for that? Thanks :) On Tue, Mar 25, 2025 at 7:15 PM Yangyu Chen wrote: > > We don't ne

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

Hi Robin Sorry Kito, that we're having so much back and forth here, it's not my > intention to block anything (not that I could anyway). I just want to > make sure I properly understand the rationale (or the spec, rather). > No worries, it's a great chance to clarify the spec together :) Some t

Re: [PATCH] riscv: Fix incorrect gnu property alignment on rv32

On Thu, Apr 10, 2025 at 9:12 PM Jesse Huang wrote: > > Codegen is incorrectly emitting a ".p2align 3" that coerces the > alignment of the .note.gnu.property section from 4 to 8 on rv32. > --- > gcc/config/riscv/riscv.cc | 2 +- > gcc/testsuite/gcc.target/riscv/gnu-proper

Re: [PATCH] riscv: Fix r15-9270 fallout on RISC-V

Hi Jakub: Checked with SVE's implementation and seems right for RVV, so OK for trunk, thanks :) On Wed, Apr 9, 2025 at 9:24 PM Jakub Jelinek wrote: > > Hi! > > On Wed, Apr 09, 2025 at 02:38:01PM +0200, Mark Wielaard wrote: > > Unfortunately this seems to have broken the riscv bootstrap: > > http

[committed] RISC-V: Include local riscv_vector.h in testsuite

That could prevent us including stdint.h from glibc, and that will cause problem when the corresponding multilib isn't built. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Include local riscv_vector.h. * gcc.target/riscv/rvv/base/abi-ca

[committed] RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32

Large code model is only supported on RV64, so we don't need to generate the multilibs for RV32 with --cmodel=large. And the compact code model is something we don't supported on upstream (which is accidentally added in the past), so we need to remove it. gcc/ChangeLog: * config/riscv/mul

Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

Hi Robin: Pushed to trunk, thanks, On Mon, Mar 31, 2025 at 11:23 PM Robin Dapp wrote: > > LGTM (even though I still don't like the spec :D). Yeah...and I also don't like the magic "ceil(AVL / 2) ≤ vl ≤ VLMAX if AVL < (2 * VLMAX)" rule... > We still have an implicit assumption in riscv-vsetvl.

[PATCH v2] RISC-V: Tweak testcase for PIE

Linux toolchain may configured with --enable-default-pie, and that will cause lots of regression test failures because the function name will append with @plt suffix (e.g. `call foo` become `call foo@plt`), also some code generation will different due to the code model like the address generation

Re: [PATCH] RISC-V: testsuite: Fix broken testsuite error of zicbop

Thanks, pushed to trunk :) On Mon, Mar 31, 2025 at 4:54 PM Liao Shihua wrote: > > Fix broken testsuite like > "ERROR: gcc.target/riscv/cmo-zicbop-2.c -Os : 1: too many arguments for " > dg-do 1 compile target { { rv32-*-*}} " > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/cmo-zicb

[PATCH] RISC-V: Tweak testcase for PIE

Linux toolchain may configured with --enable-default-pie, and that will cause lots of regression test failures because the function name will append with @plt suffix (e.g. `call foo` become `call foo@plt`). We may consider just drop @plt suffix to prevent that at all, because it's not difference b

Re: [PATCH v2] RISC-V: Tweak testcase for PIE

Push to trunk since the CI is green :) On Tue, Apr 1, 2025 at 3:43 PM Kito Cheng wrote: > > Linux toolchain may configured with --enable-default-pie, and that will > cause lots of regression test failures because the function name will > append with @plt suffix (e.g. `call foo` beco

Re: [PATCH] [testsuite] [riscv] limit vwaddsub-1.c to rv64

On Tue, Apr 1, 2025 at 12:47 PM Jeff Law wrote: > > > > On 3/31/25 7:03 PM, Alexandre Oliva wrote: > > On Mar 31, 2025, Jeff Law wrote: > >> I don't immediately see anything in this test or its history to > >> indicate it's only supposed to work for rv64. > > > > It's the 64-bit integral argument

Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.

Could you break this patch into two pieces: 1) Add new extensions. 2) Add new core (for -mcpu), pipeline model and cost model > diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1326c67563a..d2642390b2a > 100644 > --- a/gcc/ChangeLog > +++ b/gcc/ChangeLog > @@ -1,3 +1,24 @@ > +2025-04-09 Umesh K

Re: RISC-V: revert pr114194 tests on gcc-14 [PR118601]

LGTM, thanks :) Alexandre Oliva 於 2025年4月15日 週二 12:25 寫道： > > And here's another that came up more recently: > > The gcc-14 backport that split the pr114194 testcase for rv32 and rv64 > would only generate the expected rv32 sequence if commit > 6b315907c0353f71169a7555e653d29a981fef67 had also b

Re: [PATCH v6 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

pushed to trunk On Tue, Apr 29, 2025 at 9:16 PM Kito Cheng wrote: > > From: yulong > > This commit adds testcases for Xsfvcp. > > Co-Authored by: Jiawei Chen > Co-Authored by: Shihua Liao > Co-Authored by: Yixuan Chen > > gcc/testsuite/ChangeLog: > >

Re: [PATCH v3] RISC-V: Fix missing implied Zicsr from Zve32x

Seems CI still fail: https://github.com/ewlu/gcc-precommit-ci/issues/3282#issue-3030037257 Executing on host: /home/ewlu/precommit-08/_work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-newlib-stage2/gcc/xgcc -B/home/ewlu/pre commit-08/_work/gcc-precommit-ci/gcc-precommit-

Re: [PATCH] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

Hi Dongyan: > diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c > b/gcc/testsuite/gcc.target/riscv/arch-46.c > new file mode 100644 > index ..fb2bdf72597f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c > @@ -0,0 +1,10 @@ > +/* { dg-do compile } */ > +/* { dg-optio

Re: [PATCH v2] RISC-V: Recognized Svrsw60t59b extension

LGTM, but pending for the spec ratified, also a minor comment is the link seems dead, we may use https://github.com/riscv/riscv-isa-manual/pull/1907 instead On Fri, Mar 21, 2025 at 8:56 AM Mingzhu Yan wrote: > > This patch support svrsw60t59b extension[1]. > To enable GCC to recognize and process

Re: [PATCH v4] RISC-V: Fix missing implied Zicsr from Zve32x

Thanks, pushe to trunk :) On Wed, Apr 30, 2025 at 3:35 PM Jerry Zhang Jian wrote: > > The Zve32x extension depends on the Zicsr extension. > Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC. > > gcc/ChangeLog: > * common/config/riscv/riscv-common.cc: Add Zve32x depen

Re: [PATCH v6 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

pushed to trunk On Tue, Apr 29, 2025 at 9:14 PM Kito Cheng wrote: > > From: yulong > > This version is same as v5, but rebase to trunk, send out to trigger CI. > > This commit adds intrinsics support for Xsfvcp extension. > Diff with V4: Delete the sifive_vector.h fil

Re: [PATCH] RISC-V: Allow different dynamic floating point mode to be merged [PR119832]

pushed to the trunk :) Vineet: Feel free to drop TARGET_MODE_CONFLUENCE once you have a better solution :) On Wed, Apr 30, 2025 at 12:50 PM Robin Dapp wrote: > > > Although we already try to set the mode needed to FRM_DYN after a function > > call, > > there are still some corner cases where bo

[PATCH] RISC-V: Put jump table in text for large code model

Large code model assume the data or rodata may put far away from text section. So we need to put jump table in text section for large code model. gcc/ChangeLog: * config/riscv/riscv.h (JUMP_TABLES_IN_TEXT_SECTION): Check if large code model. gcc/testsuite/ChangeLog: * g

Re: [PATCH v2] riscv: Fix incorrect gnu property alignment on rv32

Thanks, committed to trunk :) On Fri, Apr 11, 2025 at 12:27 PM Jesse Huang wrote: > > Codegen is incorrectly emitting a ".p2align 3" that coerces the > alignment of the .note.gnu.property section from 4 to 8 on rv32. > > 2025-04-11 Jesse Huang > > gcc/ChangeLog > > * config/riscv/riscv

Re: [PATCH] RISC-V: Put jump table in text for large code model

committed :) On Mon, Apr 14, 2025 at 6:01 PM Kito Cheng wrote: > > This patch will be committed this week if CI passes and not strong > objections since it's bug to large code model, also change is small > > On Mon, Apr 14, 2025 at 6:00 PM Kito Cheng wrote: > > >

[PATCH] RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

gcc/testsuite/ChangeLog: PR target/120054 * gcc.target/riscv/predef-19.c: Adjust testcase. --- gcc/testsuite/gcc.target/riscv/predef-19.c | 4 1 file changed, 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c b/gcc/testsuite/gcc.target/riscv/predef-19.c

Re: [PATCH v6 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

t; cc1plus: all warnings being treated as errors > > https://builder.sourceware.org/buildbot/#/builders/338/builds/150 > > On Wed, Apr 30, 2025 at 05:25:34PM +0800, Kito Cheng wrote: > [...] > > > diff --git a/gcc/config/riscv/genrvv-type-indexer.cc > b/gcc/config/riscv/genrvv-type-indexer.cc

Re: [PATCH] RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

Pushed to the trunk :) On Mon, May 5, 2025 at 10:03 PM Jeff Law wrote: > > > > On 5/4/25 8:13 PM, Kito Cheng wrote: > > gcc/testsuite/ChangeLog: > > > > PR target/120054 > > * gcc.target/riscv/predef-19.c: Adjust testcase. > If you think it

Re: RISC-V: adjust testcase for gcc-14 [PR118182]

OK for GCC 14 branch, thanks :) On Tue, Apr 15, 2025 at 12:23 PM Alexandre Oliva wrote: > > On Apr 14, 2025, Jeff Law wrote: > > > No strong opinion. I'd lean towards xfail or twiddling the test since > > that's obviously super-save WRT codegen on the gcc-14 release branch. > > Twiddling it is,

Re: [PATCH] RISC-V: Put jump table in text for large code model

This patch will be committed this week if CI passes and not strong objections since it's bug to large code model, also change is small On Mon, Apr 14, 2025 at 6:00 PM Kito Cheng wrote: > > Large code model assume the data or rodata may put far away from > text section. So we ne

[PATCH] RISC-V: Allow different dynamic floating point mode to be merged [PR119832]

Although we already try to set the mode needed to FRM_DYN after a function call, there are still some corner cases where both FRM_DYN and FRM_DYN_CALL may appear on incoming edges. Therefore, we use TARGET_MODE_CONFLUENCE to tell GCC that FRM_DYN, FRM_DYN_CALL, and FRM_DYN_EXIT modes are compatibl

Re: [PATCH] RISC-V: Fix missing implied Zicsr from Zve32x

Seems like the testcase will fail https://github.com/ewlu/gcc-precommit-ci/issues/3278#issuecomment-2837806049 > diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c > b/gcc/testsuite/gcc.target/riscv/predef-19.c > index 2b90702192b..b29e60f9b99 100644 > --- a/gcc/testsuite/gcc.target/riscv/pr

[PATCH v6 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This version is same as v5, but rebase to trunk, send out to trigger CI. This commit adds intrinsics support for Xsfvcp extension. Diff with V4: Delete the sifive_vector.h file. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog:

[PATCH v6 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

From: yulong This commit adds testcases for Xsfvcp. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.

Re: [PATCH] RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS

LGTM, and pushed to the trunk :) On Mon, Apr 28, 2025 at 10:04 AM 曾治金 wrote: > > Hi, according to Jeff's requirement > (https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681864.html), I divide > the change of riscv_register_move_cost into separate patch. Please help to > review. Thanks. > >

[PATCH 1/8] RISC-V: Introduce riscv-ext*.def to define extensions

Adding a new ISA extension to RISC-V GCC requires modifying several places: 1. riscv_ext_version_table for the extension version. 2. riscv.opt for the target option and variable. 3. riscv_ext_flag_table to bind the extension to its target option. 4. riscv_combine_info if this extension is just a ma

[PATCH 6/8] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

Consolidate implied-extension logic by removing the old `riscv_implied_info` array and using the `implied_exts` field in the unified riscv_ext_info_t structures generated from `riscv-ext.def`. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info::riscv_implied_

[PATCH 4/8] RISC-V: Adjust riscv_can_inline_p

We don't hold any extenison flags in `target_flags`, so no need to gather the extenison flags in `target_flags`. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_can_inline_p): Drop extension flags check from `target_flags`. * config/riscv/riscv-subset.h (riscv_

[PATCH 5/8] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

Define a new riscv_ext_info_t struct to aggregate all ISA extension fields (name, version, flags, implied extensions, bitmask and extra flags) generated from riscv-ext.def. Also adjust riscv_ext_flag_table_t and riscv_implied_info_t to make it able to not hold extension name, this part will refact

[PATCH 8/8] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

Refactor extension flag handling by removing the old riscv_ext_flag_table and sourcing all flag definitions directly from the flags field of the unified riscv_ext_info_t structures generated from riscv-ext.def. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_extra_ext_flag_tab

[PATCH 2/8] RISC-V: Use riscv-ext.def to generate target options and variables

Leverage the centralized riscv-ext.def definitions to auto-generate the target option parsing and associated internal flags, replacing manual listings in riscv.opt; `riscv_ext_flag_table` part will remove in later patch. gcc/ChangeLog: * config/riscv/gen-riscv-ext-opt.cc: New. * c

[PATCH 7/8] RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

This commit drops the riscv_ext_version_table and instead uses the riscv_ext_info_t data structure to provide the version information for RISC-V extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove. (standard_extensions_p): Use

Re: [RFC] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results.

We already have a use of "(reg:SI FRM_REGNUM)" within the pattern, is it not enough? I believe the answer is not enough so you propose this patch, so could you explain a few more about what happened? (define_insn "@pred_single_widen__scalar" [(set (match_operand:VWEXTF 0 "register_operand"

[PATCH v2] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

This patch fixes the multilib_os_dir and multiarch_dir for those targets that use TARGET_COMPUTE_MULTILIB, since the TARGET_COMPUTE_MULTILIB hook only update/fix the multilib_dir but not the multilib_os_dir and multiarch_dir, so the multilib_os_dir and multiarch_dir are not set correctly for those

Re: [PATCH] RISC-V: Fix .cfi_offset directive when push pop in zc

Thanks, will push after verified on my hand :) On Mon, Feb 24, 2025 at 3:20 PM Hsing Yu Peng wrote: > > Address Fei's comment. > > Thanks > Lino > > Fei Gao 於 2025年2月24日 週一 下午2:20寫道： > > > > The case you hit is s2 set in frame mask but s1 not. So you're trying to > > set s1 bit manually. > > If

Re: [PATCH] RISC-V: Fix .cfi_offset directive when push pop in zc

Pushed with minor coding style fix: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4dcd3c7749734133f7f59509b1a118f3a13de4ee On Mon, Feb 24, 2025 at 4:00 PM Kito Cheng wrote: > > Thanks, will push after verified on my hand :) > > On Mon, Feb 24, 2025 at 3:20 PM Hsing Yu

Re: [PATCH v2] RISC-V: Fix a typo in zce to zcf implication

Hi Yuriy: V2 is LGTM, thanks :) On Wed, Feb 26, 2025 at 3:06 AM Yuriy Kolerov wrote: > > Hi Jeff, > > That check is performed in a lambda function: > > {"zce", "zcf", >[] (const riscv_subset_list *subset_list) -> bool >{ > return subset_list->xlen () == 32 && subset_list->lookup (

[PATCH] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

This patch fixes the multilib_os_dir and multiarch_dir for those targets that use TARGET_COMPUTE_MULTILIB, since the TARGET_COMPUTE_MULTILIB hook only update/fix the multilib_dir but not the multilib_os_dir and multiarch_dir, so the multilib_os_dir and multiarch_dir are not set correctly for those

Re: [PATCH 1/2] Add TARGET_COMPUTE_MULTILIB_OS hook to override multi-lib-os result.

Hi Jin Ma: I realized multilib os dir is not correctly set as you described, but I think that info should just come from multilib_select rather than creating a new hook to do that, anyway I just wrote a fix...because we hit that issue last week... Hi Jeff: Here is another approach to fix that -

[PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

abi-18.c: Update test. gcc.target/riscv/rvv/base/vsetvl_zve32-1.c: New test. gcc.target/riscv/rvv/base/vsetvl_zve32-2.c: New test. Co-authored-by: Kito Cheng --- gcc/config/riscv/riscv-v.cc | 8 +- .../riscv/riscv-vector-builtins-types.def | 322 +-

[PATCH 3/8] RISC-V: Generate extension table in documentation from riscv-ext.def

Automatically build the ISA extension reference table in invoke.texi from the unified riscv-ext.def metadata, ensuring documentation stays in sync with extension definitions and reducing manual maintenance. gcc/ChangeLog: * doc/invoke.texi: Replace hand‑written extension table with

[PATCH v2 7/8] RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

This commit drops the riscv_ext_version_table and instead uses the riscv_ext_info_t data structure to provide the version information for RISC-V extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove. (standard_extensions_p): Use

[PATCH v2 1/8] RISC-V: Introduce riscv-ext*.def to define extensions

Adding a new ISA extension to RISC-V GCC requires modifying several places: 1. riscv_ext_version_table for the extension version. 2. riscv.opt for the target option and variable. 3. riscv_ext_flag_table to bind the extension to its target option. 4. riscv_combine_info if this extension is just a ma

[PATCH v2 2/8] RISC-V: Use riscv-ext.def to generate target options and variables

Leverage the centralized riscv-ext.def definitions to auto-generate the target option parsing and associated internal flags, replacing manual listings in riscv.opt; `riscv_ext_flag_table` part will remove in later patch. gcc/ChangeLog: * config/riscv/gen-riscv-ext-opt.cc: New. * c

[PATCH v2 3/8] RISC-V: Generate extension table in documentation from riscv-ext.def

Automatically build the ISA extension reference table in invoke.texi from the unified riscv-ext.def metadata, ensuring documentation stays in sync with extension definitions and reducing manual maintenance. gcc/ChangeLog: * doc/invoke.texi: Replace hand‑written extension table with

[PATCH v2 4/8] RISC-V: Adjust riscv_can_inline_p

We don't hold any extenison flags in `target_flags`, so no need to gather the extenison flags in `target_flags`. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_can_inline_p): Drop extension flags check from `target_flags`. * config/riscv/riscv-subset.h (riscv_

[PATCH v2 6/8] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

Consolidate implied-extension logic by removing the old `riscv_implied_info` array and using the `implied_exts` field in the unified riscv_ext_info_t structures generated from `riscv-ext.def`. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info::riscv_implied_

[PATCH v2 5/8] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

Define a new riscv_ext_info_t struct to aggregate all ISA extension fields (name, version, flags, implied extensions, bitmask and extra flags) generated from riscv-ext.def. Also adjust riscv_ext_flag_table_t and riscv_implied_info_t to make it able to not hold extension name, this part will refact

[PATCH v2 8/8] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

Refactor extension flag handling by removing the old riscv_ext_flag_table and sourcing all flag definitions directly from the flags field of the unified riscv_ext_info_t structures generated from riscv-ext.def. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_extra_ext_flag_tab

Re: [PATCH] RISC-V: Add augmented hypervisor series extensions.

Hehe, you are late a little bit, let rewrite this with riscv-ext.def On Tue, May 13, 2025 at 11:56 AM Jiawei wrote: > > The augmented hypervisor series extensions 'sha'[1] is a new profile-defined > extension series that captures the full set of features that are mandated to > be supported along

[PATCH] RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue

We forgot to initialize m_allow_adding_dup in the constructor of riscv_subset_list, then that will be a random value...that will lead to a random behavior of the -march may accpet duplicate extension. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::riscv_s

Re: [PATCH v2 1/8] RISC-V: Introduce riscv-ext*.def to define extensions

pushed On Mon, May 12, 2025 at 10:18 PM Kito Cheng wrote: > > I guess this patch set is not interesting to most people, so I will commit > that once CI green :P > > On Mon, May 12, 2025 at 10:17 PM Kito Cheng wrote: >> >> Adding a new ISA extension to RISC-V GCC

Re: [PATCH v2] RISC-V: Support for zilsd and zclsd extensions.

This patch is somewhat corrupt...but anyway, fixed and pushed to trunk On Thu, May 8, 2025 at 12:43 PM Dongyan Chen wrote: > > This patch support zilsd and zclsd[1] extensions. > To enable GCC to recognize and process zilsd and zclsd extension > correctly at compile time. > > [1] https://github.

Re: [PATCH v5] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

pushed to trunk, thanks :) On Mon, May 12, 2025 at 5:20 PM Dongyan Chen wrote: > > This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1]. > To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and > supm extensions correctly at compile time. > > [1]https://github.com/ris

[PATCH] RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V architecture, which allows the use of an even-odd RVC general purpose register (x8-x15) in inline asm. Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102 gcc/ChangeLog: * config/riscv/constraints.md (cR): New

[PATCH] RISC-V: Support Zilsd code gen

This commit adds the code gen support for Zilsd, which is a newly added extension for RISC-V. The Zilsd extension allows for loading and storing 64-bit values using even-odd register pairs. We only try to do miminal code gen support for that, which means only use the new instructions when the load

[committed] RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]

gcc/ChangeLog: * config/riscv/t-riscv: Drop duplicate build rule for riscv-ext.opt. --- gcc/config/riscv/t-riscv | 2 -- 1 file changed, 2 deletions(-) diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index e99d6689ba0..854daa96e73 100644 --- a/gcc/config/riscv/t-

Re: [PATCH v2 2/8] RISC-V: Use riscv-ext.def to generate target options and variables

https://gcc.gnu.org/pipermail/gcc-patches/2025-May/683671.html On Wed, May 14, 2025 at 6:58 PM Mark Wielaard wrote: > > Hi Kito, > > On Mon, May 12, 2025 at 10:17:36PM +0800, Kito Cheng wrote: > > Leverage the centralized riscv-ext.def definitions to auto-generate > >

[committed] RISC-V: Regen riscv-ext.opt.urls

gcc/ChangeLog: * config/riscv/riscv-ext.opt.urls: Regenerate. --- gcc/config/riscv/riscv-ext.opt.urls | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/config/riscv/riscv-ext.opt.urls b/gcc/config/riscv/riscv-ext.opt.urls index e69de29bb2d..c4f471079df 100644 --- a/gcc/config/ris

Re: [PATCH v3] RISC-V: Add augmented hypervisor series extensions.

Pushed, thanks :) On Tue, May 13, 2025 at 3:25 PM Jiawei wrote: > > The augmented hypervisor series extensions 'sha'[1] is a new profile-defined > extension series that captures the full set of features that are mandated to > be supported along with the 'H' extension. > > [1] > https://github.c

Re: [PATCH] RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue

pushed :) On Wed, May 14, 2025 at 9:18 PM Christoph Müllner < christoph.muell...@vrull.eu> wrote: > On Tue, May 13, 2025 at 4:34 AM Kito Cheng wrote: > > > > We forgot to initialize m_allow_adding_dup in the constructor of > > riscv_subset_list, then that will be a ra

Re: gcc project build error in Ubuntu18.04

I am surprised that such generic names are defined within the system header files, I inclined just rename that to major_version, minor_version, could you send a patch for that? On Fri, May 16, 2025 at 3:50 PM Songhe Zhu wrote: > > Hi kito > When syncing GCC to the master branch and building

Re: [PATCH] RISC-V: Add new operand constraint: cR

Committed :) On Sat, May 17, 2025 at 9:36 PM Jeff Law wrote: > > > > On 5/14/25 9:20 PM, Kito Cheng wrote: > > This commit introduces a new operand constraint `cR` for the RISC-V > > architecture, which allows the use of an even-odd RVC general purpose > > regis

Re: [PATCH] RISC-V: Support Zilsd code gen

On Sat, May 17, 2025 at 9:34 PM Jeff Law wrote: > > > > On 5/14/25 9:14 PM, Kito Cheng wrote: > > This commit adds the code gen support for Zilsd, which is a > > newly added extension for RISC-V. The Zilsd extension allows > > for loading and storing 64-bit

Re: [PATCH] RISC-V: Add zvfbfa and zvfofp8min intrinsic.

Seems like you don't really add new intrinsics for those two new extensions? Also our policy is only to add extensions when they are ratified. I am happy to review the patch anyway, but just remind you we won't accept that until it is ratified :) On Mon, Apr 14, 2025 at 4:25 PM Dongyan Chen wrot

Re: [PATCH v2] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

Hi Jin: Thanks for heads up:) Hi Jeff: I've rebased that on the trunk and everything seems right, do you think it's OK for the trunk? On Mon, May 19, 2025 at 2:35 PM Jin Ma wrote: > On Sun, 16 Mar 2025 11:23:07 -0600, Jeff Law wrote: > > > > > > On 3/

Re: [PATCH] RISC-V: Support Zilsd code gen

committed to trunk :) On Mon, May 19, 2025 at 11:49 AM Kito Cheng wrote: > On Sat, May 17, 2025 at 9:34 PM Jeff Law wrote: > > > > > > > > On 5/14/25 9:14 PM, Kito Cheng wrote: > > > This commit adds the code gen support for Zilsd, which is a > > >

Re: [PATCH v2] RISC-V: Fix the warning of temporary object dangling references.

Pushed to trunk :) On Mon, May 19, 2025 at 3:18 PM Dongyan Chen wrote: > > During the GCC compilation, some warnings about temporary object dangling > references emerged. They appeared in these code lines in riscv-common.cc: > const riscv_ext_info_t &implied_ext_info, const riscv_ext_info_t &ext

Re: [PATCH] RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc

Committed to trunk, thanks :) On Mon, May 19, 2025 at 10:44 AM Songhe Zhu wrote: > > From: zhusonghe > > The variables `major` and `minor` in `gen-riscv-ext-texi.cc` > conflict with the macros of the same name defined in ``, > which are exposed when building with newer versions of GCC on older >

Re: [PATCH v2] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

Pushed to trunk :) On Wed, May 21, 2025 at 2:35 AM Jeff Law wrote: > > > > On 5/19/25 12:48 AM, Kito Cheng wrote: > > Hi Jin: > > > > Thanks for heads up:) > > > > Hi Jeff: > > > > I've rebased that on the trunk and everything seems righ

Re: [PATCH] [RFC] RISC-V: Add extra check to help choosing multilib with equivalent arch.

I thought this issue should be fixed when we implement those implication rules correctly? Does march=rv32imaf_zca/mabi=ilp32 still not able select march=rv32imac/mabi=ilp32 still happen after this[1] patch? [1] https://github.com/gcc-mirror/gcc/commit/42ce61eaefc4db70e2e7ea2d8ef091daa458eb48 On

Re: [PATCH] RISC-V: Fix the warning of temporary object dangling references.

Hm, it really doesn't make too much sense to get that warning, but I can reproduce that when I compile with gcc 13 (and newer)...and seems like a known issue [1][2]... However I don't really like that approach, could you change the argument type of get_riscv_ext_info to `const char *` to suppr

Re: [PATCH] RISC-V: Default-initialize variable.

LGTM On Wed, May 21, 2025 at 9:49 PM Robin Dapp wrote: > > Hi, > > this patch initializes saved_vxrm_mode to VXRM_MODE_NONE. This is a > warning (but no error) when building the compiler so better fix it. > > Regtested on rv64gcv_zvl512b. Going to commit as obvious if the CI > is happy. > > Reg

Re: [PATCH] RISC-V: Support CPUs in -march.

I could imagine that is a simpler way to set the march since the march string becomes terribly long - we have an arch string more than 300 char...so I support this, although I think this should be discuss with LLVM community, but I think it's fine to accept as a GCC extension. So LGTM, go ahead to

Re: [PATCH] RISC-V: Support CPUs in -march.

On Wed, May 21, 2025 at 10:19 PM Robin Dapp wrote: > > > I could imagine that is a simpler way to set the march since the march > > string becomes terribly long - we have an arch string more than 300 > > char...so I support this, although I think this should be discuss with > > LLVM community, but

Re: [PATCH] RISC-V: Add autovec mode param.

Could you make a simple testcase that could vectorize two loops in different modes (e.g one SI and one SF) and with this param will only auto vec on loop? On Wed, May 21, 2025 at 9:47 PM Robin Dapp wrote: > > Hi, > > This patch adds a --param=autovec-mode=. When the param is > specified we make

[PATCH] RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-riscv-ext-texi

Separate the build rules to compile and link stage to make sure BUILD_LINKERFLAGS and BUILD_LDFLAGS are applied correctly. We hit this issue when we try to build GCC with non-system-default g++, and it use newer libstdc++, and then got error from using older libstdc++ from system, that should not

Re: [v3] RISC-V: Add minimal support of double trap extension 1.0

pushed to trunk :) On Thu, May 29, 2025 at 1:19 PM Jiawei wrote: > > Add support of double trap extension [1], enabling GCC > to recognize the following extensions at compile time. > > New extensions: > - ssdbltrp > - smdbltrp > > [1] > https://github.com/riscv/riscv-double-trap/releases

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