LGTM, thanks :)
Alexandre Oliva <ol...@adacore.com> 於 2025年4月15日 週二 12:25 寫道：
>
> And here's another that came up more recently:
>
> The gcc-14 backport that split the pr114194 testcase for rv32 and rv64
> would only generate the expected rv32 sequence if commit
> 6b315907c0353f71169a7555e653d29a981fef67 had also been backported, but
> it wasn't. Without it, we get the same code as before on both rv32
> and rv64, so revert to the original test.
>
> Also tested on riscv64-elf and riscv32-elf on x86_64-linux-gnu.
> Ok for gcc-14?
>
>
> for gcc/testsuite/ChangeLog
>
> PR target/118601
> * gcc.target/riscv/rvv/xtheadvector/pr114194.c: Restore.
> * gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: Remove.
> * gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: Likewise.
> ---
> .../riscv/rvv/xtheadvector/pr114194-rv32.c | 51
> ------------------
> .../riscv/rvv/xtheadvector/pr114194-rv64.c | 55
> --------------------
> .../gcc.target/riscv/rvv/xtheadvector/pr114194.c | 56
> ++++++++++++++++++++
> 3 files changed, 56 insertions(+), 106 deletions(-)
> delete mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
> delete mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
>
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
> b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
> deleted file mode 100644
> index 0bee5ec33de83..0000000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -/* { dg-do compile { target rv32 } } */
> -/* { dg-options "-march=rv32gc_xtheadvector -O2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -/*
> -** foo0_1:
> -** sb\tzero,0\([a-x0-9]+\)
> -** ret
> -*/
> -void foo0_1 (void *p)
> -{
> - __builtin_memset (p, 0, 1);
> -}
> -
> -/*
> -** foo0_7:
> -** li\t[a-x0-9]+,7
> -** th.vsetvli\tzero,[a-x0-9]+,e8,m1
> -** th\.vmv\.v\.i\tv[0-9],0
> -** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
> -** ret
> -*/
> -void foo0_7 (void *p)
> -{
> - __builtin_memset (p, 0, 7);
> -}
> -
> -/*
> -** foo1_1:
> -** li\t[a-x0-9]+,1
> -** sb\t[a-x0-9]+,0\([a-x0-9]+\)
> -** ret
> -*/
> -void foo1_1 (void *p)
> -{
> - __builtin_memset (p, 1, 1);
> -}
> -
> -/*
> -** foo1_5:
> -** li\t[a-x0-9]+,5
> -** th.vsetvli\tzero,[a-x0-9]+,e8,m1
> -** th\.vmv\.v\.i\tv[0-9],1
> -** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
> -** ret
> -*/
> -
> -void foo1_5 (void *p)
> -{
> - __builtin_memset (p, 1, 5);
> -}
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
> b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
> deleted file mode 100644
> index 84333c1cf5a7c..0000000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
> +++ /dev/null
> @@ -1,55 +0,0 @@
> -/* { dg-do compile { target rv64 } } */
> -/* { dg-options "-march=rv64gc_xtheadvector -O2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -/*
> -** foo0_1:
> -** sb\tzero,0\([a-x0-9]+\)
> -** ret
> -*/
> -void foo0_1 (void *p)
> -{
> - __builtin_memset (p, 0, 1);
> -}
> -
> -/*
> -** foo0_7:
> -** sb\tzero,0\([a-x0-9]+\)
> -** sb\tzero,1\([a-x0-9]+\)
> -** sb\tzero,2\([a-x0-9]+\)
> -** sb\tzero,3\([a-x0-9]+\)
> -** sb\tzero,4\([a-x0-9]+\)
> -** sb\tzero,5\([a-x0-9]+\)
> -** sb\tzero,6\([a-x0-9]+\)
> -** ret
> -*/
> -void foo0_7 (void *p)
> -{
> - __builtin_memset (p, 0, 7);
> -}
> -
> -/*
> -** foo1_1:
> -** li\t[a-x0-9]+,1
> -** sb\t[a-x0-9]+,0\([a-x0-9]+\)
> -** ret
> -*/
> -void foo1_1 (void *p)
> -{
> - __builtin_memset (p, 1, 1);
> -}
> -
> -/*
> -** foo1_5:
> -** li\t[a-x0-9]+,1
> -** sb\t[a-x0-9]+,0\([a-x0-9]+\)
> -** sb\t[a-x0-9]+,1\([a-x0-9]+\)
> -** sb\t[a-x0-9]+,2\([a-x0-9]+\)
> -** sb\t[a-x0-9]+,3\([a-x0-9]+\)
> -** sb\t[a-x0-9]+,4\([a-x0-9]+\)
> -** ret
> -*/
> -void foo1_5 (void *p)
> -{
> - __builtin_memset (p, 1, 5);
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
> b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
> new file mode 100644
> index 0000000000000..2e53a7ecc3e71
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
> @@ -0,0 +1,56 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** foo0_1:
> +** sb\tzero,0\([a-x0-9]+\)
> +** ret
> +*/
> +void foo0_1 (void *p)
> +{
> + __builtin_memset (p, 0, 1);
> +}
> +
> +/*
> +** foo0_7:
> +** sb\tzero,0\([a-x0-9]+\)
> +** sb\tzero,1\([a-x0-9]+\)
> +** sb\tzero,2\([a-x0-9]+\)
> +** sb\tzero,3\([a-x0-9]+\)
> +** sb\tzero,4\([a-x0-9]+\)
> +** sb\tzero,5\([a-x0-9]+\)
> +** sb\tzero,6\([a-x0-9]+\)
> +** ret
> +*/
> +void foo0_7 (void *p)
> +{
> + __builtin_memset (p, 0, 7);
> +}
> +
> +/*
> +** foo1_1:
> +** li\t[a-x0-9]+,1
> +** sb\t[a-x0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void foo1_1 (void *p)
> +{
> + __builtin_memset (p, 1, 1);
> +}
> +
> +/*
> +** foo1_5:
> +** li\t[a-x0-9]+,1
> +** sb\t[a-x0-9]+,0\([a-x0-9]+\)
> +** sb\t[a-x0-9]+,1\([a-x0-9]+\)
> +** sb\t[a-x0-9]+,2\([a-x0-9]+\)
> +** sb\t[a-x0-9]+,3\([a-x0-9]+\)
> +** sb\t[a-x0-9]+,4\([a-x0-9]+\)
> +** ret
> +*/
> +void foo1_5 (void *p)
> +{
> + __builtin_memset (p, 1, 5);
> +}
>
>
> --
> Alexandre Oliva, happy hacker https://blog.lx.oliva.nom.br/
> Free Software Activist FSFLA co-founder GNU Toolchain Engineer
> More tolerance and less prejudice are key for inclusion and diversity.
> Excluding neuro-others for not behaving ""normal"" is *not* inclusive!
>
