sorry for my stupid mistake, forgot v2, it's just same as v1 and see v3
On Mon, Dec 23, 2024 at 11:15 PM Kito Cheng <kito.ch...@sifive.com> wrote:
>
> ---
> gcc/config/riscv/autovec-opt.md | 16 ++--
> gcc/config/riscv/autovec.md | 30 +++----
> gcc/config/riscv/riscv-v.cc | 4 +-
> gcc/config/riscv/vector-iterators.md | 46 +++++++++++
> gcc/config/riscv/vector.md | 118 +++++++++++++++++++++++++++
> 5 files changed, 189 insertions(+), 25 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 645dc53d868..4704bf342e3 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -810,7 +810,7 @@
> "&& 1"
> [(const_int 0)]
> {
> - riscv_vector::expand_reduction (<WREDUC_UNSPEC>, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (<WREDUC_UNSPEC_AV>,
> riscv_vector::REDUCE_OP,
> operands,
> CONST0_RTX (<V_DOUBLE_EXTEND_VEL>mode));
> DONE;
> @@ -829,7 +829,7 @@
> "&& 1"
> [(const_int 0)]
> {
> - riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
> + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED_AV,
> riscv_vector::REDUCE_OP_FRM_DYN,
> operands,
> CONST0_RTX (<V_DOUBLE_EXTEND_VEL>mode));
> @@ -850,7 +850,7 @@
> "&& 1"
> [(const_int 0)]
> {
> - riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
> + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED_AV,
> riscv_vector::REDUCE_OP_FRM_DYN,
> operands, operands[2]);
> DONE;
> @@ -878,7 +878,7 @@
> else
> {
> rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
> - riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
> + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED_AV,
> riscv_vector::REDUCE_OP_M_FRM_DYN,
> ops, operands[1]);
> }
> @@ -1226,7 +1226,7 @@
> {
> rtx ops[] = {operands[0], operands[2], operands[1],
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> - riscv_vector::expand_reduction (<WREDUC_UNSPEC>,
> + riscv_vector::expand_reduction (<WREDUC_UNSPEC_AV>,
> riscv_vector::REDUCE_OP_M,
> ops, CONST0_RTX
> (<V_DOUBLE_EXTEND_VEL>mode));
> DONE;
> @@ -1281,7 +1281,7 @@
> [(const_int 0)]
> {
> rtx ops[] = {operands[0], operands[3], operands[1], operands[2]};
> - riscv_vector::expand_reduction (<WREDUC_UNSPEC>,
> + riscv_vector::expand_reduction (<WREDUC_UNSPEC_AV>,
> riscv_vector::REDUCE_OP_M,
> ops, CONST0_RTX
> (<V_DOUBLE_EXTEND_VEL>mode));
> DONE;
> @@ -1317,7 +1317,7 @@
> {
> rtx ops[] = {operands[0], operands[2], operands[1],
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> - riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
> + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED_AV,
> riscv_vector::REDUCE_OP_M_FRM_DYN,
> ops, CONST0_RTX
> (<V_DOUBLE_EXTEND_VEL>mode));
> DONE;
> @@ -1372,7 +1372,7 @@
> [(const_int 0)]
> {
> rtx ops[] = {operands[0], operands[3], operands[1], operands[2]};
> - riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
> + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED_AV,
> riscv_vector::REDUCE_OP_M_FRM_DYN,
> ops, CONST0_RTX
> (<V_DOUBLE_EXTEND_VEL>mode));
> DONE;
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 8d30ab22186..4432b7d1d05 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2097,7 +2097,7 @@
> "&& 1"
> [(const_int 0)]
> {
> - riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_AV,
> riscv_vector::REDUCE_OP,
> operands, CONST0_RTX (<VEL>mode));
> DONE;
> }
> @@ -2110,7 +2110,7 @@
> {
> int prec = GET_MODE_PRECISION (<VEL>mode);
> rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX_AV,
> riscv_vector::REDUCE_OP,
> operands, min);
> DONE;
> })
> @@ -2120,7 +2120,7 @@
> (match_operand:V_VLSI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU_AV,
> riscv_vector::REDUCE_OP,
> operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2132,7 +2132,7 @@
> {
> int prec = GET_MODE_PRECISION (<VEL>mode);
> rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN_AV,
> riscv_vector::REDUCE_OP,
> operands, max);
> DONE;
> })
> @@ -2144,7 +2144,7 @@
> {
> int prec = GET_MODE_PRECISION (<VEL>mode);
> rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MINU_AV,
> riscv_vector::REDUCE_OP,
> operands, max);
> DONE;
> })
> @@ -2154,7 +2154,7 @@
> (match_operand:V_VLSI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (UNSPEC_REDUC_AND, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_AND_AV,
> riscv_vector::REDUCE_OP,
> operands, CONSTM1_RTX (<VEL>mode));
> DONE;
> })
> @@ -2164,7 +2164,7 @@
> (match_operand:V_VLSI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (UNSPEC_REDUC_OR, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_OR_AV,
> riscv_vector::REDUCE_OP,
> operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2174,7 +2174,7 @@
> (match_operand:V_VLSI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_XOR_AV,
> riscv_vector::REDUCE_OP,
> operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2198,7 +2198,7 @@
> "&& 1"
> [(const_int 0)]
> {
> - riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED_AV,
> riscv_vector::REDUCE_OP_FRM_DYN,
> operands, CONST0_RTX (<VEL>mode));
> DONE;
> @@ -2213,7 +2213,7 @@
> REAL_VALUE_TYPE rv;
> real_inf (&rv, true);
> rtx f = const_double_from_real_value (rv, <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX_AV,
> riscv_vector::REDUCE_OP,
> operands, f);
> DONE;
> })
> @@ -2226,7 +2226,7 @@
> REAL_VALUE_TYPE rv;
> real_inf (&rv, false);
> rtx f = const_double_from_real_value (rv, <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN_AV,
> riscv_vector::REDUCE_OP,
> operands, f);
> DONE;
> })
> @@ -2239,7 +2239,7 @@
> REAL_VALUE_TYPE rv;
> real_inf (&rv, true);
> rtx f = const_double_from_real_value (rv, <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX_AV,
> riscv_vector::REDUCE_OP,
> operands, f);
> DONE;
> })
> @@ -2252,7 +2252,7 @@
> REAL_VALUE_TYPE rv;
> real_inf (&rv, false);
> rtx f = const_double_from_real_value (rv, <VEL>mode);
> - riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, riscv_vector::REDUCE_OP,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN_AV,
> riscv_vector::REDUCE_OP,
> operands, f);
> DONE;
> })
> @@ -2277,7 +2277,7 @@
> [(const_int 0)]
> {
> rtx ops[] = {operands[0], operands[2]};
> - riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED_AV,
> riscv_vector::REDUCE_OP_FRM_DYN,
> ops, operands[1]);
> DONE;
> @@ -2304,7 +2304,7 @@
> else
> {
> rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
> - riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED_AV,
> riscv_vector::REDUCE_OP_M_FRM_DYN,
> ops, operands[1]);
> }
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 814c5febabe..a6996964332 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4160,13 +4160,13 @@ expand_reduction (unsigned unspec, unsigned
> insn_flags, rtx *ops, rtx init)
> rtx scalar_move_ops[] = {m1_tmp, init};
> insn_code icode = code_for_pred_broadcast (m1_mode);
> if (need_mask_operand_p (insn_flags))
> - emit_nonvlmax_insn (icode, SCALAR_MOVE_OP, scalar_move_ops, ops[3]);
> + emit_nonvlmax_insn (icode, SCALAR_MOVE_OP, scalar_move_ops, gen_int_mode
> (1, Pmode));
> else
> emit_vlmax_insn (icode, SCALAR_MOVE_OP, scalar_move_ops);
>
> rtx m1_tmp2 = gen_reg_rtx (m1_mode);
> rtx reduc_ops[] = {m1_tmp2, vector_src, m1_tmp};
> - icode = code_for_pred (unspec, vmode);
> + icode = code_for_pred_av (unspec, vmode);
>
> if (need_mask_operand_p (insn_flags))
> {
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index e9da26b95d6..76ca07bd73d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -88,8 +88,11 @@
> ;; Integer and Float Reduction
> UNSPEC_REDUC
> UNSPEC_REDUC_SUM
> + UNSPEC_REDUC_SUM_AV
> UNSPEC_REDUC_SUM_ORDERED
> UNSPEC_REDUC_SUM_UNORDERED
> + UNSPEC_REDUC_SUM_ORDERED_AV
> + UNSPEC_REDUC_SUM_UNORDERED_AV
> UNSPEC_REDUC_MAXU
> UNSPEC_REDUC_MAX
> UNSPEC_REDUC_MINU
> @@ -97,11 +100,23 @@
> UNSPEC_REDUC_AND
> UNSPEC_REDUC_OR
> UNSPEC_REDUC_XOR
> + UNSPEC_REDUC_MAXU_AV
> + UNSPEC_REDUC_MAX_AV
> + UNSPEC_REDUC_MINU_AV
> + UNSPEC_REDUC_MIN_AV
> + UNSPEC_REDUC_AND_AV
> + UNSPEC_REDUC_OR_AV
> + UNSPEC_REDUC_XOR_AV
> +
>
> UNSPEC_WREDUC_SUM
> UNSPEC_WREDUC_SUMU
> + UNSPEC_WREDUC_SUM_AV
> + UNSPEC_WREDUC_SUMU_AV
> UNSPEC_WREDUC_SUM_ORDERED
> UNSPEC_WREDUC_SUM_UNORDERED
> + UNSPEC_WREDUC_SUM_ORDERED_AV
> + UNSPEC_WREDUC_SUM_UNORDERED_AV
> ])
>
> (define_c_enum "unspecv" [
> @@ -1596,32 +1611,61 @@
> UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
> ])
>
> +(define_int_iterator ANY_REDUC_AV [
> + UNSPEC_REDUC_SUM_AV UNSPEC_REDUC_MAXU_AV UNSPEC_REDUC_MAX_AV
> UNSPEC_REDUC_MINU_AV
> + UNSPEC_REDUC_MIN_AV UNSPEC_REDUC_AND_AV UNSPEC_REDUC_OR_AV
> UNSPEC_REDUC_XOR_AV
> +])
> +
> +
> (define_int_iterator ANY_WREDUC [
> UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
> ])
>
> +(define_int_iterator ANY_WREDUC_AV [
> + UNSPEC_WREDUC_SUM_AV UNSPEC_WREDUC_SUMU_AV
> +])
> +
> (define_int_iterator ANY_FREDUC [
> UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
> ])
>
> +(define_int_iterator ANY_FREDUC_AV [
> + UNSPEC_REDUC_MAX_AV UNSPEC_REDUC_MIN_AV
> +])
> +
> (define_int_iterator ANY_FREDUC_SUM [
> UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
> ])
>
> +(define_int_iterator ANY_FREDUC_SUM_AV [
> + UNSPEC_REDUC_SUM_ORDERED_AV UNSPEC_REDUC_SUM_UNORDERED_AV
> +])
> +
> (define_int_iterator ANY_FWREDUC_SUM [
> UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
> ])
>
> +(define_int_iterator ANY_FWREDUC_SUM_AV [
> + UNSPEC_WREDUC_SUM_ORDERED_AV UNSPEC_WREDUC_SUM_UNORDERED_AV
> +])
> +
> (define_int_attr reduc_op [
> (UNSPEC_REDUC_SUM "redsum")
> + (UNSPEC_REDUC_SUM_AV "redsum")
> (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
> + (UNSPEC_REDUC_SUM_ORDERED_AV "redosum") (UNSPEC_REDUC_SUM_UNORDERED_AV
> "redusum")
> (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax")
> (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
> + (UNSPEC_REDUC_MAXU_AV "redmaxu") (UNSPEC_REDUC_MAX_AV "redmax")
> (UNSPEC_REDUC_MINU_AV "redminu") (UNSPEC_REDUC_MIN_AV "redmin")
> (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR
> "redxor")
> + (UNSPEC_REDUC_AND_AV "redand") (UNSPEC_REDUC_OR_AV "redor")
> (UNSPEC_REDUC_XOR_AV "redxor")
> (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
> + (UNSPEC_WREDUC_SUM_AV "wredsum") (UNSPEC_WREDUC_SUMU_AV "wredsumu")
> (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED
> "wredusum")
> + (UNSPEC_WREDUC_SUM_ORDERED_AV "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED_AV
> "wredusum")
> ])
>
> (define_code_attr WREDUC_UNSPEC [(zero_extend "UNSPEC_WREDUC_SUMU")
> (sign_extend "UNSPEC_WREDUC_SUM")])
> +(define_code_attr WREDUC_UNSPEC_AV [(zero_extend "UNSPEC_WREDUC_SUMU_AV")
> (sign_extend "UNSPEC_WREDUC_SUM_AV")])
>
> (define_mode_attr VINDEX [
> (RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI
> "RVVM1QI")
> @@ -3516,6 +3560,8 @@
> (UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
> (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
> (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
> + (UNSPEC_REDUC_SUM_ORDERED_AV "o") (UNSPEC_REDUC_SUM_UNORDERED_AV "u")
> + (UNSPEC_WREDUC_SUM_ORDERED_AV "o") (UNSPEC_WREDUC_SUM_UNORDERED_AV "u")
> ])
>
> (define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u")
> (UNSPEC_VMULHSU "su")
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index d0b135c755f..e9d15237706 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -7985,6 +7985,28 @@
> [(set_attr "type" "vired")
> (set_attr "mode" "<MODE>")])
>
> +;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs), but for
> auto vectorizer
> +(define_insn "@pred_av_<reduc_op><mode>"
> + [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr")
> + (unspec:<V_LMUL1>
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
> + (match_operand 5 "vector_length_operand" " rK")
> + (match_operand 6 "const_int_operand" " i")
> + (match_operand 7 "const_int_operand" " i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_LMUL1> [
> + (match_operand:V_VLSI 3 "register_operand" " vr")
> + (match_operand:<V_LMUL1> 4 "register_operand" " vr")
> + ] ANY_REDUC_AV)
> + (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu")]
> UNSPEC_REDUC))]
> + "TARGET_VECTOR"
> + "v<reduc_op>.vs\t%0,%3,%4%p1"
> + [(set_attr "type" "vired")
> + (set_attr "mode" "<MODE>")])
> +
> +
> ;; Integer Widen Reduction Sum (vwredsum[u].vs)
> (define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr,
> vr")
> @@ -8006,6 +8028,28 @@
> [(set_attr "type" "viwred")
> (set_attr "mode" "<MODE>")])
>
> +;; Integer Widen Reduction Sum (vwredsum[u].vs), but for auto vectorizer
> +(define_insn "@pred_av_<reduc_op><mode>"
> + [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr")
> + (unspec:<V_EXT_LMUL1>
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
> + (match_operand 5 "vector_length_operand" " rK")
> + (match_operand 6 "const_int_operand" " i")
> + (match_operand 7 "const_int_operand" " i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_EXT_LMUL1> [
> + (match_operand:VI_QHS 3 "register_operand" " vr")
> + (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr")
> + ] ANY_WREDUC_AV)
> + (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" "
> vu")] UNSPEC_REDUC))]
> + "TARGET_VECTOR"
> + "v<reduc_op>.vs\t%0,%3,%4%p1"
> + [(set_attr "type" "viwred")
> + (set_attr "mode" "<MODE>")])
> +
> +
> ;; Float Reduction (vfred(max|min).vs)
> (define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,
> vr")
> @@ -8027,6 +8071,28 @@
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
>
> +;; Float Reduction (vfred(max|min).vs), but for auto vectorizer
> +(define_insn "@pred_av_<reduc_op><mode>"
> + [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr")
> + (unspec:<V_LMUL1>
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
> + (match_operand 5 "vector_length_operand" " rK")
> + (match_operand 6 "const_int_operand" " i")
> + (match_operand 7 "const_int_operand" " i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_LMUL1> [
> + (match_operand:V_VLSF 3 "register_operand" " vr")
> + (match_operand:<V_LMUL1> 4 "register_operand" " vr")
> + ] ANY_FREDUC_AV)
> + (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu")]
> UNSPEC_REDUC))]
> + "TARGET_VECTOR"
> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
> + [(set_attr "type" "vfredu")
> + (set_attr "mode" "<MODE>")])
> +
> +
> ;; Float Reduction Sum (vfred[ou]sum.vs)
> (define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_LMUL1> 0 "register_operand"
> "=vr,vr")
> @@ -8052,6 +8118,32 @@
> (set (attr "frm_mode")
> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> +;; Float Reduction Sum (vfred[ou]sum.vs), but for auto vectorizer
> +(define_insn "@pred_av_<reduc_op><mode>"
> + [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr")
> + (unspec:<V_LMUL1>
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
> + (match_operand 5 "vector_length_operand" " rK")
> + (match_operand 6 "const_int_operand" " i")
> + (match_operand 7 "const_int_operand" " i")
> + (match_operand 8 "const_int_operand" " i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_LMUL1> [
> + (match_operand:V_VLSF 3 "register_operand" " vr")
> + (match_operand:<V_LMUL1> 4 "register_operand" " 0")
> + ] ANY_FREDUC_SUM_AV)
> + (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu")]
> UNSPEC_REDUC))]
> + "TARGET_VECTOR"
> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
> + [(set_attr "type" "vfred<order>")
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
> +
> +
> ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
> (define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr,
> vr")
> @@ -8077,6 +8169,32 @@
> (set (attr "frm_mode")
> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> +;; Float Widen Reduction Sum (vfwred[ou]sum.vs), but for auto vectorizer
> +(define_insn "@pred_av_<reduc_op><mode>"
> + [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr")
> + (unspec:<V_EXT_LMUL1>
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
> + (match_operand 5 "vector_length_operand" " rK")
> + (match_operand 6 "const_int_operand" " i")
> + (match_operand 7 "const_int_operand" " i")
> + (match_operand 8 "const_int_operand" " i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_EXT_LMUL1> [
> + (match_operand:VF_HS 3 "register_operand" " vr")
> + (match_operand:<V_EXT_LMUL1> 4 "register_operand" " 0")
> + ] ANY_FWREDUC_SUM)
> + (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" "
> vu")] UNSPEC_REDUC))]
> + "TARGET_VECTOR"
> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
> + [(set_attr "type" "vfwred<order>")
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
> +
> +
> ;;
> -------------------------------------------------------------------------------
> ;; ---- Predicated permutation operations
> ;;
> -------------------------------------------------------------------------------
> --
> 2.34.1
>
