On Thu, Apr 10, 2025 at 9:12 PM Jesse Huang <jesse.hu...@sifive.com> wrote:
>
> Codegen is incorrectly emitting a ".p2align 3" that coerces the
> alignment of the .note.gnu.property section from 4 to 8 on rv32.
> ---
> gcc/config/riscv/riscv.cc | 2 +-
> gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c | 12 ++++++++++++
> 3 files changed, 25 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 38f3ae7cd84..d3656a7a430 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10382,7 +10382,7 @@ riscv_file_end ()
> fprintf (asm_out_file, "1:\n");
>
> /* pr_type. */
> - fprintf (asm_out_file, "\t.p2align\t3\n");
> + fprintf (asm_out_file, "\t.p2align\t%u\n", p2align);
> fprintf (asm_out_file, "2:\n");
> fprintf (asm_out_file, "\t.long\t0xc0000000\n");
> /* pr_datasz. */
> diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
> b/gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
> new file mode 100644
> index 00000000000..d0c01d8cb99
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32g_zicfiss -fcf-protection=return -mabi=ilp32d "
> { target { rv32 } } } */
> +/* { dg-options "-march=rv32gc_zicfiss -fcf-protection=return -mabi=ilp32d "
> { target { rv32 } } } */
> +/* { dg-options "-march=rv32g_zicfilp -fcf-protection=branch -mabi=ilp32d "
> { target { rv32 } } } */
> +/* { dg-options "-march=rv32gc_zicfilp -fcf-protection=branch -mabi=ilp32d "
> { target { rv32 } } } */
> +/* { dg-options "-march=rv32g_zicfiss_zicfilp -fcf-protection=full
> -mabi=ilp32d " { target { rv32 } } } */
> +/* { dg-options "-march=rv32gc_zicfiss_zicfilp -fcf-protection=full
> -mabi=ilp32d " { target { rv32 } } } */
^^^^ GCC can only specify only one set of option...so just one
dg-options is enough, also { target { rv32 } } is not needed.
> +
> +void foo() {}
> +
> +/* { dg-final { scan-assembler-times ".p2align\t2" 3 } } */
> +/* { dg-final { scan-assembler-not ".p2align\t3" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c
> b/gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c
> new file mode 100644
> index 00000000000..25847ba410a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64g_zicfiss -fcf-protection=return -mabi=lp64d " {
> target { rv64 } } } */
> +/* { dg-options "-march=rv64gc_zicfiss -fcf-protection=return -mabi=lp64d "
> { target { rv64 } } } */
> +/* { dg-options "-march=rv64g_zicfilp -fcf-protection=branch -mabi=lp64d " {
> target { rv64 } } } */
> +/* { dg-options "-march=rv64gc_zicfilp -fcf-protection=branch -mabi=lp64d "
> { target { rv64 } } } */
> +/* { dg-options "-march=rv64g_zicfiss_zicfilp -fcf-protection=full
> -mabi=lp64d " { target { rv64 } } } */
> +/* { dg-options "-march=rv64gc_zicfiss_zicfilp -fcf-protection=full
> -mabi=lp64d " { target { rv64 } } } */
^^^ Same here
> +
> +void foo() {}
> +
> +/* { dg-final { scan-assembler-times ".p2align\t3" 3 } } */
> +/* { dg-final { scan-assembler-not ".p2align\t2" } } */
> --
> 2.39.3
>
