On 5/3/23 13:41, Aldy Hernandez wrote:
[Andrew, since you suggested this, is this what you had in mind?].
Pushed. You can comment when you're back from vacation :).
Aldy
The equal_p method in vrange_storage is only used to compare ranges
that are the same type. No sense passing the type if
On 5/5/23 22:53, Jakub Jelinek wrote:
Hi!
Similarly to the earlier sqrt patch, this patch attempts to improve
sin/cos ranges. As the functions are periodic, for the reverse range
there is not much we can do (but I've discovered I forgot to take
into account the boundary ulps for the discover
On Fri, May 05, 2023 at 08:41:48PM -0700, Jerry D via Fortran wrote:
> The attached patch adds a check for the invalid comma and emits a runtime
> error if -std=f95,f2003,f2018 are specified at compile time.
>
> Attached patch includes a new test case.
>
> Regression tested on x86_64-linux-gnu.
>
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in
function arg
The attached patch adds a check for the invalid comma and emits a
runtime error if -std=f95,f2003,f2018 are specified at compile time.
Attached patch includes a new test case.
Regression tested on x86_64-linux-gnu.
OK for mainline?
Regards,
Jerry
Author: Jerry DeLisle
Date: Fri May 5 20:
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Croatian team of translators. The file is available at:
https://translationproject.org/latest/gcc/hr.po
(This file, 'gcc-13.1.0.hr.po', has j
Picked all changes mentioned in previous to single patch as attachment. Please
help to review if any mistake.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, May 6, 2023 10:20 AM
To: Kito Cheng
Cc: juzhe.zh...@rivai.ai; rguenther ; richard.sandiford
; jeffreyalaw ; gcc-patches
Thanks, committed to trunk!
On Fri, May 5, 2023 at 10:13 PM wrote:
>
> From: Juzhe-Zhong
>
> This patch is fixing my recent optimization patch:
> https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
>
> In that patch, the new_info = parse_insn (i) is not correct.
> S
Yes, that makes sense, will have a try and keep you posted.
Pan
-Original Message-
From: Kito Cheng
Sent: Saturday, May 6, 2023 10:19 AM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; rguenther ; richard.sandiford
; jeffreyalaw ; gcc-patches
; palmer ; jakub
Subject: Re: Re: [PATCH] machine
I think x86 first? The major thing we want to make sure is that this
change won't affect those targets which do not really require 16 bit
machine_mode too much.
On Sat, May 6, 2023 at 10:12 AM Li, Pan2 via Gcc-patches
wrote:
>
> Sure thing, I will pick them all together and trigger(will send out
Sure thing, I will pick them all together and trigger(will send out the overall
diff before start to make sure my understand is correct) the test again. BTW
which target do we prefer first? X86 or RISC-V.
Pan
From: juzhe.zh...@rivai.ai
Sent: Saturday, May 6, 2023 10:00 AM
To: kito.cheng ; Li,
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
> new file mode 100644
> index 000..6384888dd03
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_
Yeah, you should also swap mode and code in rtx_def according to Richard
suggestion
since it will not change the rtx_def data structure.
I think the only problem is the mode in tree data structure.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-06 09:53
To: Li, Pan2
CC: Richard Biener; 钟
Hi Pan:
Could you try to apply the following diff and measure again? This
makes tree_type_common size unchanged.
sizeof tree_type_common= 128 (mode = 8 bit)
sizeof tree_type_common= 136 (mode = 16 bit)
sizeof tree_type_common= 128 (mode = 8 bit w/ this diff)
diff --git a/gcc/tree-core.h b/gcc/t
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in
function arg
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in
function arg
Yes, totally agree the number cannot be very accurate up to a point. Update the
correlated memory bytes allocated for the X86 target.
Bytes allocated with O2:
-
Benchmark | upstream
On 5/4/23 11:08, Raphael Moreira Zinsly wrote:
When (a & (1 << bit_no)) is tested inside an IF we can use a bit extract.
gcc/ChangeLog:
* config/riscv/bitmanip.md
(bext): Rename one to avoid name clash.
(branch_bext): New split pattern.
Unfortunately, doesn't cause a performance improvement for coremark,
but happens a few times in newlib, just enough to affect coremark
0.01% by size (or 4 bytes, and three cycles (__fwalk_sglue and
__vfiprintf_r each two bytes).
gcc:
* config/cris/cris.md (splitop): Add PLUS.
* con
While moves of constants into registers are separately
optimizable, a combination of a move with a subsequent "and"
is slightly preferable even if the move can be generated
with the same number (and timing) of insns, as moves of
"just" registers are eliminated now and then in different
passes, loos
Hi, Richards. I would like to give more information about this patch so that it
will make this patch easier for you to review.
Currently, I saw we have 3 situations that we need to handle in case of loop
control IV in auto-vectorization:
1. Single rgroup loop control (ncopies == 1 && vec_num ==
On 5/3/23 23:49, guojiufu wrote:
Hi,
On 2023-05-01 03:00, Jeff Law wrote:
On 3/16/23 21:39, Jiufu Guo wrote:
Hi,
When assigning a parameter to a variable, or assigning a variable to
return value with struct type, and the parameter/return is passed
through registers.
For this kind of case,
On 5/3/23 21:25, liuhongt wrote:
Here's update patch with documents in md.texi.
Ok for trunk?
--
Use swap_communattive_operands_p for canonicalization. When both value
has same operand precedence value, then first bit in the mask should
select first operand.
The canonicalization
On 5/5/23 14:46, Jakub Jelinek wrote:
On Fri, May 05, 2023 at 03:37:47PM +, Tamar Christina wrote:
2023-05-05 Jakub Jelinek
* Makefile.in (check_p_numbers): Rename to one_to_, move
earlier with helper variables also renamed.
(MATCH_SPLUT_SEQ): Use $(wordlis
On 4/19/23 03:57, Jin Ma wrote:
This patch adds the 'Zfa' extension for riscv, which is based on:
https://github.com/riscv/riscv-isa-manual/commits/zfb
https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da
The binutils-gdb for 'Zfa' extension:
htt
Observed after opsplit1 with AND in libgcc floating-point
functions, like the first spottings of opsplit1/AND
opportunities. Two patterns are nominally needed, as the
peephole2 optimizer continues from the *first replacement*
insn, not from a minimum context for general matching; one
that includes
On Fri, May 05, 2023 at 02:42:38PM -0700, Hans Boehm wrote:
> I think A.6-tso also needs to change the last line in the table from
> lr.aqrl ... sc to lr.aq ... sc.rl, otherwise I think we have problems with
> a subsequent A.7-tso generated l.aq . Otherwise I agree.
Indeed! Thanks for the correct
On Fri, May 5, 2023 at 2:42 PM Hans Boehm wrote:
>
> I think A.6-tso also needs to change the last line in the table from lr.aqrl
> ... sc to lr.aq ... sc.rl, otherwise I think we have problems with a
> subsequent A.7-tso generated l.aq . Otherwise I agree.
>
> I certainly agree that, given the
I think A.6-tso also needs to change the last line in the table from
lr.aqrl ... sc to lr.aq ... sc.rl, otherwise I think we have problems with
a subsequent A.7-tso generated l.aq . Otherwise I agree.
I certainly agree that, given the Ztso extension, there should be a
standard compiler-implemented
On Thu, May 04, 2023 at 02:29:34PM -0500, Peter Bergner wrote:
> I'd like to pull in Dan's upstream libffi commit into trunk to fix a
> wrong code bug/testsuite failure on powerpc64le-linux with long double
> defaulting to ieee128. This passed bootstrap and regtesting with no
> regressions. Ok fo
On 5/4/23 2:29 PM, Peter Bergner wrote:
> I'd like to pull in Dan's upstream libffi commit into trunk to fix a
> wrong code bug/testsuite failure on powerpc64le-linux with long double
> defaulting to ieee128. This passed bootstrap and regtesting with no
> regressions. Ok for trunk?
>
> This bug
Hi!
Similarly to the earlier sqrt patch, this patch attempts to improve
sin/cos ranges. As the functions are periodic, for the reverse range
there is not much we can do (but I've discovered I forgot to take
into account the boundary ulps for the discovery of impossible result
ranges). For fold_r
On Fri, May 05, 2023 at 03:37:47PM +, Tamar Christina wrote:
> > 2023-05-05 Jakub Jelinek
> >
> > * Makefile.in (check_p_numbers): Rename to one_to_, move
> > earlier with helper variables also renamed.
> > (MATCH_SPLUT_SEQ): Use $(wordlist 1,$(NUM_MATCH_SPLITS),$(one_to_999
On Fri, May 05, 2023 at 12:18:12PM -0700, Palmer Dabbelt wrote:
> On Fri, 05 May 2023 11:55:31 PDT (-0700), Andrea Parri wrote:
> > On Fri, May 05, 2023 at 10:12:56AM -0700, Patrick O'Neill wrote:
> > > The RISC-V Ztso extension currently has no effect on generated code.
> > > With the additional o
Hi Mikael,
On 5/5/23 13:43, Mikael Morin wrote:
Hello,
Le 01/05/2023 à 18:29, Harald Anlauf via Fortran a écrit :
+/* Given two expressions, check that their rank is conformable, i.e.
either
+ both have the same rank or at least one is a scalar. */
+
+bool
+gfc_op_rank_conformable (gfc_ex
On Fri, 05 May 2023 11:55:31 PDT (-0700), Andrea Parri wrote:
On Fri, May 05, 2023 at 10:12:56AM -0700, Patrick O'Neill wrote:
The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized atomic mappi
On Fri, May 05, 2023 at 10:12:56AM -0700, Patrick O'Neill wrote:
> The RISC-V Ztso extension currently has no effect on generated code.
> With the additional ordering constraints guarenteed by Ztso, we can emit
> more optimized atomic mappings than the RVWMO mappings.
>
> This patch implements And
On 5/5/23 13:36, Patrick Palka wrote:
This extends the PR93107 fix, which made us do resolve_nondeduced_context
on the elements of an initializer list during auto deduction, to happen
for CTAD as well.
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?
PR c+
On 5/5/23 14:30, Patrick Palka wrote:
On Fri, 5 May 2023, Patrick Palka wrote:
Here we're neglecting to propagate parenthesized-ness when the member
access expression (this->m) resolves to a static member (and thus
finish_class_member_access_expr yields a VAR_DECL instead of a
COMPONENT_REF).
On Fri, 5 May 2023, Patrick Palka wrote:
> Here we're neglecting to propagate parenthesized-ness when the member
> access expression (this->m) resolves to a static member (and thus
> finish_class_member_access_expr yields a VAR_DECL instead of a
> COMPONENT_REF).
>
> Bootstrapped and regtested on
> -Original Message-
> From: Alexander Monakov
> Sent: Friday, May 5, 2023 7:22 PM
> To: Tamar Christina
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] Makefile.in: clean up match.pd-related dependencies
>
>
> On Fri, 5 May 2023, Tamar Christina wrote:
>
> > > --
Here we're neglecting to propagate parenthesized-ness when the member
access expression (this->m) resolves to a static member (and thus
finish_class_member_access_expr yields a VAR_DECL instead of a
COMPONENT_REF).
Bootstrapped and regtested on x86_64-pc-linux-gnu, does look OK for
trunk?
On Fri, 5 May 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Alexander Monakov
> > Sent: Friday, May 5, 2023 6:59 PM
> > To: Tamar Christina
> > Cc: Richard Biener ; gcc-patches@gcc.gnu.org
> > Subject: RE: [PATCH] Makefile.in: clean up match.pd-related dependencies
> >
On 5/5/23 13:36, Patrick Palka wrote:
It seems DR 2256 permitted goto to cross the initialization of a
trivially initialized object with a non-trivial destructor. We
already supported this as an -fpermissive extension, so this patch
just makes us unconditionally support this.
Bootstrapped and r
> -Original Message-
> From: Alexander Monakov
> Sent: Friday, May 5, 2023 6:59 PM
> To: Tamar Christina
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] Makefile.in: clean up match.pd-related dependencies
>
>
> On Fri, 5 May 2023, Tamar Christina wrote:
>
> > > >
On Fri, 5 May 2023, Tamar Christina wrote:
> > > Am 05.05.2023 um 19:03 schrieb Alexander Monakov via Gcc-patches > patc...@gcc.gnu.org>:
> > >
> > > Clean up confusing changes from the recent refactoring for parallel
> > > match.pd build.
> > >
> > > gimple-match-head.o is not built. Remove r
On Fri, May 05, 2023 at 01:32:02PM -0400, Jason Merrill wrote:
> > --- gcc/ada/gcc-interface/utils2.cc.jj 2023-01-16 23:19:05.539727388
> > +0100
> > +++ gcc/ada/gcc-interface/utils2.cc 2023-05-05 15:37:30.193990948 +0200
> > @@ -3332,6 +3332,7 @@ gnat_invariant_expr (tree expr)
> > case
> > Am 05.05.2023 um 19:03 schrieb Alexander Monakov via Gcc-patches patc...@gcc.gnu.org>:
> >
> > Clean up confusing changes from the recent refactoring for parallel
> > match.pd build.
> >
> > gimple-match-head.o is not built. Remove related flags adjustment.
> >
> > Autogenerated gimple-match-
It seems DR 2256 permitted goto to cross the initialization of a
trivially initialized object with a non-trivial destructor. We
already supported this as an -fpermissive extension, so this patch
just makes us unconditionally support this.
Bootstrapped and regtested on x86_64-pc-linux-gnu, does th
This extends the PR93107 fix, which made us do resolve_nondeduced_context
on the elements of an initializer list during auto deduction, to happen
for CTAD as well.
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?
PR c++/106214
PR c++/93107
gcc/cp/Ch
On 5/5/23 09:40, Jakub Jelinek wrote:
On Fri, May 05, 2023 at 07:38:45AM -0400, Jason Merrill wrote:
On 5/5/23 06:45, Jakub Jelinek wrote:
+ if (TREE_READONLY (t) && !TREE_SIDE_EFFECTS (t))
+{
+ /* Return true for const qualified vars, but for members or array
+elements withou
The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized atomic mappings than the RVWMO mappings.
This patch implements Andrea Parri's proposed Ztso mappings ("Proposed
Mapping").
https://github.c
> Am 05.05.2023 um 19:03 schrieb Alexander Monakov via Gcc-patches
> :
>
> Clean up confusing changes from the recent refactoring for
> parallel match.pd build.
>
> gimple-match-head.o is not built. Remove related flags adjustment.
>
> Autogenerated gimple-match-N.o files do not depend on
>
Because everyone was commenting that we needed vector load/store support
(including Juzhe). Juzhe specifically pointed me to his patch for the
load/store patterns in his review of my code. Would you like me to
remove the patterns?
On 5/5/23 12:34, Kito Cheng wrote:
Errr, why you just mixed in
Clean up confusing changes from the recent refactoring for
parallel match.pd build.
gimple-match-head.o is not built. Remove related flags adjustment.
Autogenerated gimple-match-N.o files do not depend on
gimple-match-exports.cc.
{gimple,generic)-match-auto.h only depend on the prerequisites of
This patch follows on from g:9f635bd13fe9e85872e441b6f3618947f989909a
("the previous patch"). To start by quoting that:
If an insn requires two operands to be tied, and the input operand dies
in the insn, IRA acts as though there were a copy from the input to the
output with the same execution fr
Implement vmovnbq, vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq
using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmovnbq, vmovntq, vqmovnbq)
(vqmovntq, vqmovunbq, vqmovuntq): New.
* config/arm/arm-
Implement vrndq, vrndaq, vrndmq, vrndnq, vrndpq, vrndxq using the new
MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_F): New.
(vrndaq, vrndmq, vrndnq, vrndpq, vrndq, vrndxq): New.
* config/arm/arm-mve
Factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq so
that they use the same pattern.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_MOVN, MVE_MOVN_M): New.
(mve_insn): Add vmovnb, vmovnt, vqmovnb, vqmovnt, vqmovunb,
vqmovunt.
This patch adds the binary_widen_n shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_widen_n): New.
* config/arm/arm-mve-builtins-shapes.h (binary_widen_n): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 53 +++
Implement vshllbq and vshlltq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vshllbq, vshlltq): New.
* config/arm/arm-mve-builtins-base.def (vshllbq, vshlltq): New.
* config/arm/arm-mve-builtins-base.
Implement vabsq, vnegq, vclsq, vclzq, vqabsq, vqnegq using the new MVE
builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N_NO_U_F): New.
(vabsq, vnegq, vclsq, vclzq, vqabsq, vqnegq): New.
* config/arm/arm
Factorize vshllbq vshlltq so that they use the same pattern.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn): Add vshllb, vshllt.
(VSHLLBQ_N, VSHLLTQ_N): Remove.
(VSHLLxQ_N): New.
(VSHLLBQ_M_N, VSHLLTQ_M_N): Remove.
(VSHLLxQ_
This patch adds the binary_move_narrow and binary_move_narrow_unsigned
shapes descriptions.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_move_narrow): New.
(binary_move_narrow_unsigned): New.
* config/arm/arm-mve-builtins-shape
Factorize vabs vcls vclz vneg vqabs vqneg vrnda vrndm vrndn vrndp vrnd
vrndx so that they use the same pattern.
This patch introduces the mve_mnemo iterator because some of the
involved intrinsics have a different name from their mnenonic: for
instance vrndq vs vrintz.
2022-09-08 Christophe Lyon
This patch adds the unary shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary): New.
* config/arm/arm-mve-builtins-shapes.h (unary): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 27 +++
gcc/confi
Errr, why you just mixed in JuZhe’s patch set into this patch set?
Michael Collison 於 2023年5月5日 週五，23:47寫道：
> This series of patches adds foundational support for RISC-V
> auto-vectorization support. These patches are based on the current upstream
> rvv vector intrinsic support and is not a new i
> hi Jiawei
>
> Please ignore my previous reply. I accidently sent the email before I
> finished it.
> Sorry for that!
>
> I downloaded the series of patches from you and found in some cases
> it fails to generate zcmp push and pop insns.
>
> TC:
>
> char my_getchar();
> int test_s0()
> {
>
>
2023-03-02 Michael Collison
Vineet Gupta
* gcc.target/riscv/rvv/autovec: New directory
for autovectorization tests.
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New
test to verify code generation of vector add on rv32.
* gcc.target/riscv/r
From: Kevin Lee
2023-04-14 Kevin Lee
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit
type
* gcc.target/riscv/rvv/autovec/loop-add.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/l
While working on autovectorizing for the RISCV port I encountered an issue
where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
where GET_MODE_NUNITS is equal to one.
Tested on RISCV and x86_64-linux-g
2023-04-05 Michael Collison
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New
test to verify code generation of vector "and" on rv32.
* gcc.target/riscv/rvv/autovec/loop-and.c: New
test to verify code generation of vector "and" on rv64.
* gcc.target/ris
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv.cc
(riscv_estimated_poly_value): Implement
TARGET_ESTIMATED_POLY_VALUE.
(riscv_preferred_simd_mode): Implement
TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
(riscv_get_mask_mode):
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h (get_tail_
2023-04-25 Michael Collison
Juzhe Zhong
* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
vector-iterators.md.
* config/riscv/vector-auto.md: New file containing
autovectorization patterns.
* config/riscv/vector.md: Remove
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-protos.h
(riscv_vector_preferred_simd_mode): New.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(emit_vlmax_vsetvl): Ditto.
(get_mask_policy_no_pr
This series of patches adds foundational support for RISC-V auto-vectorization
support. These patches are based on the current upstream rvv vector intrinsic
support and is not a new implementation. Most of the implementation consists of
adding the new vector cost model, the autovectorization pat
On Fri, May 5, 2023 at 5:13 PM Palmer Dabbelt wrote:
>
> On Fri, 05 May 2023 08:04:53 PDT (-0700), christoph.muell...@vrull.eu wrote:
> > What I forgot to mention:
> > Zfa is frozen and in public review:
> > https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
>
> Thanks, I'd als
On Fri, May 5, 2023 at 11:38 AM Tamar Christina
wrote:
> > -Original Message-
> > From: Jakub Jelinek
> > Sent: Friday, May 5, 2023 4:33 PM
> > To: Tamar Christina
> > Cc: Jeff Law ; David Edelsohn >;
> > GCC Patches
> > Subject: Re: [PATCH 5/5] match.pd: Use splits in makefile and ma
> -Original Message-
> From: Jakub Jelinek
> Sent: Friday, May 5, 2023 4:33 PM
> To: Tamar Christina
> Cc: Jeff Law ; David Edelsohn ;
> GCC Patches
> Subject: Re: [PATCH 5/5] match.pd: Use splits in makefile and make
> configurable.
>
> On Fri, May 05, 2023 at 03:22:11PM +, Tamar C
On Fri, May 05, 2023 at 03:22:11PM +, Tamar Christina wrote:
> > We require GNU make, so perhaps we could use something like $(wordlist
> > 1,$(NUM_MATCH_SPLITS),$(check_p_numbers))
> > instead of
> > $(shell seq 1 $(NUM_MATCH_SPLITS))
> > provided we move the check_p_numbers definition earlier
> -Original Message-
> From: Jakub Jelinek
> Sent: Friday, May 5, 2023 4:18 PM
> To: Jeff Law
> Cc: David Edelsohn ; Tamar Christina
> ; GCC Patches
> Subject: Re: [PATCH 5/5] match.pd: Use splits in makefile and make
> configurable.
>
> On Fri, May 05, 2023 at 09:04:16AM -0600, Jeff La
On Fri, May 05, 2023 at 09:04:16AM -0600, Jeff Law via Gcc-patches wrote:
> On 5/5/23 08:59, David Edelsohn via Gcc-patches wrote:
> > This patch has broken GCC bootstrap on AIX. It appears to rely upon, or
> > complain about, the command "seq":
> >
> > /nasfarm/edelsohn/install/GCC12/bin/g++ -st
While looking into a different issue, I noticed that it
would take until the second forwprop pass to do some
forward proping and it was because the ssa name was
used more than once but the second statement was
"dead" and we don't remove that until much later.
So this uses simple_dce_from_worklist
On 5/5/23 09:08, Tamar Christina wrote:
-Original Message-
From: Jeff Law
Sent: Friday, May 5, 2023 4:04 PM
To: David Edelsohn ; Tamar Christina
Cc: GCC Patches
Subject: Re: [PATCH 5/5] match.pd: Use splits in makefile and make
configurable.
On 5/5/23 08:59, David Edelsohn via Gc
On Fri, 05 May 2023 08:04:53 PDT (-0700), christoph.muell...@vrull.eu wrote:
What I forgot to mention:
Zfa is frozen and in public review:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
Thanks, I'd also forgot to send that out ;).
I think the only blocker here on the sp
Hello,
On Wed, Apr 26 2023, Aldy Hernandez via Gcc-patches wrote:
> gcc/ChangeLog:
>
> * ipa-cp.cc (ipa_vr_operation_and_type_effects): Convert to ranger API.
> (ipa_value_range_from_jfunc): Same.
> (propagate_vr_across_jump_function): Same.
> * ipa-fnsummary.cc (evaluate_c
> -Original Message-
> From: Jeff Law
> Sent: Friday, May 5, 2023 4:04 PM
> To: David Edelsohn ; Tamar Christina
>
> Cc: GCC Patches
> Subject: Re: [PATCH 5/5] match.pd: Use splits in makefile and make
> configurable.
>
>
>
> On 5/5/23 08:59, David Edelsohn via Gcc-patches wrote:
> >
What I forgot to mention:
Zfa is frozen and in public review:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
On Fri, May 5, 2023 at 5:03 PM Christoph Müllner
wrote:
>
> On Wed, Apr 19, 2023 at 11:58 AM Jin Ma wrote:
> >
> > This patch adds the 'Zfa' extension for riscv, w
On 5/5/23 08:59, David Edelsohn via Gcc-patches wrote:
This patch has broken GCC bootstrap on AIX. It appears to rely upon, or
complain about, the command "seq":
/nasfarm/edelsohn/install/GCC12/bin/g++ -std=c++11 -g -DIN_GCC
-fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall
-
On Wed, Apr 19, 2023 at 11:58 AM Jin Ma wrote:
>
> This patch adds the 'Zfa' extension for riscv, which is based on:
> https://github.com/riscv/riscv-isa-manual/commits/zfb
>
> https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da
>
> The binutils-gdb for '
This patch has broken GCC bootstrap on AIX. It appears to rely upon, or
complain about, the command "seq":
/nasfarm/edelsohn/install/GCC12/bin/g++ -std=c++11 -g -DIN_GCC
-fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall
-Wno-narrowing -Wwrite-strings -Wcast-qual -Wno-format
-Wmiss
From: Juzhe-Zhong
Address comments from Robin.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (preferred_simd_mode): Fix comments.
* config/riscv/riscv.cc (riscv_get_arg_info): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Fix function name.
Thank you!
-Original Message-
From: Kito Cheng
Sent: Friday, May 5, 2023 10:52 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH v2] RISC-V: Legitimise the const0_rtx for RVV indexed
load/store
pushed to trun
pushed v1 to trunk
On Fri, May 5, 2023 at 8:46 PM Li, Pan2 via Gcc-patches
wrote:
>
> Ok, sounds good. Thank you!
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Friday, May 5, 2023 8:37 PM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
>
pushed to trunk, thanks :)
On Thu, May 4, 2023 at 5:12 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch try to legitimise the const0_rtx (aka zero register)
> as the base register for the RVV indexed load/store instructions
> by allowing the const as the operand of the indexed RT
Hi Juzhe,
I wasn't yet able to check this locally so just some minor comment nits:
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN < 128 &&
> +
From: Juzhe-Zhong
This patch is fixing my recent optimization patch:
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
In that patch, the new_info = parse_insn (i) is not correct.
Since consider the following case:
vsetvli a5,a4, e8,m1
..
vsetvli zero,a5,
From: Juzhe-Zhong
This patch is depending on
https://patchwork.sourceware.org/project/gcc/patch/20230504054544.203366-1-juzhe.zh...@rivai.ai/
Fix codes according to comments of Kito.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Move RVV type argument
handling outside.
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