[PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes

[Michael Collison]

2023-04-24  Michael Collison  <colli...@rivosinc.com>
            Juzhe Zhong  <juzhe.zh...@rivai.ai>

        * config/riscv/riscv-protos.h
        (riscv_vector_preferred_simd_mode): New.
        (riscv_vector_mask_mode_p): Ditto.
        (riscv_vector_get_mask_mode): Ditto.
        (emit_vlmax_vsetvl): Ditto.
        (get_mask_policy_no_pred): Ditto.
        (get_tail_policy_no_pred): Ditto.
        (vlmul_field_enum): Ditto.
        * config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
        Remove static scope.
        * config/riscv/riscv-opts.h (riscv_vector_lmul_enum): New enum.
---
 gcc/config/riscv/riscv-opts.h   | 10 ++++++++++
 gcc/config/riscv/riscv-protos.h |  9 +++++++++
 2 files changed, 19 insertions(+)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4207db240ea..00c4ab222ae 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -67,6 +67,7 @@ enum stack_protector_guard {
   SSP_GLOBAL                   /* global canary */
 };
 
+
 /* RISC-V auto-vectorization preference.  */
 enum riscv_autovec_preference_enum {
   NO_AUTOVEC,
@@ -82,6 +83,15 @@ enum riscv_autovec_lmul_enum {
   RVV_M8 = 8
 };
 
+/* vectorization factor.  */
+enum riscv_vector_lmul_enum
+{
+  RVV_LMUL1 = 1,
+  RVV_LMUL2 = 2,
+  RVV_LMUL4 = 4,
+  RVV_LMUL8 = 8
+};
+
 #define MASK_ZICSR    (1 << 0)
 #define MASK_ZIFENCEI (1 << 1)
 
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 33eb574aadc..fb39b856735 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -243,4 +243,13 @@ th_mempair_output_move (rtx[4], bool, machine_mode, 
RTX_CODE);
 #endif
 
 extern bool riscv_use_divmod_expander (void);
+/* Routines implemented in riscv-v.cc.  */
+
+namespace riscv_vector {
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode);
+extern bool riscv_vector_mask_mode_p (machine_mode);
+extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
+extern rtx get_mask_policy_no_pred ();
+extern rtx get_tail_policy_no_pred ();
+}
 #endif /* ! GCC_RISCV_PROTOS_H */
-- 
2.34.1