From: Kevin Lee <kev...@rivosinc.com>

2023-04-14 Kevin Lee <kev...@rivosinc.com>
gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit
type
        * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-and.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-div.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-max.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-min.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-or.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto
        * gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto
---
 .../gcc.target/riscv/rvv/autovec/loop-add-rv32.c       |  7 ++++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c  |  7 ++++---
 .../gcc.target/riscv/rvv/autovec/loop-and-rv32.c       |  7 ++++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c  |  7 ++++---
 .../gcc.target/riscv/rvv/autovec/loop-div-rv32.c       | 10 ++++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c  | 10 ++++++----
 .../gcc.target/riscv/rvv/autovec/loop-max-rv32.c       |  9 +++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c  |  9 +++++----
 .../gcc.target/riscv/rvv/autovec/loop-min-rv32.c       |  9 +++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c  |  9 +++++----
 .../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c       | 10 ++++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c  | 10 ++++++----
 .../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c       |  7 ++++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c  |  7 ++++---
 .../gcc.target/riscv/rvv/autovec/loop-or-rv32.c        |  7 ++++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c   |  7 ++++---
 .../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c       |  7 ++++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c  |  7 ++++---
 .../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c       |  7 ++++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c  |  7 ++++---
 20 files changed, 92 insertions(+), 68 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
index bdc3b6892e9..d2765e67d0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] + b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
index d7f992c7d27..c43f6d3e8cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] + b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
index eb1ac5b44fd..703f4843c2b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] & b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
index ff0cc2a5df7..ae74e4c6cc5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] & b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
index 21960f265b7..59d379d8647 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] / b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,6 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
index bd675b4f6f0..aa8ca21bac9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] / b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,6 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
index 751ee9ecaa3..5e44b3f1a5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] >= b[i] ? a[i] : b[i];                     \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,5 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
index f4dbf3f04fc..4e4cc3ea97d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] >= b[i] ? a[i] : b[i];                     \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,5 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
index e51cf590577..128bbed8d79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] <= b[i] ? a[i] : b[i];                     \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,5 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
index 304f939f6f9..74e75dd5adc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] <= b[i] ? a[i] : b[i];                     \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,5 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
index 7c497f6e4cc..23bc5d04bd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] % b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,6 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
index 7508f4a50d1..2b1d57a0cb2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] % b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,5 +22,6 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
index fd6dcbf9c53..6561633536a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] * b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
index 9fce40890ef..08b207f0701 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] * b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
index 305d106abd9..58f7b06b5be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] | b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
index 501017bc790..7e6b0bed282 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] | b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
index 7d0a40ec539..48ae9411872 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] - b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
index c8900884f83..23a91e38931 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] - b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
index 6a9ffdb11d5..0a65b6261b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" 
} */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] ^ b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
index c9d7d7f8a75..9bfff8e6701 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } 
*/
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
 
 #include <stdint.h>
 
@@ -10,8 +10,9 @@
       dst[i] = a[i] ^ b[i];                            \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
@@ -21,4 +22,4 @@
 
 TEST_ALL()
 
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
-- 
2.34.1

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