Factorize vabs vcls vclz vneg vqabs vqneg vrnda vrndm vrndn vrndp vrnd
vrndx so that they use the same pattern.
This patch introduces the mve_mnemo iterator because some of the
involved intrinsics have a different name from their mnenonic: for
instance vrndq vs vrintz.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_INT_M_UNARY, MVE_INT_UNARY)
(MVE_FP_UNARY, MVE_FP_M_UNARY): New.
(mve_insn): Add vabs, vcls, vclz, vneg, vqabs, vqneg, vrnda,
vrndm, vrndn, vrndp, vrnd, vrndx.
(isu): Add VABSQ_M_S, VCLSQ_M_S, VCLZQ_M_S, VCLZQ_M_U, VNEGQ_M_S,
VQABSQ_M_S, VQNEGQ_M_S.
(mve_mnemo): New.
* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrndxq_f<mode>)
(mve_vrndq_f<mode>, mve_vrndpq_f<mode>, mve_vrndnq_f<mode>)
(mve_vrndmq_f<mode>, mve_vrndaq_f<mode>): Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vnegq_f<mode>, mve_vabsq_f<mode>): Merge into ...
(mve_v<absneg_str>q_f<mode>): ... this.
(mve_vnegq_s<mode>, mve_vabsq_s<mode>): Merge into ...
(mve_v<absneg_str>q_s<mode>): ... this.
(mve_vclsq_s<mode>, mve_vqnegq_s<mode>, mve_vqabsq_s<mode>): Merge into
...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vabsq_m_s<mode>, mve_vclsq_m_s<mode>)
(mve_vclzq_m_<supf><mode>, mve_vnegq_m_s<mode>)
(mve_vqabsq_m_s<mode>, mve_vqnegq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vabsq_m_f<mode>, mve_vnegq_m_f<mode>, mve_vrndaq_m_f<mode>)
(mve_vrndmq_m_f<mode>, mve_vrndnq_m_f<mode>, mve_vrndpq_m_f<mode>)
(mve_vrndxq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
---
gcc/config/arm/iterators.md | 80 ++++++++
gcc/config/arm/mve.md | 383 +++++-------------------------------
2 files changed, 126 insertions(+), 337 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 53873704174..0b4f69ee874 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -333,6 +333,42 @@ (define_code_iterator SSPLUSMINUS [ss_plus ss_minus])
;; Max/Min iterator, to factorize MVE patterns
(define_code_iterator MAX_MIN_SU [smax umax smin umin])
+;; MVE integer unary operations.
+(define_int_iterator MVE_INT_M_UNARY [
+ VABSQ_M_S
+ VCLSQ_M_S
+ VCLZQ_M_S VCLZQ_M_U
+ VNEGQ_M_S
+ VQABSQ_M_S
+ VQNEGQ_M_S
+ ])
+
+(define_int_iterator MVE_INT_UNARY [
+ VCLSQ_S
+ VQABSQ_S
+ VQNEGQ_S
+ ])
+
+(define_int_iterator MVE_FP_UNARY [
+ VRNDQ_F
+ VRNDAQ_F
+ VRNDMQ_F
+ VRNDNQ_F
+ VRNDPQ_F
+ VRNDXQ_F
+ ])
+
+(define_int_iterator MVE_FP_M_UNARY [
+ VABSQ_M_F
+ VNEGQ_M_F
+ VRNDAQ_M_F
+ VRNDMQ_M_F
+ VRNDNQ_M_F
+ VRNDPQ_M_F
+ VRNDQ_M_F
+ VRNDXQ_M_F
+ ])
+
;; MVE integer binary operations.
(define_code_iterator MVE_INT_BINARY_RTX [plus minus mult])
@@ -551,6 +587,8 @@ (define_code_attr mve_addsubmul [
(define_int_attr mve_insn [
(VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F "vabd")
(VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd")
+ (VABSQ_M_F "vabs")
+ (VABSQ_M_S "vabs")
(VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd")
(VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd")
(VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd")
@@ -558,6 +596,9 @@ (define_int_attr mve_insn [
(VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic")
(VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic")
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
+ (VCLSQ_M_S "vcls")
+ (VCLSQ_S "vcls")
+ (VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
(VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F
"vcreate")
(VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
(VHADDQ_M_N_S "vhadd") (VHADDQ_M_N_U "vhadd")
@@ -577,9 +618,13 @@ (define_int_attr mve_insn [
(VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul")
(VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul")
(VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul")
+ (VNEGQ_M_F "vneg")
+ (VNEGQ_M_S "vneg")
(VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr")
(VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr")
(VORRQ_N_S "vorr") (VORRQ_N_U "vorr")
+ (VQABSQ_M_S "vqabs")
+ (VQABSQ_S "vqabs")
(VQADDQ_M_N_S "vqadd") (VQADDQ_M_N_U "vqadd")
(VQADDQ_M_S "vqadd") (VQADDQ_M_U "vqadd")
(VQADDQ_N_S "vqadd") (VQADDQ_N_U "vqadd")
@@ -594,6 +639,8 @@ (define_int_attr mve_insn [
(VQDMULHQ_M_S "vqdmulh")
(VQDMULHQ_N_S "vqdmulh")
(VQDMULHQ_S "vqdmulh")
+ (VQNEGQ_M_S "vqneg")
+ (VQNEGQ_S "vqneg")
(VQRDMLADHQ_M_S "vqrdmladh")
(VQRDMLADHXQ_M_S "vqrdmladhx")
(VQRDMLAHQ_M_N_S "vqrdmlah")
@@ -638,6 +685,12 @@ (define_int_attr mve_insn [
(VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
(VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
(VRMULHQ_S "vrmulh") (VRMULHQ_U "vrmulh")
+ (VRNDAQ_F "vrnda") (VRNDAQ_M_F "vrnda")
+ (VRNDMQ_F "vrndm") (VRNDMQ_M_F "vrndm")
+ (VRNDNQ_F "vrndn") (VRNDNQ_M_F "vrndn")
+ (VRNDPQ_F "vrndp") (VRNDPQ_M_F "vrndp")
+ (VRNDQ_F "vrnd") (VRNDQ_M_F "vrnd")
+ (VRNDXQ_F "vrndx") (VRNDXQ_M_F "vrndx")
(VRSHLQ_M_N_S "vrshl") (VRSHLQ_M_N_U "vrshl")
(VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
(VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl")
@@ -666,6 +719,13 @@ (define_int_attr mve_insn [
])
(define_int_attr isu [
+ (VABSQ_M_S "s")
+ (VCLSQ_M_S "s")
+ (VCLZQ_M_S "i")
+ (VCLZQ_M_U "i")
+ (VNEGQ_M_S "s")
+ (VQABSQ_M_S "s")
+ (VQNEGQ_M_S "s")
(VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
(VQRSHRNBQ_N_S "s") (VQRSHRNBQ_N_U "u")
(VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
@@ -692,6 +752,17 @@ (define_int_attr isu [
(VSHRNTQ_N_S "i") (VSHRNTQ_N_U "i")
])
+(define_int_attr mve_mnemo [
+ (VABSQ_M_S "vabs") (VABSQ_M_F "vabs")
+ (VNEGQ_M_S "vneg") (VNEGQ_M_F "vneg")
+ (VRNDAQ_F "vrinta") (VRNDAQ_M_F "vrinta")
+ (VRNDMQ_F "vrintm") (VRNDMQ_M_F "vrintm")
+ (VRNDNQ_F "vrintn") (VRNDNQ_M_F "vrintn")
+ (VRNDPQ_F "vrintp") (VRNDPQ_M_F "vrintp")
+ (VRNDQ_F "vrintz") (VRNDQ_M_F "vrintz")
+ (VRNDXQ_F "vrintx") (VRNDXQ_M_F "vrintx")
+ ])
+
;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
;; a stack pointer operand. The minus operation is a candidate for an rsub
;; and hence only plus is supported.
@@ -1862,6 +1933,15 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VQSHRUNBQ_N_S "s")
(VQSHRUNTQ_M_N_S "s")
(VQSHRUNTQ_N_S "s")
+ (VABSQ_M_S "s")
+ (VCLSQ_M_S "s")
+ (VCLZQ_M_S "s") (VCLZQ_M_U "u")
+ (VNEGQ_M_S "s")
+ (VQABSQ_M_S "s")
+ (VQNEGQ_M_S "s")
+ (VCLSQ_S "s")
+ (VQABSQ_S "s")
+ (VQNEGQ_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b5c89fd4105..7bf344d547a 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -130,102 +130,21 @@ (define_insn "mve_vst4q<mode>"
[(set_attr "length" "16")])
;;
-;; [vrndq_m_f])
+;; [vrndaq_f]
+;; [vrndmq_f]
+;; [vrndnq_f]
+;; [vrndpq_f]
+;; [vrndq_f]
+;; [vrndxq_f]
;;
-(define_insn "mve_vrndq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRNDQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrndxq_f])
-;;
-(define_insn "mve_vrndxq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VRNDXQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrintx.f%#<V_sz_elem> %q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrndq_f])
-;;
-(define_insn "mve_vrndq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VRNDQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrintz.f%#<V_sz_elem> %q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrndpq_f])
-;;
-(define_insn "mve_vrndpq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VRNDPQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrintp.f%#<V_sz_elem> %q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrndnq_f])
-;;
-(define_insn "mve_vrndnq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VRNDNQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrintn.f%#<V_sz_elem> %q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrndmq_f])
-;;
-(define_insn "mve_vrndmq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VRNDMQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrintm.f%#<V_sz_elem> %q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrndaq_f])
-;;
-(define_insn "mve_vrndaq_f<mode>"
+(define_insn "@mve_<mve_insn>q_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VRNDAQ_F))
+ MVE_FP_UNARY))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrinta.f%#<V_sz_elem> %q0, %q1"
+ "<mve_mnemo>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -244,15 +163,16 @@ (define_insn "mve_vrev64q_f<mode>"
])
;;
-;; [vnegq_f])
+;; [vabsq_f]
+;; [vnegq_f]
;;
-(define_insn "mve_vnegq_f<mode>"
+(define_insn "mve_v<absneg_str>q_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
+ (ABSNEG:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vneg.f%#<V_sz_elem>\t%q0, %q1"
+ "v<absneg_str>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -270,19 +190,6 @@ (define_insn "mve_vdupq_n_f<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vabsq_f])
-;;
-(define_insn "mve_vabsq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vabs.f%#<V_sz_elem>\t%q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vrev32q_f])
;;
@@ -365,43 +272,18 @@ (define_insn "mve_vcvtq_from_f_<supf><mode>"
"vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
-;; [vqnegq_s])
-;;
-(define_insn "mve_vqnegq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VQNEGQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqneg.s%#<V_sz_elem>\t%q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqabsq_s])
-;;
-(define_insn "mve_vqabsq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VQABSQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqabs.s%#<V_sz_elem>\t%q0, %q1"
- [(set_attr "type" "mve_move")
-])
;;
-;; [vnegq_s])
+;; [vabsq_s]
+;; [vnegq_s]
;;
-(define_insn "mve_vnegq_s<mode>"
+(define_insn "mve_v<absneg_str>q_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
+ (ABSNEG:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vneg.s%#<V_sz_elem>\t%q0, %q1"
+ "v<absneg_str>.s%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -460,16 +342,18 @@ (define_expand "mve_vclzq_u<mode>"
)
;;
-;; [vclsq_s])
+;; [vclsq_s]
+;; [vqabsq_s]
+;; [vqnegq_s]
;;
-(define_insn "mve_vclsq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VCLSQ_S))
+ MVE_INT_UNARY))
]
"TARGET_HAVE_MVE"
- "vcls.s%#<V_sz_elem>\t%q0, %q1"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -487,19 +371,6 @@ (define_insn "@mve_vaddvq_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vabsq_s])
-;;
-(define_insn "mve_vabsq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (abs:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
- ]
- "TARGET_HAVE_MVE"
- "vabs.s%#<V_sz_elem>\t%q0, %q1"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vrev32q_u, vrev32q_s])
;;
@@ -2254,18 +2125,23 @@ (define_insn "mve_vshlcq_<supf><mode>"
"vshlc %q0, %1, %4")
;;
-;; [vabsq_m_s])
+;; [vabsq_m_s]
+;; [vclsq_m_s]
+;; [vclzq_m_s, vclzq_m_u]
+;; [vnegq_m_s]
+;; [vqabsq_m_s]
+;; [vqnegq_m_s]
;;
-(define_insn "mve_vabsq_m_s<mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VABSQ_M_S))
+ MVE_INT_M_UNARY))
]
"TARGET_HAVE_MVE"
- "vpst\;vabst.s%#<V_sz_elem> %q0, %q2"
+ "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2285,38 +2161,6 @@ (define_insn "mve_vaddvaq_p_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vclsq_m_s])
-;;
-(define_insn "mve_vclsq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VCLSQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vclst.s%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vclzq_m_s, vclzq_m_u])
-;;
-(define_insn "mve_vclzq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VCLZQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vcmpcsq_m_n_u])
;;
@@ -2813,22 +2657,6 @@ (define_insn "mve_vmvnq_m_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vnegq_m_s])
-;;
-(define_insn "mve_vnegq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VNEGQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vpselq_u, vpselq_s])
;;
@@ -2845,22 +2673,6 @@ (define_insn "@mve_vpselq_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqabsq_m_s])
-;;
-(define_insn "mve_vqabsq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VQABSQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqdmlahq_n_s])
;;
@@ -2893,22 +2705,6 @@ (define_insn "mve_vqdmlashq_n_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqnegq_m_s])
-;;
-(define_insn "mve_vqnegq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VQNEGQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqrdmladhq_s])
;;
@@ -3198,19 +2994,27 @@ (define_insn "mve_vmladavaxq_s<mode>"
"vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
[(set_attr "type" "mve_move")
])
+
;;
-;; [vabsq_m_f])
+;; [vabsq_m_f]
+;; [vnegq_m_f]
+;; [vrndaq_m_f]
+;; [vrndmq_m_f]
+;; [vrndnq_m_f]
+;; [vrndpq_m_f]
+;; [vrndq_m_f]
+;; [vrndxq_m_f]
;;
-(define_insn "mve_vabsq_m_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VABSQ_M_F))
+ MVE_FP_M_UNARY))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vabst.f%#<V_sz_elem> %q0, %q2"
+ "vpst\;<mve_mnemo>t.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3863,21 +3667,6 @@ (define_insn "mve_vmvnq_m_n_<supf><mode>"
"vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vnegq_m_f])
-;;
-(define_insn "mve_vnegq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VNEGQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
;;
;; [vbicq_m_n_s, vbicq_m_n_u]
@@ -4104,86 +3893,6 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrndaq_m_f])
-;;
-(define_insn "mve_vrndaq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRNDAQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrndmq_m_f])
-;;
-(define_insn "mve_vrndmq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRNDMQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrndnq_m_f])
-;;
-(define_insn "mve_vrndnq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRNDNQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrndpq_m_f])
-;;
-(define_insn "mve_vrndpq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRNDPQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrndxq_m_f])
-;;
-(define_insn "mve_vrndxq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRNDXQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vcvtmq_m_s, vcvtmq_m_u])
;;
--
2.34.1
