https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From c23b4d2dde0e03051332604d18eaf3bd434e4d4e Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Thu, 15 Aug 2024 21:49:23 +
Subject: [PATCH 1/3] [BPF] Refactor BPFSubtarget::initSubtargetFeatures()
(NFC)
R
https://github.com/peilin-ye ready_for_review
https://github.com/llvm/llvm-project/pull/108636
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@@ -622,6 +665,47 @@ let Predicates = [BPFHasLdsx] in {
def LDD : LOADi64;
+class LOAD_ACQUIRE
+: TYPE_LD_ST {
+ bits<4> dst;
+ bits<20> addr;
+
+ let Inst{51-48} = dst;
+ let Inst{55-52} = addr{19-16}; // base reg
+ let Inst{47-32} = addr{15-0}; // offset
+ let Ins
https://github.com/peilin-ye edited
https://github.com/llvm/llvm-project/pull/108636
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https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 7a3c9741ec7a5680b0a59ed7c0316a71c78ccf48 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
https://github.com/peilin-ye edited
https://github.com/llvm/llvm-project/pull/108636
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peilin-ye wrote:
Back on this; rebased and pushed patchset v6 to make `acquire-release.ll` also
cover `-march=bpfeb` as suggested by Eduard. Basically:
```
; CHECK-LE: w0 = load_acquire((u8 *)(r1 + 0)) # encoding:
[0xd3,0x10,0x00,0x00,0x10,0x00,0x00,0x00]
; CHECK-BE: w0 = load_acquire((u8 *)(r
https://github.com/peilin-ye edited
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https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 32cc1b238ddd67a96627a1cc57c1b9ca5c6be938 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
@@ -1205,10 +1298,19 @@ class LOAD32
: LOAD32;
+class LOAD_ACQUIREi32
+: LOAD_ACQUIRE;
+
let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
def LDW32 : LOADi32;
def LDH32 : LOADi32;
def LDB32 : LOADi32;
+
+ let Predicates = [BPFHasLoadAcquire]
https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From fda5dadf6af584fab9eef9fa588efe5454a9d1d1 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
peilin-ye wrote:
Thanks for all your suggestions! Main changes in patchset v5:
1. use `-mcpu=v4` instead of `-mcpu=v5`
2. make both load-acquire and store-release `BPF_STX | BPF_ATOMIC` insns,
instead of introducing new mode modifiers:
`BPF_STX | BPF_ATOMIC` insns use a subset of `BPFArithOp<
@@ -522,6 +526,28 @@ let Predicates = [BPFNoALU32] in {
}
def STD : STOREi64;
+class relaxed_store
+ : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+ let IsAtomic = 1;
+ let IsAtomicOrderingReleaseOrStronger = 0;
+}
+
+class releasing_store
+ : PatFra
peilin-ye wrote:
> In the above, you will do unsigned load extension. But what about signed
extension load variant?
@yonghong-song, if we ever need that, we can add a new flag to bit `0-3` of
`imm` to indicate "this 8- or 16-bit load-acquire is sign-extending", just like
`BPF_FETCH` for `BPF_X
peilin-ye wrote:
Another problem is, right now, if I do this:
```diff
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -1343,11 +1343,11 @@ let Predicates = [BPFHasALU32] in {
let Predicates = [BPFHasLoadAcquire] in {
foreach P = [[relaxed_load, LDW
@@ -48,6 +48,24 @@ def BPF_END : BPFArithOp<0xd>;
def BPF_XCHG: BPFArithOp<0xe>;
def BPF_CMPXCHG : BPFArithOp<0xf>;
+class BPFAtomicLoadStoreOp val> {
+ bits<4> Value = val;
+}
+
+def BPF_ATOMIC_LOAD : BPFAtomicLoadStoreOp<0x1>;
+def BPF_ATOMIC_STORE : BPFAtomicLoadStore
https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 885d5141f6707a0fdf4be363351083f8fdf8fd54 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
peilin-ye wrote:
Changes in v7:
1. Change encoding to make it easier to support `SEQ_CST` in the future
(Yingchi)
```
(before) | imm{7-4}| imm{3-0} |
- | --- | |
load-acquire | BPF_LOAD_ACQ (0x1) | 0x0 |
store-release | BPF_STORE_
@@ -48,6 +48,13 @@ def BPF_END : BPFArithOp<0xd>;
def BPF_XCHG: BPFArithOp<0xe>;
def BPF_CMPXCHG : BPFArithOp<0xf>;
+class BPFAtomicLoadStoreOp val> {
+ bits<4> Value = val;
+}
+
+def BPF_LOAD_ACQ : BPFAtomicLoadStoreOp<0x1>;
+def BPF_STORE_REL : BPFAtomicLoadStoreOp<0xb
@@ -0,0 +1,142 @@
+; RUN: llc < %s -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding \
+; RUN: | FileCheck -check-prefixes=CHECK-LE %s
+; RUN: llc < %s -march=bpfeb -mcpu=v4 -verify-machineinstrs -show-mc-encoding \
peilin-ye wrote:
(replied above)
@@ -0,0 +1,142 @@
+; RUN: llc < %s -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding \
peilin-ye wrote:
> again
Thanks for pointing this out, but I do want to test the MC encoding. It looks
like at the moment a lot of tests under `llvm/test/CodeGen
peilin-ye wrote:
Pushed v8 to make it generate plain (`BPF_MEM`) loads and stores if user
requested `__ATOMIC_RELAXED`, as suggested by Yonghong. Updated commit message
accordingly.
https://github.com/llvm/llvm-project/pull/108636
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peilin-ye wrote:
Sure Yonghong, I can include that in this PR. Similarly, since we cannot have
both `relaxed_load` and
`relaxed_load`, I'll keep it `zext` (`BPF_MEM` |
`BPF_LDX`) for now. For example:
```c
int foo(char *ptr) {
return __atomic_load_n(ptr, __ATOMIC_RELAXED);
}
```
This'll
https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 8ab5d1c2e36dfa44be637478deeabaa4f586dcee Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
peilin-ye wrote:
Hi @arsenm, I'm trying to match `atomic_load_zext_{8,16}` in BPF backend but it
doesn't work:
```
fatal error: error in backend: Cannot select: t8: i32,ch = AtomicLoad<(load
acquire (s8) from %ir.ptr), zext from i8> t0, t2, demo.bpf.c:3:12
t2: i64,ch = CopyFromReg t0, Registe
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
peilin-ye wrote:
> So your change looks good. Once you get some kernel work in reasonable shape,
> this patch can land. Thanks!
Sure, thanks for reviewing this!
https://github.com/llvm/llvm-project/pull/108636
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@@ -67,6 +67,8 @@ void BPFTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__BPF_FEATURE_SDIV_SMOD");
Builder.defineMacro("__BPF_FEATURE_GOTOL");
Builder.defineMacro("__BPF_FEATURE_ST");
+Builder.defineMacro("__BPF_FEATURE_LOAD_ACQUIRE"
peilin-ye wrote:
@yonghong-song Hi Yonghong, about my earlier question:
> However, I wonder how do I generate a sign-extending (sext), acquiring
> ATOMIC_LOAD in SelectionDAG?
After more digging, I found this in
`llvm/include/llvm/CodeGen/TargetLowering.h`:
```cpp
/// Returns how the platf
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
@@ -48,6 +48,13 @@ def BPF_END : BPFArithOp<0xd>;
def BPF_XCHG: BPFArithOp<0xe>;
def BPF_CMPXCHG : BPFArithOp<0xf>;
+class BPFAtomicLoadStoreOp val> {
+ bits<4> Value = val;
+}
+
+def BPF_LOAD_ACQ : BPFAtomicLoadStoreOp<0x1>;
+def BPF_STORE_REL : BPFAtomicLoadStoreOp<0xb
@@ -0,0 +1,106 @@
+; RUN: llc < %s -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding \
+; RUN: | FileCheck -check-prefixes=CHECK-LE %s
+; RUN: llc < %s -march=bpfeb -mcpu=v4 -verify-machineinstrs -show-mc-encoding \
+; RUN: | FileCheck -check-prefixes=CHECK-BE %s
+
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 885d5141f6707a0fdf4be363351083f8fdf8fd54 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
peilin-ye wrote:
Pushed v9:
- Rewrote `acquire-release.ll` to make it also test `__ATOMIC_RELAXED`
(renamed to `atomic-load-store.ll`, just like e.g.
`llvm/test/CodeGen/X86/atomic-load-store.ll`)
- Style change as suggested by Matt
https://github.com/llvm/llvm-project/pull/108636
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https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 885d5141f6707a0fdf4be363351083f8fdf8fd54 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Sat, 5 Oct 2024 06:44:21 +
Subject: [PATCH 1/3] [BPF] Rename isST*() and isLD*() functions in
BPFMISimplifyPat
@@ -703,6 +714,20 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD_STORE(SDValue Op,
+ Sel
@@ -69,29 +69,25 @@ void BPFSubtarget::initSubtargetFeatures(StringRef CPU,
StringRef FS) {
CPU = "v3";
if (CPU == "probe")
CPU = sys::detail::getHostCPUNameForBPF();
- if (CPU == "generic" || CPU == "v1")
+ if (CPU.empty() || CPU == "generic" || CPU == "v1")
-
peilin-ye wrote:
@eddyz87,
Thanks! I didn't know about `XXXISelLowering.cpp`.
> But there should be a way to tweak existing `fail` function to stop after
> errors are reported.
Can we `exit(1)` ? :-)
`fail()` calls `LLVMContext::diagnose()`, which already `exit(1)` when there's
no "report
peilin-ye wrote:
> lgtm, but please note CI failure:
Oops, I'll take a closer look later. Thanks!
https://github.com/llvm/llvm-project/pull/108636
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peilin-ye wrote:
@eddyz87,
> Sorry for the delayed reply.
No worries at all!
> I'd say let's go with what you suggest, but avoid exit(1) call. We need to
> figure out how to do fail() w/o backtrace, but that is outside of the scope
> for this pull request.
Got it, rebased and added a 4th co
https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 68d003f7156b16656a11a1395b88b6fbed368401 Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Thu, 15 Aug 2024 21:49:23 +
Subject: [PATCH 1/4] [BPF] Refactor BPFSubtarget::initSubtargetFeatures()
(NFC)
R
https://github.com/peilin-ye edited
https://github.com/llvm/llvm-project/pull/108636
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https://github.com/peilin-ye updated
https://github.com/llvm/llvm-project/pull/108636
>From 087c7eb6e5fdd6866ee5209ce9cea93864dd3c6d Mon Sep 17 00:00:00 2001
From: Peilin Ye
Date: Thu, 15 Aug 2024 21:49:23 +
Subject: [PATCH 1/3] [BPF] Refactor BPFSubtarget::initSubtargetFeatures()
(NFC)
R
peilin-ye wrote:
(pushed v2 to resolve the easier issues first :-)
- deleted redundant `CPU.empty()` check
- for now, fall back to `ACQUIRE` and `RELEASE` if user requested weaker memory
orders (`RELAXED` or `CONSUME`), until we actually support them
- took Eduard's suggestion in #107343 to u
peilin-ye wrote:
Hi @eddyz87, thanks for the review and context!
> ```
> lock *(u64 *)(r1 + 0x0) = r2 release
> lock r2 = *(u64 *)(r1 + 0x0) acquire
> ```
Appending `acquire` and `release` does sound nice to me since it makes the
syntax more similar to LLVM IR (e.g. `store atomic i64 %v, ptr %
@@ -621,6 +642,16 @@ let Predicates = [BPFHasLdsx] in {
def LDD : LOADi64;
+class acquiring_load
+: PatFrag<(ops node:$ptr), (base node:$ptr)> {
+ let IsAtomic = 1;
peilin-ye wrote:
Got it, I'll make it generate acquire and release for weaker types, and
@@ -522,6 +526,28 @@ let Predicates = [BPFNoALU32] in {
}
def STD : STOREi64;
+class relaxed_store
+ : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+ let IsAtomic = 1;
+ let IsAtomicOrderingReleaseOrStronger = 0;
+}
+
+class releasing_store
+ : PatFra
peilin-ye wrote:
Hi @yonghong-song,
No worries, and thanks for taking a look at this!
> So far, I suggest to stick to cpu v4.
I see, I can do that.
> is it possible to add acquire/release support in BPF_ATOMIC? We might want to
> reserve BPFModelModifier 7 for future use.
Sounds good, that
@@ -522,6 +526,28 @@ let Predicates = [BPFNoALU32] in {
}
def STD : STOREi64;
+class relaxed_store
+ : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+ let IsAtomic = 1;
+ let IsAtomicOrderingReleaseOrStronger = 0;
+}
+
+class releasing_store
+ : PatFra
peilin-ye wrote:
@yonghong-song, back to your example:
> ```
> $ cat t4.c
> short foo(short *ptr) {
> return __atomic_load_n(ptr, __ATOMIC_ACQUIRE);
> }
> ```
> ```
> :
>0: e9 10 00 00 00 00 00 00 w0 = load_acquire((u16 *)(r1 + 0x0))
>1: 95 00 00 00
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
https://github.com/peilin-ye edited
https://github.com/llvm/llvm-project/pull/108636
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peilin-ye wrote:
When landing, please simply land this PR as-is - considering that I've made
several references to this PR on the mailing list, and the two other commits
except the "main" one are pretty small, I no longer think it's worth it to
restructure this into stacked PRs. For future co
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