================
@@ -522,6 +526,28 @@ let Predicates = [BPFNoALU32] in {
}
def STD : STOREi64<BPF_DW, "u64", store>;
+class relaxed_store<PatFrag base>
+ : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+ let IsAtomic = 1;
+ let IsAtomicOrderingReleaseOrStronger = 0;
+}
+
+class releasing_store<PatFrag base>
+ : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+ let IsAtomic = 1;
+ let IsAtomicOrderingRelease = 1;
+}
----------------
peilin-ye wrote:
For `ATOMIC_STORE`: `IsAtomicOrderingRelease = 1` only matches `RELEASE`.
`IsAtomicOrderingReleaseOrStronger = 1` matches both `RELEASE` and `SEQ_CST`
(sequentially consistent).
- - -
For ARM64, it looks like that `releasing_store<>` has been intended to match
both `RELEASE` and `SEQ_CST` since at least commit 00ed9964c659 ("ARM64:
initial backend import"):
```c
// A store operation that actually needs release semantics.
class releasing_store<PatFrag base>
: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
assert(Ordering != AcquireRelease && "unexpected store ordering");
return Ordering == Release || Ordering == SequentiallyConsistent;
}]>;
```
Looking at `llvm/test/CodeGen/AArch64/fast-isel-atomic.ll`, it seems that a
"`store atomic` `release`" and a "`store atomic` `seq_cst`" can be turned into
the same ARM64 insn:
```
; CHECK-LABEL: atomic_store_release_16:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_release_16(ptr %p, i16 %val) #0 {
store atomic i16 %val, ptr %p release, align 2
ret void
}
```
```
; CHECK-LABEL: atomic_store_seq_cst_16:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_16(ptr %p, i16 %val) #0 {
store atomic i16 %val, ptr %p seq_cst, align 2
ret void
}
```
I haven't read the manual to understand why yet, however.
- - -
For us, I used `IsAtomicOrderingRelease` since I didn't want to match `seq_cst`
(the 4th commit in this PR makes it generate an "unsupported" error if user
called `__atomic_{load,store}[_n]()` with `__ATOMIC_SEQ_CST`, as suggested by
Eduard).
https://github.com/llvm/llvm-project/pull/108636
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