================
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+ SelectionDAG &DAG) const {
+ const char *Msg =
+ "sequentially consistent (seq_cst) atomic load is not supported";
+ SDNode *N = Op.getNode();
+ SDLoc DL(N);
+
+ if (cast<AtomicSDNode>(N)->getMergedOrdering() ==
+ AtomicOrdering::SequentiallyConsistent)
+ fail(DL, DAG, Msg);
+
+ return Op;
+}
+
+SDValue BPFTargetLowering::LowerATOMIC_STORE(SDValue Op,
+ SelectionDAG &DAG) const {
+ const char *Msg =
+ "sequentially consistent (seq_cst) atomic store is not supported";
+ EVT VT = Op.getOperand(1).getValueType();
+ SDNode *N = Op.getNode();
+ SDLoc DL(N);
+
+ // Promote operand #1 (value to store) if necessary.
+ if (!isTypeLegal(VT))
+ return SDValue();
+
+ if (cast<AtomicSDNode>(N)->getMergedOrdering() ==
+ AtomicOrdering::SequentiallyConsistent)
+ fail(DL, DAG, Msg);
----------------
peilin-ye wrote:
I see.
> Currently as per my understanding the new instructions does not have this
> ordering field (the asm, the encoding)?
Right now, `BPF_LOAD_ACQ` and `BPF_STORE_REL` use bit `4-7` of the `imm` field.
If we ever need `SEQ_CST`, we can add a new flag to bit `0-3` to indicate
"this atomic load is sequentially consistent", similar to what we already do
for other `BPF_ATOMIC` instructions: e.g. `BPF_XOR` in `imm{4-7}` means "it's
an atomic XOR", then `BPF_FETCH` in `imm{0-3}` indicates whether "it returns
the old value" or not.
- - -
Right now, this PR does:
```
| imm{0-3} | imm{4-7} |
------------- | -------- | ------------------- |
load-acquire | 0x0 | BPF_LOAD_ACQ (0x1) |
store-release | 0x0 | BPF_STORE_REL (0x2) |
```
Let me change it to (encodings unchanged):
```
| imm{0-3} | imm{4-7} |
------------- | ----------------- | --------------- |
load-acquire | BPF_ACQUIRE (0x0) | BPF_LOAD (0x1) |
store-release | BPF_RELEASE (0x0) | BPF_STORE (0x2) |
```
So that, in the future, we can have e.g.:
```
| imm{0-3} | imm{4-7} |
------------- | ----------------- | --------------- |
load-acquire | BPF_ACQUIRE (0x0) | BPF_LOAD (0x1) |
load-seq_cst | BPF_SEQ_CST (0x1) | BPF_LOAD (0x1) |
store-release | BPF_RELEASE (0x0) | BPF_STORE (0x2) |
store-seq_cst | BPF_SEQ_CST (0x1) | BPF_STORE (0x2) |
```
https://github.com/llvm/llvm-project/pull/108636
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