================
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+ SelectionDAG &DAG) const {
+ const char *Msg =
+ "sequentially consistent (seq_cst) atomic load is not supported";
+ SDNode *N = Op.getNode();
+ SDLoc DL(N);
+
+ if (cast<AtomicSDNode>(N)->getMergedOrdering() ==
+ AtomicOrdering::SequentiallyConsistent)
+ fail(DL, DAG, Msg);
+
+ return Op;
+}
+
+SDValue BPFTargetLowering::LowerATOMIC_STORE(SDValue Op,
+ SelectionDAG &DAG) const {
+ const char *Msg =
+ "sequentially consistent (seq_cst) atomic store is not supported";
+ EVT VT = Op.getOperand(1).getValueType();
+ SDNode *N = Op.getNode();
+ SDLoc DL(N);
+
+ // Promote operand #1 (value to store) if necessary.
+ if (!isTypeLegal(VT))
+ return SDValue();
----------------
peilin-ye wrote:
```c
// clang --target=bpf -mcpu=v4 -O2 -g -c -o demo.bpf.o demo.bpf.c
void bar(char *ptr, char val) {
__atomic_store_n(ptr, val, __ATOMIC_RELEASE);
}
```
Compiling the above program would trigger that if clause:
```
...
llvm::SelectionDAG::LegalizeTypes()
llvm::DAGTypeLegalizer::run()
llvm::DAGTypeLegalizer::PromoteIntegerOperand()
llvm::DAGTypeLegalizer::CustomLowerNode()
llvm::TargetLowering::LowerOperationWrapper()
llvm::BPFTargetLowering::LowerATOMIC_STORE()
```
BPF doesn't have native support for `i8` (see `BPFISelLowering.cpp`) :
```cpp
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
if (STI.getHasAlu32())
addRegisterClass(MVT::i32, &BPF::GPR32RegClass);
```
https://github.com/llvm/llvm-project/pull/108636
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