: Wednesday, April 9, 2025 6:47 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V: Refine the testcases for cond_widen_complicate-3
Hi Pan,
Richard committed combine
Kito Cheng
Sent: Tuesday, April 1, 2025 9:53 AM
To: Robin Dapp
Cc: Kito Cheng ; gcc-patches@gcc.gnu.org;
pal...@dabbelt.com; jeffreya...@gmail.com; rd...@ventanamicro.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; vine...@rivosinc.com;
patr...@rivosinc.com; monk.chi...@sifive.com
Subject: Re: [PATCH v3
in and Jeff, I will re-send the patch of vadd.vv/vx after stage
1 open, and then all other
similar cases.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, March 30, 2025 8:31 AM
To: Robin Dapp ; Paul-Antoine Arras ;
gcc-patches@gcc.gnu.org; Li, Pan2
Subject: Re: [PATCH] RISC-V:
eems no other failures from rvv.exp now.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, March 13, 2025 5:48 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V
o meet current behavior.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, March 12, 2025 7:11 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V: Refine the testcase
for a while if we need to tweak the vxrm behaviors, like set,
consume, global_reg, ... etc.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, March 4, 2025 8:51 PM
To: Vineet Gupta ; Andrew Waterman
Cc: Li, Pan2 ; jeffreya...@gmail.com;
gcc-patches@gcc.gnu.org; juzhe.zh
: Thursday, February 27, 2025 5:22 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v4] RISC-V: Fix bug for expand_const_vector interleave
[PR118931]
Hi Pan,
> + poly_int64 base1_poly = rtx_to_poly_in
ate in v4.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, February 27, 2025 1:37 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v2] RISC-V: Fix bug for expand_const_vector interleave
erleave, I think it is safe because it
leverage the
merge to generate the result, instead of IOR. Only the IOR for final result have
this issue.
Pan
-Original Message-----
From: Robin Dapp
Sent: Thursday, February 27, 2025 12:23 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai
be an issue
> and all we needed to check is CONST_VECTOR_NUNITS () * step.
I see, that explains why we have poly shift right in previous, will update in
v3.
Pan
-----Original Message-
From: Robin Dapp
Sent: Wednesday, February 26, 2025 12:46 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc:
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, February 24, 2025 7:44 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Fix bug for expand_const_vector interleave
[PR118931]
I don't explore more cases here consider we are in stage 4. I think the
expand_const_vector need some
refactor up to a point.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, February 24, 2025 4:29 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch
support DI as element size.
I will try to reproduce this after this ICE fix.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, February 18, 2025 5:36 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp...
diford
Sent: Monday, February 17, 2025 7:48 PM
To: Li, Pan2
Cc: Jeff Law ; Andrew Waterman ;
gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Make VXRM as global register [PR118103]
Richard Sandiford writes:
> The probl
t where set the partial vector to true.
Is there any suggestion here?
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, February 17, 2025 6:08 PM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subje
> So OK with the two whitespace fixes.
Thanks Jeff, will commit with the whitespace fixes.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, February 18, 2025 2:00 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subj
need another place to fix this, let me have a try.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, February 17, 2025 6:02 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re:
ile before
any potential action to take.
Pan
-Original Message-
From: Richard Sandiford
Sent: Wednesday, February 12, 2025 5:03 PM
To: Jeff Law
Cc: Andrew Waterman ; Li, Pan2 ;
gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH
Thanks Jeff and Andrew, committed as the CI passed.
Pan
-Original Message-
From: Andrew Waterman
Sent: Friday, February 7, 2025 9:54 PM
To: Jeff Law
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V
m: Robin Dapp
Sent: Friday, February 7, 2025 5:50 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Make VXRM as global register [PR118103]
> Inspired by PR118103, the VXRM register should b
> I think you meant "the value extended into" rather than "the extended to".
> OK with that fix.
Thanks Jeff, will commit the series with that fix.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, January 28, 2025 11:18 PM
To: Li, Pan2 ; gcc-patche
> Nit, can you move this check in the caller riscv_emit_mode_set () which
> already
> checks similarly for VXRM (unless there's a corner case.
Sure, I will send v2 after gcc-16 open.
Pan
-Original Message-
From: Vineet Gupta
Sent: Tuesday, January 28, 2025 11:01 AM
To:
Thanks Jeff, I will resolve the conflict and send v3 after test.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, January 27, 2025 12:38 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2 1/4] RISC-V
> It's a nice cleanup, but let's defer since it doesn't fix a bug.
Sure thing, will defer to gcc-16.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, January 26, 2025 9:34 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; r
Thanks Jeff and Sam, updated v2 for -fno-strict-aliasing.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, January 26, 2025 1:06 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com;
vine...@rivosinc.com; richard.sandif
To be efficient, I send the
sssub bugfix first, and then validate the ssadd and sstrunc
in the meantime.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, January 22, 2025 6:46 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail
Sent: Tuesday, January 21, 2025 12:47 AM
To: Palmer Dabbelt
Cc: Li, Pan2 ; Vineet Gupta ;
gnu-toolch...@rivosinc.com; Robin Dapp ;
juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Subject: Re: gcc mode switching issue (was Re: RISC-V round_away () handling of
non canonical rounding modes)
On 1/1
It is 627.cam4_s or 527.cam4_r? I can help to reproduce this from k1 board.
Pan
-Original Message-
From: Vineet Gupta
Sent: Friday, January 17, 2025 10:23 AM
To: Li, Pan2
Cc: Jeff Law ; Palmer Dabbelt ;
gnu-toolchain ; Robin Dapp ;
juzhe.zh...@rivai.ai; GCC Patches
Subject: Re: gcc
Hi Vineet,
Is there any more information about the issue description here? Like steps for
reproducing, as well as expect behavior but actual result.. etc.
It is not easy to start the investigation with blow mail thread. Thanks a lot.
Pan
-Original Message-
From: Vineet Gupta
Sent: Fri
> OK for the trunk. Sorry for the delay.
Never mind, thanks Jeff and Happ New Year, 😉!
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, January 7, 2025 9:32 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai
Kindly ping for the series.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, December 23, 2024 3:09 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject
Kindly ping for this series, and Merry Christmas!
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, December 12, 2024 4:42 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, December 10, 2024 2:28 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com; Li, Pan2
Subject
Thanks Kito, all issues like below of rvv.exp are fixed.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, December 9, 2024 2:58 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Fix
I see, thanks Robin, will have a try for this change.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, November 27, 2024 9:44 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1 1/3
from test.
Pan
-Original Message-
From: Uros Bizjak
Sent: Wednesday, November 27, 2024 4:15 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao
Subject: Re: [PATCH v4] I386: Add more testcases for unsigned SAT_ADD vector
pattern
On Wed, Nov 27, 2024 at 3:00 AM wrote:
>
s.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, November 27, 2024 8:48 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1 1/3] RISC-V: Combine vec_duplicate + vadd.vv to va
8_t, uint16_t, uint32_t, uint64_t
BTW, how can I tell the x86, x86_32, x86_64 from the test source code?
Pan
-Original Message-
From: Uros Bizjak
Sent: Monday, November 25, 2024 4:40 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao
Subject: Re: [PATCH v2] I386: Add more
> You're scanning ".SAT_ADD ", so maybe better with pass "optimized" instead of
> "expand"?
Sure, let me update in v2.
Pan
-Original Message-
From: Liu, Hongtao
Sent: Monday, November 25, 2024 10:09 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Almost forgot this patch, kindly reminder.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, November 11, 2024 4:44 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp
> Had the discussion above been included in the patch I probably would
> have just acked it then :-) Now that I understand what you're doing,
> it's fine.
I see, thank you ;).
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, November 19, 2024 10:57 PM
To: Li,
I prefer to fix it one by one (like strided, then gather ... etc), to
make sure the patch
could be friendly for review, as well as avoid any new failures of rvv.exp
anonymously.
Is there any best practice for such kind of changes ?
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday
> Just a reminder that this requires either adding a new exp file or
> adding a few new lines in riscv.exp.
I see, thanks a lot.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, November 14, 2024 3:31 PM
To: Li, Pan2
Cc: 钟居哲 ; gcc-patches ;
jeffreyalaw ; Robin Dapp
S
Make sense and sure thing, let me file another patch for this.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, November 14, 2024 3:22 PM
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ;
jeffreyalaw ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V: Rearrange the test files for scalar SAT_ADD
> Take Maxim up on their offer, I think? It's possible the issue is latent
> so worth looking into nonetheless.
I see, I will ping Maxim later for this as I am in the middle of sth.
Pan
-Original Message-
From: Sam James
Sent: Wednesday, November 13, 2024 10:32 AM
To: L
> Take Maxim up on their offer, I think? It's possible the issue is latent
> so worth looking into nonetheless.
I see, I will ping Maxim later for this as I am in the middle of sth.
Pan
-Original Message-
From: Sam James
Sent: Wednesday, November 13, 2024 10:32 AM
To: L
No response from the compiler farm.
But due to some more discussion for the simplification on SAT, this patch is
reverted. Thus I bet this build error should be gone
up to a point. Please feel free to ping me if any issues.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, November
No response from the compiler farm.
But due to some more discussion for the simplification on SAT, this patch is
reverted. Thus I bet this build error should be gone
up to a point. Please feel free to ping me if any issues.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, November
> Just the first patch - I didn't have time to look at the second one yet.
I see, thanks a lot.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, November 12, 2024 10:39 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
Thanks Richard for reviewing.
> OK.
Sorry for disturbing, is the approval for the series or just the first patch.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, November 12, 2024 8:16 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe
matching pattern as
we discussed in previous.
It may look like below as I understanding.
if (SAT_ADD_SUPPORTED (...))
return target_implemented_expanders (...);
return fallback_expansion (..);
Pan
-Original Message-
From: Richard Biener
Sent: Friday, November 8, 2024 4:03 PM
To: Li,
if (__builtin_add_overflow (x, y, &ret)) \
return -1; \
else \
return ret;\
}
Pan
-Original Message-
From: Jeff Law
Sent: Friday, November 8, 2024 4:08 AM
To: Tamar Christina ; Li, Pan2 ;
Richard Bie
---Original Message-
From: Tamar Christina
Sent: Thursday, November 7, 2024 7:43 PM
To: Li, Pan2 ; Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: RE: [PATCH v2 01/10] Match: Simplify branch form
I see, thanks a lot.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, November 7, 2024 5:03 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2
Hi Richard,
I would like to double confirm about the doc as I am not the native speaker.
It may be referenced by all other developers and I am not sure if there is
something misleading or fuzzy.
Thanks a lot.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, October 30, 2024 7
the branchless version is
preferred in most case IMO if
they have nearly count of stmt. Not sure if it is still true during the
vectorization.
Pan
-Original Message-
From: Tamar Christina
Sent: Thursday, November 7, 2024 12:25 AM
To: Li, Pan2 ; Richard Biener
Cc: gcc-patches@gcc.gn
hese to
> straight-line code?
Make sense, we could find one form that most of us consider to be the
"cheapest".
Pan
-Original Message-----
From: Richard Biener
Sent: Wednesday, November 6, 2024 8:43 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com;
The docker multi-isa doesn't work well here, I will apply an account from
compiler farm...
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, October 30, 2024 9:32 AM
To: Maxim Kuvyrkov
Cc: Sam James ; gcc-regress...@gcc.gnu.org; Jeff Law
; juzhe.zh...@rivai.ai; ki
The docker multi-isa doesn't work well here, I will apply an account from
compiler farm...
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, October 30, 2024 9:32 AM
To: Maxim Kuvyrkov
Cc: Sam James ; gcc-regression@gcc.gnu.org; Jeff Law
; juzhe.zh...@rivai.ai; ki
_1) ... in
v2.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, October 30, 2024 5:23 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com; Andrew Pinski
Subject: R
; wouldn't it be zero as base?
Yes, the base of vec_serices should be zero.
>> +For each element index i load address is operand 1 + @var{i} * operand 2.
> the load address
Sure, will update in v2.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, October
_EXPR, type, op_0, op_1),
+build1 (NEGATE_EXPR, type,
+build1 (NOP_EXPR, type,
+build2 (LT_EXPR, boolean_type_node,
+build2 (PLUS_EXPR, type, op_0, op_1),
+
Thanks, let me have a try first and will back to you if still cannot reproduce
this.
Pan
-Original Message-
From: Maxim Kuvyrkov
Sent: Wednesday, October 30, 2024 7:39 AM
To: Li, Pan2
Cc: Sam James ; gcc-regress...@gcc.gnu.org; Jeff Law
; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Thanks, let me have a try first and will back to you if still cannot reproduce
this.
Pan
-Original Message-
From: Maxim Kuvyrkov
Sent: Wednesday, October 30, 2024 7:39 AM
To: Li, Pan2
Cc: Sam James ; gcc-regression@gcc.gnu.org; Jeff Law
; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
linaro.org
Sent: Sunday, October 27, 2024 9:58 AM
To: Li, Pan2
Cc: gcc-regress...@gcc.gnu.org
Subject: [Linaro-TCWG-CI] gcc-15-4672-gdf4af89bc3e: Failure on arm
Dear contributor, our automatic CI has detected problems related to your
patch(es). Please find some details below. If you have any
r non-len-only-masked
> variants are missing but this is OK I guess.
Yes, we can add non-masked/non-len variants when we need in future.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, October 29, 2024 6:44 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@
I see, this error may require bootstrap build. There is no aarch64 machine
currently. Let me try to find one somewhere.
Pan
-Original Message-
From: Sam James
Sent: Sunday, October 27, 2024 3:37 PM
To: Li, Pan2
Cc: gcc-regress...@gcc.gnu.org; jeffreya...@gmail.com; juzhe.zh
=arm-linux-gnueabihf \
--enable-language=c,c++ \
--enable-bootstrap \
--disable-multilib \
--with-arch=armv7-a \
--prefix=${_INSTALL_DIR}
make -j64 && make install
Any suggestions for reproducing this issue ?
Pan
-Original Message-
=arm-linux-gnueabihf \
--enable-language=c,c++ \
--enable-bootstrap \
--disable-multilib \
--with-arch=armv7-a \
--prefix=${_INSTALL_DIR}
make -j64 && make install
Any suggestions for reproducing this issue ?
Pan
-Original Message-
I see, this error may require bootstrap build. There is no aarch64 machine
currently. Let me try to find one somewhere.
Pan
-Original Message-
From: Sam James
Sent: Sunday, October 27, 2024 3:37 PM
To: Li, Pan2
Cc: gcc-regression@gcc.gnu.org; jeffreya...@gmail.com; juzhe.zh
linaro.org
Sent: Sunday, October 27, 2024 9:58 AM
To: Li, Pan2
Cc: gcc-regression@gcc.gnu.org
Subject: [Linaro-TCWG-CI] gcc-15-4672-gdf4af89bc3e: Failure on arm
Dear contributor, our automatic CI has detected problems related to your
patch(es). Please find some details below. If you have any
> Nit, space before '('.
> LGTM with that fixed and once the middle-end changes are in.
Got it, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, October 25, 2024 11:56 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.c
...@rivai.ai; Li, Pan2 ;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH 1/2] Match: Simplify unsigned scalar sat_sub(x -1) to (x -
x != 0)
On Tue, Oct 22, 2024 at 10:39 PM Li Xu wrote:
>
> From: xuli
>
> When the imm operand op1=1 in the unsigned scalar sat_sub form2 bel
--Original Message-
From: Richard Biener
Sent: Monday, October 21, 2024 8:29 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH 01/11] Match: Support form 1 for vec
chard Biener
Sent: Thursday, October 17, 2024 3:13 PM
To: Li, Pan2
Cc: Richard Sandiford ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com
Subject: Re: [PATCH v1] Internal-fn: Add new IFN mask_len_strided_load/store
On Thu, Oct 17, 2024 at 8:38 AM Li,
(unspec:RVVM1SI [
431 │ (reg:DI 0 zero)
432 │ ] UNSPEC_VUNDEF))) "strided_ld-st.c":4:22 -1
433 │ (nil))
Pan
-----Original Message-
From: Li, Pan2
Sent: Wednesday, June 5, 2024 3:50 PM
To: Richard Biener ; Richard Sandiford
Cc: gcc-pa
Thanks Kito. Just notice these some silly mistakes this morning, ;)!
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, October 15, 2024 9:45 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V
Thanks Jakub for reminder, let me eliminate the dup pattern.
Pan
-Original Message-
From: Jakub Jelinek
Sent: Monday, October 14, 2024 8:05 PM
To: Richard Biener
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
tamar.christ...@arm.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya
heapest (smallest) variant.
Got it. There are many variants but we can simplify them to the cheapest one.
I will have a try after all saturation alu supported.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, October 11, 2024 6:27 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.
refine this part after all saturation alu are
supported
(to make sure we have full picture).
Pan
-Original Message-----
From: Richard Biener
Sent: Friday, October 11, 2024 5:10 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com
Thanks richard for comments.
> Use HOST_WIDE_INT_1U instead of 1ull
> OK with that change.
Got it, will commit it with this change if no surprise from test.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, October 8, 2024 5:07 PM
To: Li, Pan2
Cc: gcc-patches@gcc.g
Thanks Robin, this depends on [PATCH 1/2] of match.pd change, will commit it
after that.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, September 24, 2024 8:40 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh
-
From: Richard Biener
Sent: Tuesday, September 24, 2024 3:42 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] Widening-Mul: Fix one ICE for SAT_SUB matching operan
Got it, thanks a lot.
Pan
-Original Message-
From: Uros Bizjak
Sent: Tuesday, September 24, 2024 3:29 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; richard.guent...@gmail.com;
tamar.christ...@arm.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp
Got it and thanks, let me rerun to make sure it works well as expected.
Pan
-Original Message-
From: Uros Bizjak
Sent: Tuesday, September 24, 2024 2:33 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; richard.guent...@gmail.com;
tamar.christ...@arm.com; juzhe.zh...@rivai.ai; kito.ch
do compile { target ia32 } }" instead.
Is there any suggestion to run the "ia32" test when configure gcc build?
I first leverage ia32 but complain UNSUPPORTED for this case.
Pan
-Original Message-
From: Uros Bizjak
Sent: Tuesday, September 24, 2024 2:17 PM
To:
bin Dapp
Sent: Thursday, September 19, 2024 9:25 PM
To: gcc-patches
Cc: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; Li, Pan2 ; rdapp@gmail.com
Subject: [PATCH] RISC-V: testsuite: Fix SELECT_VL SLP fallout.
Hi,
this fixes asm-scan fallout from
t practices for the remark "obvious"?
Like [NFC] in subject to give some hit for not-function-change, maybe take
[TBO] stand for to-be-obvious or something like that.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, September 19, 2024 4:26 PM
To: Li, Pan2 ; gcc-patches@
Thanks Richard for comments.
Will commit it with that change if no surprise from test suite.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, September 19, 2024 2:23 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch
ng a scan-asm test for something
> we can look at more directly if we're willing to add a bit more
> information into the dump file.
I see, that would be a alternative approach for the backend code-gen checking.
It may make it easier for similar cases, I think we can have a try in sho
Got, thanks Richard and will have a try in v5.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, September 18, 2024 8:06 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp
resend the v4 series for this change.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, September 12, 2024 2:51 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Sub
Committed.
Pan
From: 钟居哲
Sent: Thursday, September 12, 2024 12:40 PM
To: Bohan Lei ; gcc-patches
Cc: Li, Pan2
Subject: Re: [PATCH v2] RISC-V: Eliminate latter vsetvl when fused
LGTM
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
From: Boh
est inline the cfg match for both the case_0 and
case_1?
That may make func body grows, and we may have more cases like case_2,
case_3... etc.
If so, I will inline this to match_cond_with_binary_phi in v4.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, September 11, 2024 9
Committed, thanks Juzhe and garthlei.
Pan
From: 钟居哲
Sent: Wednesday, September 11, 2024 7:36 PM
To: gcc-patches
Cc: Li, Pan2 ; Robin Dapp ; jeffreyalaw
; kito.cheng
Subject: [PATCH 1/2] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass
Hi, garthlei.
Thanks for fixing it.
I see, you
ix should be
removed as the body of function has nothing to do with lto.
Otherwise no comments from myside, and l'd leave it to kito or juzhe.
Pan
-Original Message-
From: Jin Ma
Sent: Tuesday, September 10, 2024 1:57 PM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.
e matching types on their
> operands.
Got it, will revisit the matching I added before for possible redundant
checking.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, September 10, 2024 3:02 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh
as other
op like and/or ... etc.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, September 9, 2024 8:19 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PAT
onday, September 9, 2024 8:27 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2 1/2] Genmatch: Support control flow graph case 1 for phi
on condition
On Thu, Sep 5,
> Any comments on this patch?
I may need some time to go through all details (PS: Sorry I cannot approve
patches, leave it to juzhe or kito).
Thanks a lot for fixing this.
Pan
-Original Message-
From: Jin Ma
Sent: Monday, September 9, 2024 6:30 PM
To: Li, Pan2 ; gcc-patc
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