Sure thing, will send the v5 for CI system and commit it if no surprise.
BTW, shall we plan some refactor for expand_const_vector in next stage 1, which
grows to more than 500 lines and unfriendly for debugging up to a point.
Pan
-----Original Message-----
From: Robin Dapp <rdapp....@gmail.com>
Sent: Thursday, February 27, 2025 5:22 PM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp <rdapp....@gmail.com>
Subject: Re: [PATCH v4] RISC-V: Fix bug for expand_const_vector interleave
[PR118931]
Hi Pan,
> + poly_int64 base1_poly = rtx_to_poly_int64 (base1);
> + bool overflow_smode_p = false;
> +
> + if (!step1.is_constant ())
> + overflow_smode_p = true;
> + else
> + {
> + int elem_count = XVECLEN (src, 0);
> + uint64_t step1_val = (uint64_t)step1.to_constant ();
> + uint64_t base1_val = (uint64_t)base1_poly.to_constant ();
The casts aren't necessary anymore I suppose?
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118931-run-1.c
> @@ -0,0 +1,19 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-options "-O3 -march=rv64gcv -flto -mrvv-vector-bits=zvl" } */
Please change -flto to -fwhole-program still.
OK with these changed, thanks!
--
Regards
Robin
