[U-Boot] [PATCH v2 0/2] This series introduces the ability to override the environment offets

[Philipp Tomsich]

from the device tree by setting the following nodes in '/config':

'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
'u-boot,mmc-env-offset-redundant'
- overrides CONFIG_ENV_OFFSET_REDUND

and adds the appropriate documentation in config.txt.


Changes in v2:
- added documentation in config.txt

Philipp Tomsich (2):
  env_mmc: configure environment offsets via device tree
  doc: document u-boot,mmc-env-offset and u-boot,mmc-env-offset-redund

 common/env_mmc.c| 31 +++
 doc/device-tree-bindings/config.txt | 12 
 2 files changed, 39 insertions(+), 4 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v2 1/2] env_mmc: configure environment offsets via device tree

[Philipp Tomsich]

This introduces the ability to override the environment offets from the
device tree by setting the following nodes in '/config':
'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
'u-boot,mmc-env-offset-redundant'
- overrides CONFIG_ENV_OFFSET_REDUND

To keep with the previous logic, the CONFIG_* defines still need to
be available and the statically defined values become the defaults,
when the corresponding properties are not set in the device-tree.

Signed-off-by: Philipp Tomsich 
Acked-by: Simon Glass 

---

Changes in v2: None

 common/env_mmc.c | 31 +++
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/common/env_mmc.c b/common/env_mmc.c
index a5d14d4..65c5690 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -10,6 +10,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,15 +37,37 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_ENV_OFFSET 0
 #endif
 
-__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
+#ifdef CONFIG_OF_LIBFDT
+static inline s64 mmc_offset(int copy)
 {
-   s64 offset;
+   const char *propname = "u-boot,mmc-env-offset";
+   s64 defvalue = CONFIG_ENV_OFFSET;
 
-   offset = CONFIG_ENV_OFFSET;
-#ifdef CONFIG_ENV_OFFSET_REDUND
+#if defined(CONFIG_ENV_OFFSET_REDUND)
+   if (copy) {
+   propname = "u-boot,mmc-env-offset-redundant";
+   defvalue = CONFIG_ENV_OFFSET_REDUND;
+   }
+#endif
+
+   return fdtdec_get_config_int(gd->fdt_blob, propname, defvalue);
+}
+#else
+static inline s64 mmc_offset(int copy)
+{
+   s64 offset = CONFIG_ENV_OFFSET;
+
+#if defined(CONFIG_ENV_OFFSET_REDUND)
if (copy)
offset = CONFIG_ENV_OFFSET_REDUND;
 #endif
+   return offset;
+}
+#endif
+
+__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
+{
+   s64 offset = mmc_offset(copy);
 
if (offset < 0)
offset += mmc->capacity;
-- 
1.9.1

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[U-Boot] [PATCH v2 2/2] doc: document u-boot, mmc-env-offset and u-boot, mmc-env-offset-redund

[Philipp Tomsich]

Adding documentation on the new config properties:
   'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
   'u-boot,mmc-env-offset-redundant'
   - overrides CONFIG_ENV_OFFSET_REDUND

Signed-off-by: Philipp Tomsich 

---

Changes in v2:
- added documentation in config.txt

 doc/device-tree-bindings/config.txt | 12 
 1 file changed, 12 insertions(+)

diff --git a/doc/device-tree-bindings/config.txt 
b/doc/device-tree-bindings/config.txt
index 5640bae..12a37c7 100644
--- a/doc/device-tree-bindings/config.txt
+++ b/doc/device-tree-bindings/config.txt
@@ -20,3 +20,15 @@ u-boot,efi-partition-entries-offset
is formatted.
 
This setting will override any values configured via Kconfig.
+
+u-boot,mmc-env-offset
+u-boot,mmc-env-offset-redundant
+   If present, the values of the 'u-boot,mmc-env-offset' and/or
+   of the u-boot,mmc-env-offset-redundant' properties overrides
+   CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND, respectively,
+   for SD/MMC devices.
+
+   Values are interpreted as the offset from the start of the
+   device, specified in bytes.  It is assumed that the setting
+   will point at the beginning of a LBA and values that are not
+   LBA-aligned will be rounded up to the next LBA address.
-- 
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[U-Boot] [PATCH 0/2] With the update of the RK3399 DTS (to sync it with what the kernel uses),

[Philipp Tomsich]

the support for the Designware driver in the RK3399 needs some minor
adjustments to successfully attach:
 - the clock identifier that the simple clk driver for the RK3399 sees
   has changed (SCLK_SDMMC -> HCLK_SDMMC)
 - the 'clock-freq-min-max' property has been deprecated upstream

For the submitted update of the DTS see:
https://patchwork.ozlabs.org/patch/752192/

For the deprecation of the 'clock-freq-min-max' property, see

https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b


Philipp Tomsich (2):
  rockchip: clk: rk3399: adapt MMC clk configuration to the updated
RK3399 DTS
  rockchip: mmc: handle deprecation of 'clock-freq-min-max'

 drivers/clk/rockchip/clk_rk3399.c |  4 
 drivers/mmc/rockchip_dw_mmc.c | 20 ++--
 2 files changed, 22 insertions(+), 2 deletions(-)

-- 
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[U-Boot] [PATCH 2/2] rockchip: mmc: handle deprecation of 'clock-freq-min-max'

[Philipp Tomsich]

The 'clock-freq-min-max' property was deprecated in the upstream
(i.e. Linux) DTS bindings in favor of the 'max-frequency' property.

With the latest RK3399 DTSI does no longer include the deprecated
property and the rockchip_dw_mmc driver requiring it to be present,
the driver doesn't bind to the node in the RK3399 DTSI any longer
(thus breaking access to the SD card on the RK3399-Q7 board).

To fix this, we implement a similar logic as in the Linux driver: if
the deprecated property is present, we issue a warning (if DEBUG is
enabled); if it is missing, we require 'max-frequency' to be set and
use it to create a min/max value-pair.

See 
https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b
for the deprecation/matching change in Linux.

Signed-off-by: Philipp Tomsich 
---

 drivers/mmc/rockchip_dw_mmc.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index c36eda0..432ae20 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -76,9 +76,25 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice 
*dev)
return -EINVAL;
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  "fifo-mode");
+
+   /*
+* 'clock-freq-min-max' is deprecated
+* (see 
https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
+*/
if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
-"clock-freq-min-max", priv->minmax, 2))
-   return -EINVAL;
+"clock-freq-min-max", priv->minmax, 2)) {
+   int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "max-frequency", -EINVAL);
+
+   if (val < 0)
+   return val;
+
+   priv->minmax[0] = 40;  /* 400 kHz */
+   priv->minmax[1] = val;
+   } else {
+   debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
+   }
 #endif
return 0;
 }
-- 
1.9.1

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[U-Boot] [PATCH 1/2] rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS

[Philipp Tomsich]

The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.

With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.

Signed-off-by: Philipp Tomsich 
---

 drivers/clk/rockchip/clk_rk3399.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index ac658b9..4e807f1 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -747,6 +747,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, 
uint clk_id)
u32 div, con;
 
switch (clk_id) {
+   case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->clksel_con[16]);
break;
@@ -772,6 +773,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
int aclk_emmc = 198*MHz;
 
switch (clk_id) {
+   case HCLK_SDMMC:
case SCLK_SDMMC:
/* Select clk_sdmmc source from GPLL by default */
src_clk_div = GPLL_HZ / set_rate;
@@ -861,6 +863,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return 0;
+   case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
rate = rk3399_mmc_get_clk(priv->cru, clk->id);
@@ -898,6 +901,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong 
rate)
switch (clk->id) {
case 0 ... 63:
return 0;
+   case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
-- 
1.9.1

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Re: [U-Boot] [PATCH 07/11] i2c: Drop use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello Lokesh,

Am 25.04.2017 um 05:03 schrieb Lokesh Vutla:

Hi Simon,

On Sunday 23 April 2017 09:05 PM, Simon Glass wrote:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
---

  README   | 16 
  board/ti/am335x/board.c  |  6 +-
  board/ti/am43xx/board.c  |  3 +--


[..snip..]


diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 3e842d3187..0d2e84011d 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -67,11 +67,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev 
*)CTRL_DEVICE_BASE;
  #ifdef CONFIG_TI_I2C_BOARD_DETECT
  void do_board_detect(void)
  {
-   enable_i2c0_pin_mux();
-   i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
-   if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))


This is very early board detection code that happens in SPL. There were
common Kconfig options added for eeprom
address(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS) but
missed updating in these boards.

Instead of removing can this be updated to

-   if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+   if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+   CONFIG_EEPROM_CHIP_ADDRESS))
printf("ti_i2c_eeprom_init failed\n");
  }
  #endif


Good catch. Do you have time for testing Simons patchseries
on a real hw?

Thanks!

bye,
Heiko




-   printf("ti_i2c_eeprom_init failed\n");
+   printf("ti_i2c_eeprom_init failed\n");
  }
  #endif

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 390cc168cd..a190893450 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -42,8 +42,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev 
*)CTRL_DEVICE_BASE;
  #ifdef CONFIG_TI_I2C_BOARD_DETECT
  void do_board_detect(void)
  {
-   if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
-   printf("ti_i2c_eeprom_init failed\n");
+   printf("ti_i2c_eeprom_init failed\n");
  }
  #endif


Same as above.

Thanks and regards,
Lokesh

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Re: [U-Boot] [PATCH v2 00/22] x86: Add ACPI S3 resume support

[Bin Meng]

Hi Stefan,

On Mon, Apr 24, 2017 at 5:28 PM, Stefan Roese  wrote:
> Hi Bin,
>
> On 21.04.2017 16:24, Bin Meng wrote:
>>
>> This adds ACPI S3 (suspend to ram) resume capability in U-Boot.
>> With S3 support within U-Boot, the board wakes up and resumes to
>> OS very quickly.
>>
>> This so far is enabled and tested on Intel MinnowMax board. Please
>> check README.x86 for how to test it with a plain Linux kernel.
>> Linux (w/ or w/o SeaBIOS) and Windows 10 (w/ SeaBIOS) were tested.
>>
>> This series is available for testing at u-boot-x86/s3-working.
>
>
> Thank you very much for working on this. I've started testing this
> patchset on my congatec BayTrail SoM based board. Booting into
> a v4.11-rc based kernel with serial console works just fine.
> Suspend and resume work nicely and fast! :)
>

Thanks for testing!

> Booting Ubuntu 16.04 (kernel 4.4) with graphical interface seems to
> have some (rare) problems though. When I boot into Ubuntu with the
> correct "console=" configuration (log via serial console), suspend
> / resume seems to work fine as well - at least in the tests I did
> so far. But when I don't provide this "console=" and use "quiet"
> instead, resume does not seem to work reliably. Most of the times it
> works just fine as well, but sometimes the graphical user interface
> doesn't come up at all after resuming (display stays in power safe
> mode). The U-Boot log is the same in both cases:
>

I only have a pre-installed Ubuntu 14.04 hard disk which was installed
from U-Boot and SeaBIOS at the time when ACPI/SeaBIOS support was
added to U-Boot long time ago. So suspend/resume does not work with my
installation since I believe Ubuntu has lots of custom scripts for
helping suspend/resume. I've run the testing on this installation
though, and U-Boot did not even boot after I pressed the power button
which means my Ubuntu 14.04 might not even put the system into the
correct ACPI sleeping state. So I have to reinstall a new one.

So how about your Ubuntu 16.04 installation? Was it installed from
U-Boot? Or from original commercial BIOS? What do you mean by "display
stays in power safe mode"? Is it a black screen, or is it just
U-Boot's video output screen?

> Jumping to OS waking vector 0009a1d0
>
> And the POST debug byte is also identical (0x40).
>

These logs looks good. Nothing strange.

> Do you have any ideas, where this might come from? Could you
> perhaps check this on MinnoxMax as well, if such a setup also
> sometimes has problems with resuming? Is there anything that I could
> do to test this on my platform?
>

To match your env, I will install a 16.04 from U-Boot for testing. Can
you add the following kernel parameters for testing suspend/resume?

"console=ttyS0,115200 initcall_debug ignore_loglevel no_console_suspend"

Regards,
Bin
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Re: [U-Boot] [PATCH 07/11] i2c: Drop use of CONFIG_I2C_HARD

[Lokesh Vutla]

On Tuesday 25 April 2017 01:26 PM, Heiko Schocher wrote:
> Hello Lokesh,
> 
> Am 25.04.2017 um 05:03 schrieb Lokesh Vutla:
>> Hi Simon,
>>
>> On Sunday 23 April 2017 09:05 PM, Simon Glass wrote:
>>> Drop use of this long-deprecated option.
>>>
>>> Signed-off-by: Simon Glass 
>>> ---
>>>
>>>   README   | 16 
>>>   board/ti/am335x/board.c  |  6 +-
>>>   board/ti/am43xx/board.c  |  3 +--
>>
>> [..snip..]
>>
>>> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
>>> index 3e842d3187..0d2e84011d 100644
>>> --- a/board/ti/am335x/board.c
>>> +++ b/board/ti/am335x/board.c
>>> @@ -67,11 +67,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev
>>> *)CTRL_DEVICE_BASE;
>>>   #ifdef CONFIG_TI_I2C_BOARD_DETECT
>>>   void do_board_detect(void)
>>>   {
>>> -enable_i2c0_pin_mux();
>>> -i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
>>> -
>>> -if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
>>
>> This is very early board detection code that happens in SPL. There were
>> common Kconfig options added for eeprom
>> address(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS) but
>> missed updating in these boards.
>>
>> Instead of removing can this be updated to
>>
>> -if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
>> +if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
>> +CONFIG_EEPROM_CHIP_ADDRESS))
>>   printf("ti_i2c_eeprom_init failed\n");
>>   }
>>   #endif
> 
> Good catch. Do you have time for testing Simons patchseries
> on a real hw?

Yeah, this series breaks booting of BeagleBone Black. The above
mentioned diff
fixes it.

Thanks and regards,
Lokesh

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[U-Boot] [PATCH v7] usb: gadget: avoid variable name clipping in cb_getvar

[nicolas.le.bayon]

From: Nicolas Le Bayon 

Instead of using a fixed-size array to store variable name, preferring a
dynamic allocation treats correctly all variable name lengths.
Variable names are growing through releases and features. By this way, name
clipping is prevented.

Signed-off-by: Nicolas Le Bayon 
Reviewed-by: Marek Vasut 
Acked-by: Lukasz Majewski 
---

Changes in v2:
 - instead of using a bigger fixed size, use malloc to fit with size needs
Changes in v3:
 - v2 was an error (intermediate version), so propose a complete one
Changes in v4:
 - be more explicit and detailed in label and description fields
 - remove intermediate variable only used one time
 - be more explicit in error message
 - fix indent issue
Changes in v5:
 - drop an unuseful error() call
Changes in v6:
 - add Marek review approval
Changes in v7:
 - add Lukasz ack approval

 drivers/usb/gadget/f_fastboot.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 2160b1c..7cd6d24 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -432,9 +432,15 @@ static void cb_getvar(struct usb_ep *ep, struct 
usb_request *req)
else
strcpy(response, "FAILValue not set");
} else {
-   char envstr[32];
+   char *envstr;
 
-   snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd);
+   envstr = malloc(strlen("fastboot.") + strlen(cmd) + 1);
+   if (!envstr) {
+   fastboot_tx_write_str("FAILmalloc error");
+   return;
+   }
+
+   sprintf(envstr, "fastboot.%s", cmd);
s = getenv(envstr);
if (s) {
strncat(response, s, chars_left);
@@ -442,6 +448,8 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request 
*req)
printf("WARNING: unknown variable: %s\n", cmd);
strcpy(response, "FAILVariable not implemented");
}
+
+   free(envstr);
}
fastboot_tx_write_str(response);
 }
-- 
1.9.1

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Re: [U-Boot] sunxi: Build issue with Bananapi_M2_Ultra

[Chen-Yu Tsai]

Hi,

On Tue, Apr 25, 2017 at 1:56 PM, Jagan Teki  wrote:
> Hi,
>
> We're unable to build with buildman with gcc-4.9.x
>
>arm:  +   Bananapi_M2_Ultra
> +arm-unknown-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will
> not fit in region `.sram'
> +arm-unknown-linux-gnueabi-ld.bfd: region `.sram' overflowed by 716 bytes
> +make[2]: *** [spl/u-boot-spl] Error 1
> +make[1]: *** [spl/u-boot-spl] Error 2
>
> Any inputs?

CC-ing Andre as he's probably interested in this as well.

I normally build my stuff with Debian's 6.3 cross compiler. It seems
that people don't always use the latest stuff, So I did a comparison
between Linaro's 2016.02 5.3 and 2016.11 6.2.1 toolchains. I don't
have a 4.x toolchain at the moment.

Long story short, the latter builds successfully, while the former fails.
However, the object file sizes don't vary much between the two. I think
the real difference is that the 6.2.1 toolchain comes with the GOLD linker.
It probably does a much better job at pruning out dead code.

Appended is a list of object file sizes for the 5.3 toolchain, with
total sizes for the 6.2.1 toolchain for comparison.

A few things pop up:

  - spl/arch/arm/lib/interrupts.o
We are not using interrupts at all. Is this even necessary?
IIRC there was a patch to get rid of this from Tom (CC-ed).

  - spl/common/dlmalloc.o
Why do we still need this when we have SYS_MALLOC_SIMPLE
enabled?

  - spl/common/image.o
Almost half of this is description strings for U-boot legacy
images, which probably isn't used in SPL? Could we somehow
use macros to get rid of them?

Now I've seen people do some cool stuff to get code size down,
like using fixed size arrays for string tables, which saves a
pointer. We probably don't need to go there.


Regards
ChenYu


   textdata bss dec hex filename
296   0   0 296 128 spl/drivers/gpio/sunxi_gpio.o
   1566   0 1921758 6de spl/drivers/mmc/sunxi_mmc.o
575  28   8 611 263 spl/drivers/mmc/mmc_legacy.o
   5383   0   45387150b spl/drivers/mmc/mmc.o
922   0   0 922 39a spl/drivers/power/axp221.o
795   0   0 795 31b spl/drivers/block/blk_legacy.o
641   0   0 641 281 spl/drivers/i2c/i2c_core.o
921  44   0 965 3c5 spl/drivers/i2c/mvtwsi.o
230   0   0 230  e6 spl/drivers/serial/ns16550.o
608 240   0 848 350 spl/drivers/serial/serial_ns16550.o
619   0   8 627 273 spl/drivers/serial/serial.o
 22   0   0  22  16 spl/arch/arm/lib/eabi_compat.o
 32   0   0  32  20 spl/arch/arm/lib/lshrdi3.o
 93   0   0  93  5d spl/arch/arm/lib/cache.o
  2 200   0 202  ca spl/arch/arm/lib/spl.o
378   0   0 378 17a spl/arch/arm/lib/cache-cp15.o
160   0   0 160  a0 spl/arch/arm/lib/memset.o
 32   0   0  32  20 spl/arch/arm/lib/ashrdi3.o
 84   0   0  84  54 spl/arch/arm/lib/reloc_arm_efi.o
  4   0   0   4   4 spl/arch/arm/lib/div0.o
   1273   0   01273 4f9 spl/arch/arm/lib/interrupts.o
  0   0   0   0   0 spl/arch/arm/lib/sections.o
 96   0   0  96  60 spl/arch/arm/lib/vectors.o
372   0   0 372 174 spl/arch/arm/lib/crt0_arm_efi.o
100   0   0 100  64 spl/arch/arm/lib/crt0.o
 57   0   0  57  39 spl/arch/arm/lib/reset.o
768   0   0 768 300 spl/arch/arm/lib/lib1funcs.o
108   0   0 108  6c spl/arch/arm/lib/zimage.o
260   0   0 260 104 spl/arch/arm/lib/div64.o
 60   0   0  60  3c spl/arch/arm/lib/muldi3.o
392   0   0 392 188 spl/arch/arm/lib/uldivmod.o
736   0   0 736 2e0 spl/arch/arm/lib/memcpy.o
 32   0   0  32  20 spl/arch/arm/lib/ashldi3.o
504   0   0 504 1f8 spl/arch/arm/lib/psci-dt.o
 22   0   0  22  16 spl/arch/arm/lib/stack.o
 95   0   0  95  5f spl/arch/arm/mach-sunxi/cpu_info.o
756   0   0 756 2f4 spl/arch/arm/mach-sunxi/clock_sun6i.o
131   0   0 131  83 spl/arch/arm/mach-sunxi/dram_helpers.o
106   0   0 106  6a spl/arch/arm/mach-sunxi/clock.o
289  36   0 325 145 spl/arch/arm/mach-sunxi/board.o
106   0   0 106  6a spl/arch/arm/mach-sunxi/clock.o
289  36   0 325 145 spl/arch/arm/mach-sunxi/board.o
 52   0   0  52  34 spl/arch/arm/mach-sunxi/prcm.o
384   0   0 384 180 spl/arch/arm/mach-sunxi/rsb.o
750  64   4 818 332 spl/arch/arm/mach-sunxi/usb_phy.o
142   4   0 146  92 spl/arch/arm/

Re: [U-Boot] [PATCH v2 00/22] x86: Add ACPI S3 resume support

[Stefan Roese]

Hi Bin,

On 25.04.2017 10:02, Bin Meng wrote:



>> Booting Ubuntu 16.04 (kernel 4.4) with graphical interface seems to
>> have some (rare) problems though. When I boot into Ubuntu with the
>> correct "console=" configuration (log via serial console), suspend
>> / resume seems to work fine as well - at least in the tests I did
>> so far. But when I don't provide this "console=" and use "quiet"
>> instead, resume does not seem to work reliably. Most of the times it
>> works just fine as well, but sometimes the graphical user interface
>> doesn't come up at all after resuming (display stays in power safe
>> mode). The U-Boot log is the same in both cases:
>>
> 
> I only have a pre-installed Ubuntu 14.04 hard disk which was installed
> from U-Boot and SeaBIOS at the time when ACPI/SeaBIOS support was
> added to U-Boot long time ago. So suspend/resume does not work with my
> installation since I believe Ubuntu has lots of custom scripts for
> helping suspend/resume. I've run the testing on this installation
> though, and U-Boot did not even boot after I pressed the power button
> which means my Ubuntu 14.04 might not even put the system into the
> correct ACPI sleeping state. So I have to reinstall a new one.
> 
> So how about your Ubuntu 16.04 installation? Was it installed from
> U-Boot? Or from original commercial BIOS?

Installed via original congatec BIOS.

> What do you mean by "display
> stays in power safe mode"? Is it a black screen, or is it just
> U-Boot's video output screen?

Blank screen and the monitor does not wake up from power-safe
mode. I see the log on the serial console, since I've changed the
environment (stdio) to not use the LCD as the console in U-Boot.
U-Boot uses the console as a splash screen instead.
 
>> Jumping to OS waking vector 0009a1d0
>>
>> And the POST debug byte is also identical (0x40).
>>
> 
> These logs looks good. Nothing strange.
> 
>> Do you have any ideas, where this might come from? Could you
>> perhaps check this on MinnoxMax as well, if such a setup also
>> sometimes has problems with resuming? Is there anything that I could
>> do to test this on my platform?
>>
> 
> To match your env, I will install a 16.04 from U-Boot for testing. Can
> you add the following kernel parameters for testing suspend/resume?
> 
> "console=ttyS0,115200 initcall_debug ignore_loglevel no_console_suspend"

Ah, this brings some infos. Here the resume log:

[   49.810439] smpboot: CPU 3 is now offline
[   49.828153] PM: Calling kvm_suspend+0x0/0x30 [kvm]
[   49.833517] PM: Calling mce_syscore_suspend+0x0/0x20
[   49.839072] PM: Calling ledtrig_cpu_syscore_suspend+0x0/0x20
[   49.845404] PM: Calling acpi_processor_suspend+0x0/0x1e
[   49.851255] PM: Calling timekeeping_suspend+0x0/0x2a0
[   49.856925] PM: Calling irq_gc_suspend+0x0/0x70
[   49.861992] PM: Calling save_ioapic_entries+0x0/0x90
[   49.867738] PM: Calling i8259A_suspend+0x0/0x30
[   49.872806] PM: Calling fw_suspend+0x0/0x20
[   49.877484] PM: Calling lapic_suspend+0x0/0x1b0
��

U-Boot 2017.05-rc2-00122-gf6a9c0b4fd-dirty (Apr 24 2017 - 10:50:06 +0200)

CPU: x86_64, vendor Intel, device 30679h
DRAM:  4 GiB
MMC:   ValleyView SDHCI: 0, ValleyView SDHCI: 1, ValleyView SDHCI: 2
SF: Detected w25q64cv with page size 256 Bytes, erase size 4 KiB, total 8 MiB
Model: congatec-QEVAL20-QA3-E3845
SCSI:  SATA link 0 timeout.
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: 64bit ncq stag pm led clo pio slum part sxs 
scanning bus for devices...
  Device 0: (1:0) Vendor: ATA Prod.: SanDisk Ultra II Rev: X411
Type: Hard Disk
Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)
Found 1 device(s).
Net:   e1000: 00:13:95:1c:51:e8
   eth0: e1000#0
Jumping to OS waking vector 0009a1d0
[   49.882704] ACPI: Low-level resume complete
[   49.887483] PM: Restoring platform NVS memory
[   49.892361] PM: Calling bsp_resume+0x0/0x20
[   49.897040] PM: Calling lapic_resume+0x0/0x2b0
[   49.902035] PM: Calling irqrouter_resume+0x0/0x3f
[   49.907297] PM: Calling i8259A_resume+0x0/0x30
[   49.912393] PM: Calling i8237A_resume+0x0/0x90
[   49.917434] PM: Calling ioapic_resume+0x0/0xa0
[   49.922495] PM: Calling irq_gc_resume+0x0/0x60
[   49.927464] PM: Calling irq_pm_syscore_resume+0x0/0x20
[   49.933256] PM: Calling timekeeping_resume+0x0/0x200
[   49.938844] PM: Calling acpi_processor_resume+0x0/0x5c
[   49.944595] PM: Calling ledtrig_cpu_syscore_resume+0x0/0x20
[   49.950829] PM: Calling mce_syscore_resume+0x0/0x30
[   49.956291] PM: Calling mc_bp_resume+0x0/0x50
[   49.961193] PM: Calling kvm_resume+0x0/0x40 [kvm]
[   49.966523] Enabling non-boot CPUs ...
[   49.990192] x86: Booting SMP configuration:
[   49.994894] smpboot: Booting Node 0 Processor 1 APIC 0x2
[   50.011048]  cache: parent cpu1 should not be sleeping
[   50.017239] CPU1 is up
[   50.038380] smpboot: Booting Node 0 Processor 2 APIC 0x4
[   50.054552]  cache: parent cpu2 should not be sleeping
[   50.060685] CPU2 is up
[   50

Re: [U-Boot] [PATCH v3 0/6] sunxi: video: Add support for HDMI output on A64/H3/H5

[Maxime Ripard]

On Mon, Apr 24, 2017 at 11:54:22PM +0200, Jernej Škrabec wrote:
> Hi Maxime,
> 
> Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard napisal(a):
> > Hi Jernej,
> > 
> > On Fri, Apr 21, 2017 at 07:24:12PM +0200, Jernej Škrabec wrote:
> > > Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard napisal(a):
> > > > Hi Jernej,
> > > > 
> > > > On Mon, Mar 27, 2017 at 07:22:28PM +0200, Jernej Skrabec wrote:
> > > > > This series implements support for HDMI output. This is done using
> > > > > DM video framework and sharing the HDMI controller code with RK3288.
> > > > > 
> > > > > Patch 1 splits out TCON code which is completely reusable on
> > > > > all Allwinner SoCs.
> > > > > 
> > > > > Patch 2 converts common TCON code to use DM video compatible timing
> > > > > structure.
> > > > > 
> > > > > Patch 3 adds all necessary clocks which are needed for Display
> > > > > Engine 2, TCON and HDMI.
> > > > 
> > > > I merged all these patches...
> > > > 
> > > > > Patch 4 implement actual DE2 and HDMI driver and patch 5 disables HDMI
> > > > > on all boards which don't have it (default is on).
> > > > 
> > > > But not this one, since it creates a Kconfig warning due to the
> > > > dependency of I2C_EDID on DM_I2C.
> > > > 
> > > > I think the current state of this discussion is that the i2c driver
> > > > should be converted to the DM, which seems to be stalled at the
> > > > moment.
> > > > 
> > > > Could you take in that patch and do the minor rework that were
> > > > suggested by Simon so that we can get this in ?
> 
> Sorry I missed what was suggested by Simon?

You have the history there:
https://patchwork.ozlabs.org/patch/734375/

Maxime

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Embedded Linux and Kernel engineering
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[U-Boot] [PATCH 1/1] arm/lib/bootm.c: keep ARM v7M in thumb mode during boot_jump_linux()

[patrice.chotard]

From: Patrice Chotard 

On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.

Tested on STM32f746-disco board

Similar commit:
f3c10882f7dc8ec35993d5febe59aac01e6a
Author: Matt Porter 

Signed-off-by: Patrice Chotard 
---
 arch/arm/lib/bootm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 8125cf0..6b1d3ae 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -347,7 +347,10 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
 
kernel_entry = (void (*)(int, int, uint))images->ep;
-
+#ifdef CONFIG_CPU_V7M
+   ulong addr = (ulong)kernel_entry | 1;
+   kernel_entry = (void *)addr;
+#endif
s = getenv("machid");
if (s) {
if (strict_strtoul(s, 16, &machid) < 0) {
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 00/22] x86: Add ACPI S3 resume support

[Bin Meng]

Hi Stefan,

On Tue, Apr 25, 2017 at 4:51 PM, Stefan Roese  wrote:
> Hi Bin,
>
> On 25.04.2017 10:02, Bin Meng wrote:
>
> 
>
>>> Booting Ubuntu 16.04 (kernel 4.4) with graphical interface seems to
>>> have some (rare) problems though. When I boot into Ubuntu with the
>>> correct "console=" configuration (log via serial console), suspend
>>> / resume seems to work fine as well - at least in the tests I did
>>> so far. But when I don't provide this "console=" and use "quiet"
>>> instead, resume does not seem to work reliably. Most of the times it
>>> works just fine as well, but sometimes the graphical user interface
>>> doesn't come up at all after resuming (display stays in power safe
>>> mode). The U-Boot log is the same in both cases:
>>>
>>
>> I only have a pre-installed Ubuntu 14.04 hard disk which was installed
>> from U-Boot and SeaBIOS at the time when ACPI/SeaBIOS support was
>> added to U-Boot long time ago. So suspend/resume does not work with my
>> installation since I believe Ubuntu has lots of custom scripts for
>> helping suspend/resume. I've run the testing on this installation
>> though, and U-Boot did not even boot after I pressed the power button
>> which means my Ubuntu 14.04 might not even put the system into the
>> correct ACPI sleeping state. So I have to reinstall a new one.
>>
>> So how about your Ubuntu 16.04 installation? Was it installed from
>> U-Boot? Or from original commercial BIOS?
>
> Installed via original congatec BIOS.
>
>> What do you mean by "display
>> stays in power safe mode"? Is it a black screen, or is it just
>> U-Boot's video output screen?
>
> Blank screen and the monitor does not wake up from power-safe
> mode. I see the log on the serial console, since I've changed the
> environment (stdio) to not use the LCD as the console in U-Boot.
> U-Boot uses the console as a splash screen instead.
>

Since you were seeing black screen I guess your U-Boot was not running
the VGA BIOS for the Intel Baytrail IGD? The LCD driver is not the
Intel i915 graphics driver?

>>> Jumping to OS waking vector 0009a1d0
>>>
>>> And the POST debug byte is also identical (0x40).
>>>
>>
>> These logs looks good. Nothing strange.
>>
>>> Do you have any ideas, where this might come from? Could you
>>> perhaps check this on MinnoxMax as well, if such a setup also
>>> sometimes has problems with resuming? Is there anything that I could
>>> do to test this on my platform?
>>>
>>
>> To match your env, I will install a 16.04 from U-Boot for testing. Can
>> you add the following kernel parameters for testing suspend/resume?
>>
>> "console=ttyS0,115200 initcall_debug ignore_loglevel no_console_suspend"
>
> Ah, this brings some infos. Here the resume log:
>
> [   49.810439] smpboot: CPU 3 is now offline
> [   49.828153] PM: Calling kvm_suspend+0x0/0x30 [kvm]
> [   49.833517] PM: Calling mce_syscore_suspend+0x0/0x20
> [   49.839072] PM: Calling ledtrig_cpu_syscore_suspend+0x0/0x20
> [   49.845404] PM: Calling acpi_processor_suspend+0x0/0x1e
> [   49.851255] PM: Calling timekeeping_suspend+0x0/0x2a0
> [   49.856925] PM: Calling irq_gc_suspend+0x0/0x70
> [   49.861992] PM: Calling save_ioapic_entries+0x0/0x90
> [   49.867738] PM: Calling i8259A_suspend+0x0/0x30
> [   49.872806] PM: Calling fw_suspend+0x0/0x20
> [   49.877484] PM: Calling lapic_suspend+0x0/0x1b0
> ��
>
> U-Boot 2017.05-rc2-00122-gf6a9c0b4fd-dirty (Apr 24 2017 - 10:50:06 +0200)
>
> CPU: x86_64, vendor Intel, device 30679h
> DRAM:  4 GiB
> MMC:   ValleyView SDHCI: 0, ValleyView SDHCI: 1, ValleyView SDHCI: 2
> SF: Detected w25q64cv with page size 256 Bytes, erase size 4 KiB, total 8 MiB
> Model: congatec-QEVAL20-QA3-E3845
> SCSI:  SATA link 0 timeout.
> Target spinup took 0 ms.
> AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
> flags: 64bit ncq stag pm led clo pio slum part sxs
> scanning bus for devices...
>   Device 0: (1:0) Vendor: ATA Prod.: SanDisk Ultra II Rev: X411
> Type: Hard Disk
> Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)
> Found 1 device(s).
> Net:   e1000: 00:13:95:1c:51:e8
>eth0: e1000#0
> Jumping to OS waking vector 0009a1d0
> [   49.882704] ACPI: Low-level resume complete
> [   49.887483] PM: Restoring platform NVS memory
> [   49.892361] PM: Calling bsp_resume+0x0/0x20
> [   49.897040] PM: Calling lapic_resume+0x0/0x2b0
> [   49.902035] PM: Calling irqrouter_resume+0x0/0x3f
> [   49.907297] PM: Calling i8259A_resume+0x0/0x30
> [   49.912393] PM: Calling i8237A_resume+0x0/0x90
> [   49.917434] PM: Calling ioapic_resume+0x0/0xa0
> [   49.922495] PM: Calling irq_gc_resume+0x0/0x60
> [   49.927464] PM: Calling irq_pm_syscore_resume+0x0/0x20
> [   49.933256] PM: Calling timekeeping_resume+0x0/0x200
> [   49.938844] PM: Calling acpi_processor_resume+0x0/0x5c
> [   49.944595] PM: Calling ledtrig_cpu_syscore_resume+0x0/0x20
> [   49.950829] PM: Calling mce_syscore_resume+0x0/0x30
> [   49.956291] PM: Calling mc_bp_resume+0x0/0x50
> [   49.961193] PM: Calling kvm_resume+0x0/0x40 

Re: [U-Boot] [PATCH] sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I

[Maxime Ripard]

On Tue, Apr 25, 2017 at 01:39:51AM +0800, Icenowy Zheng wrote:
> Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other
> chips the default value is 1 like other Allwinner SoCs.
> 
> Fix this default value.
> 
> The original wrong value has lead to wrong console on H3 Orange Pi
> boards.
> 
> Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
> 
> Signed-off-by: Icenowy Zheng 

Applied, thanks!
Maxime

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Embedded Linux and Kernel engineering
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Re: [U-Boot] [PATCH 1/2] ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/Kconfig

[Maxime Ripard]

Hello Masahiro,

On Tue, Apr 25, 2017 at 01:42:06PM +0900, Masahiro Yamada wrote:
> For the consistent location of SoC-level Kconfig.
> 
> Signed-off-by: Masahiro Yamada 

This patch doesn't seem to apply, which tree did you base this on?

Thanks!
Maxime

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Re: [U-Boot] [PATCH 1/2] ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/Kconfig

[Masahiro Yamada]

Hi Maxime,

2017-04-25 18:46 GMT+09:00 Maxime Ripard :
> Hello Masahiro,
>
> On Tue, Apr 25, 2017 at 01:42:06PM +0900, Masahiro Yamada wrote:
>> For the consistent location of SoC-level Kconfig.
>>
>> Signed-off-by: Masahiro Yamada 
>
> This patch doesn't seem to apply, which tree did you base this on?
>
> Thanks!
> Maxime
>

I built up this patch on top of
http://patchwork.ozlabs.org/patch/754573/



If you apply this patch onto the latest master
(commit 3c476d8), please give -C2 option
to "git am" in order to reduce the context.




-- 
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Masahiro Yamada
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Re: [U-Boot] sunxi: Build issue with Bananapi_M2_Ultra

[Chen-Yu Tsai]

On Tue, Apr 25, 2017 at 4:46 PM, Chen-Yu Tsai  wrote:
> Hi,
>
> On Tue, Apr 25, 2017 at 1:56 PM, Jagan Teki  wrote:
>> Hi,
>>
>> We're unable to build with buildman with gcc-4.9.x
>>
>>arm:  +   Bananapi_M2_Ultra
>> +arm-unknown-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will
>> not fit in region `.sram'
>> +arm-unknown-linux-gnueabi-ld.bfd: region `.sram' overflowed by 716 bytes
>> +make[2]: *** [spl/u-boot-spl] Error 1
>> +make[1]: *** [spl/u-boot-spl] Error 2
>>
>> Any inputs?
>
> CC-ing Andre as he's probably interested in this as well.
>
> I normally build my stuff with Debian's 6.3 cross compiler. It seems
> that people don't always use the latest stuff, So I did a comparison
> between Linaro's 2016.02 5.3 and 2016.11 6.2.1 toolchains. I don't
> have a 4.x toolchain at the moment.
>
> Long story short, the latter builds successfully, while the former fails.
> However, the object file sizes don't vary much between the two. I think
> the real difference is that the 6.2.1 toolchain comes with the GOLD linker.
> It probably does a much better job at pruning out dead code.
>
> Appended is a list of object file sizes for the 5.3 toolchain, with
> total sizes for the 6.2.1 toolchain for comparison.
>
> A few things pop up:
>
>   - spl/arch/arm/lib/interrupts.o
> We are not using interrupts at all. Is this even necessary?
> IIRC there was a patch to get rid of this from Tom (CC-ed).
>
>   - spl/common/dlmalloc.o
> Why do we still need this when we have SYS_MALLOC_SIMPLE
> enabled?
>
>   - spl/common/image.o
> Almost half of this is description strings for U-boot legacy
> images, which probably isn't used in SPL? Could we somehow
> use macros to get rid of them?

Digging a bit deeper, I found that interrupts and dlmalloc were
discarded by the linker. As far as C strings go, GCC 5.3 just
dumps them all in the same section, which basically means all of
them will get included, regardless of whether they are actually
used or referenced. GCC 6 does a good job of splitting them by
function, so all the C strings in one function get allocated to
one section. If a function isn't used, it's text and rodata
sections get dropped.

In a project I worked on in the past, a solution (or workaround)
for this was to use named array (not pointer) symbols for each
string. Each string would get tied to a symbol, and -fdata-sections
would work properly with these.

IMHO upgrading to a newer toolchain is easier though.

ChenYu

> Now I've seen people do some cool stuff to get code size down,
> like using fixed size arrays for string tables, which saves a
> pointer. We probably don't need to go there.
>
>
> Regards
> ChenYu
>
>
>textdata bss dec hex filename
> 296   0   0 296 128 spl/drivers/gpio/sunxi_gpio.o
>1566   0 1921758 6de spl/drivers/mmc/sunxi_mmc.o
> 575  28   8 611 263 spl/drivers/mmc/mmc_legacy.o
>5383   0   45387150b spl/drivers/mmc/mmc.o
> 922   0   0 922 39a spl/drivers/power/axp221.o
> 795   0   0 795 31b spl/drivers/block/blk_legacy.o
> 641   0   0 641 281 spl/drivers/i2c/i2c_core.o
> 921  44   0 965 3c5 spl/drivers/i2c/mvtwsi.o
> 230   0   0 230  e6 spl/drivers/serial/ns16550.o
> 608 240   0 848 350 spl/drivers/serial/serial_ns16550.o
> 619   0   8 627 273 spl/drivers/serial/serial.o
>  22   0   0  22  16 spl/arch/arm/lib/eabi_compat.o
>  32   0   0  32  20 spl/arch/arm/lib/lshrdi3.o
>  93   0   0  93  5d spl/arch/arm/lib/cache.o
>   2 200   0 202  ca spl/arch/arm/lib/spl.o
> 378   0   0 378 17a spl/arch/arm/lib/cache-cp15.o
> 160   0   0 160  a0 spl/arch/arm/lib/memset.o
>  32   0   0  32  20 spl/arch/arm/lib/ashrdi3.o
>  84   0   0  84  54 spl/arch/arm/lib/reloc_arm_efi.o
>   4   0   0   4   4 spl/arch/arm/lib/div0.o
>1273   0   01273 4f9 spl/arch/arm/lib/interrupts.o
>   0   0   0   0   0 spl/arch/arm/lib/sections.o
>  96   0   0  96  60 spl/arch/arm/lib/vectors.o
> 372   0   0 372 174 spl/arch/arm/lib/crt0_arm_efi.o
> 100   0   0 100  64 spl/arch/arm/lib/crt0.o
>  57   0   0  57  39 spl/arch/arm/lib/reset.o
> 768   0   0 768 300 spl/arch/arm/lib/lib1funcs.o
> 108   0   0 108  6c spl/arch/arm/lib/zimage.o
> 260   0   0 260 104 spl/arch/arm/lib/div64.o
>  60   0   0  60  3c spl/arch/arm/lib/muldi3.o
> 392   0   0 392 188 spl/arch/arm/lib/uldivmod.o
> 736   0   0 736 2e0 spl/arch/arm/lib/memcpy.o
>  32   0   0  

Re: [U-Boot] orangepi_pc2: Build error

[Andre Przywara]

Hi,

On 24/04/17 07:54, Jagan Teki wrote:
> On Sat, Apr 8, 2017 at 5:01 AM, André Przywara  wrote:
>> On 07/04/17 06:10, Jagan Teki wrote:
>>
>> Hi Jagan,
>>
>>> Can you check this error on master?
>>>
>>>   COPYspl/u-boot-spl.bin
>>>   MKSUNXI spl/sunxi-spl.bin
>>> ERROR: File too large!
>>> make[1]: *** [spl/sunxi-spl.bin] Error 1
>>> make: *** [spl/u-boot-spl] Error 2
>>
>> Yeah, this is unfortunately a known issue with older compilers. I
>> believe GCC 5.x and 6.x are fine, but 4.9.x generates too large code to
>> fit in the 32KB.
>> Can you state your compiler version?
>> I believe both the distributions and Linaro should offer up-to-date
>> (cross-)compilers these days.
> 
> We usually use buildman setup, so the compiler version is 4.9.0
> ~/.buildman-toolchains/gcc-4.9.0-nolibc/
> 
> So, can you maintain/resize orangepi_pc2 wrt 4.9.0 ?

4.9.0 apparently had it's 3rd birthday last weekend ;-)
Also there are quite some bugfix releases meanwhile (4.9.4 being the
latest). And given that arm64 is a rather young architecture, a three
years old compiler is probably bad in many other ways.

So I won't invest much time in getting this particular compiler to work,
but instead rather push kernel.org to update their cross compilers. I am
about to test build GCC 6.3.0 based on the buildall script they use.

I see that there is ongoing effort to get code size down, maybe that
helps here as well, without upgrading compilers.

If you have a particular build test setup, is there any chance you can
try to install a newer compiler there? Linaro offers up-to-date compiler
packages, also distributions offer packaged cross-compilers for arm64
these days.

Cheers,
Andre.
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[U-Boot] [PATCH 1/2][v4] board: freescale: ls2080ardb: Update QIXIS code

[Priyanka Jain]

Update QIXIS related code to be executed
only if CONFIG_FSL_QIXIS flag is enabled

As per board documentation, default sysclk is 100MHz.
In case QIXIS code is not enabled,
update default sysclk value to 100MHz

Signed-off-by: Priyanka Jain 
---
 Changes for v4:
Added changes for default sysclk as 100MHz

 board/freescale/ls2080ardb/ls2080ardb.c |   21 +
 1 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index c2aa101..10e8ea4 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -23,8 +23,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
+#endif
 #include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC   0x00
@@ -58,12 +60,15 @@ unsigned long long get_qixis_addr(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_FSL_QIXIS
u8 sw;
+#endif
char buf[15];
 
cpu_name(buf);
printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_FSL_QIXIS
sw = QIXIS_READ(arch);
printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
@@ -79,7 +84,7 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
+#endif
puts("SERDES1 Reference : ");
printf("Clock1 = 156.25MHz ");
printf("Clock2 = 156.25MHz");
@@ -93,6 +98,7 @@ int checkboard(void)
 
 unsigned long get_board_sys_clk(void)
 {
+#ifdef CONFIG_FSL_QIXIS
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
switch (sysclk_conf & 0x0F) {
@@ -111,7 +117,8 @@ unsigned long get_board_sys_clk(void)
case QIXIS_SYSCLK_166:
return 1;
}
-   return ;
+#endif
+   return 1;
 }
 
 int select_i2c_ch_pca9547(u8 ch)
@@ -134,6 +141,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int config_board_mux(int ctrl_type)
 {
+#ifdef CONFIG_FSL_QIXIS
u8 reg5;
 
reg5 = QIXIS_READ(brdcfg[5]);
@@ -151,7 +159,7 @@ int config_board_mux(int ctrl_type)
}
 
QIXIS_WRITE(brdcfg[5], reg5);
-
+#endif
return 0;
 }
 
@@ -181,8 +189,9 @@ int board_init(void)
 #endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#ifdef CONFIG_FSL_QIXIS
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
+#endif
 #ifdef CONFIG_FSL_LS_PPA
ppa_init();
 #endif
@@ -319,6 +328,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 void qixis_dump_switch(void)
 {
+#ifdef CONFIG_FSL_QIXIS
int i, nr_of_cfgsw;
 
QIXIS_WRITE(cms[0], 0x00);
@@ -329,6 +339,7 @@ void qixis_dump_switch(void)
QIXIS_WRITE(cms[0], i);
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
+#endif
 }
 
 /*
@@ -339,6 +350,7 @@ void update_spd_address(unsigned int ctrl_num,
unsigned int slot,
unsigned int *addr)
 {
+#ifdef CONFIG_FSL_QIXIS
u8 sw;
 
sw = QIXIS_READ(arch);
@@ -348,4 +360,5 @@ void update_spd_address(unsigned int ctrl_num,
else if (ctrl_num == 1 && slot == 1)
*addr = SPD_EEPROM_ADDRESS3;
}
+#endif
 }
-- 
1.7.4.1


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[U-Boot] [PATCH 2/2][v4] nxp/ls2080ardb: Add QSPI-boot support

[Priyanka Jain]

QSPI-boot is verified on LS20080ARDB RevF board
with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS
can not be access, so QIXIS flag is kept disabled

Signed-off-by: Priyanka Jain 
Signed-off-by: Suresh Gupta 
---
 Changes for v4: Updated copyright
 Changes for v3: Updated README

 Changes for v2: Incorporated Sun York's comments
   Introduced another patch to update qixis related code

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |1 +
 arch/arm/dts/Makefile |2 +-
 arch/arm/dts/fsl-ls2080a-rdb-qspi.dts |   57 +
 board/freescale/ls2080ardb/README |   26 +
 configs/ls2080ardb_qspi_defconfig |   40 
 include/configs/ls2080a_common.h  |7 
 include/configs/ls2080aqds.h  |9 +
 include/configs/ls2080ardb.h  |   53 +--
 8 files changed, 184 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls2080a-rdb-qspi.dts
 create mode 100644 configs/ls2080ardb_qspi_defconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 12fd80e..4b32b2e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -163,6 +163,7 @@ endchoice
 config SYS_LS_PPA_FW_ADDR
hex "Address of PPA firmware loading from"
depends on FSL_LS_PPA
+   default 0x2040 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x4050 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x580a0 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x6050 if SYS_LS_PPA_FW_IN_XIP
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0ee4281..59366cf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
-   fsl-ls2080a-rdb.dtb
+   fsl-ls2080a-rdb.dtb fsl-ls2080a-rdb-qspi.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts 
b/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts
new file mode 100644
index 000..aa9b03d
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts
@@ -0,0 +1,57 @@
+/*
+ * NXP ls2080a RDB board device tree source for QSPI-boot
+ *
+ * Copyright (C) 2017 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+   model = "Freescale Layerscape 2080a RDB Board";
+   compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
+   aliases {
+   spi0 = &qspi;
+   spi1 = &dspi;
+   };
+};
+
+&dspi {
+   bus-num = <0>;
+   status = "okay";
+
+   dflash0: n25q512a {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <0>;
+   };
+};
+
+&qspi {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <5000>;
+   reg = <0>;
+   };
+
+   qflash1: s25fs512s@1 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <5000>;
+   reg = <1>;
+   };
+};
diff --git a/board/freescale/ls2080ardb/README 
b/board/freescale/ls2080ardb/README
index 0c9c574..c870adc 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -43,6 +43,7 @@ Memory map from core's view
 0x00__ .. 0x00_000F_   Boot Rom
 0x00_0100_ .. 0x00_0FFF_   CCSR
 0x00_1800_ .. 0x00_181F_   OCRAM
+0x00_2000_ .. 0x00_2FFF_   QSPI region #1
 0x00_3000_ .. 0x00_3FFF_   IFC region #1
 0x00_8000_ .. 0x00__   DDR region #1
 0x05_1000_ .. 0x05__   IFC region #2
@@ -68,6 +69,31 @@ Booting Options
 ---
 a) NOR boot
 b) NAND boot
+c) QSPI boot
+
+cfg_rcw_src switches needs to be changed for booting from different option.
+Refer to board documentation for correct switch setting.
+
+QSPI boot details
+===
+Supported only for
+ LS2080/LS2088ARDB RevF board with LS2088A SoC.
+
+Images needs to be copied to QSPI flash
+as per memory map given below.
+
+Memory map for QSPI flash
+-
+Image  Flash Offset
+RCW+PBI0x
+Boot firmware (U-Boot) 0x0010
+Boot firmware Environme

[U-Boot] [PATCH v7 00/16] Add Intel Arria 10 SoC support

[Ley Foon Tan]

This is the 7th version of patchset to adds support for Intel Arria 10 SoC.
This is initial patchset enables the basic support for Arria 10 and other
features will come after this.

This series is rebased on top of 
http://git.denx.de/?p=u-boot/u-boot-socfpga.git.

v6 -> v7 changes:
-
-  Revert change in socfpga_bridges_reset() for Gen5.

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240052.html
[v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg241249.html
[v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg243107.html
[v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg243815.html
[v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg244930.html
[v6]: https://www.mail-archive.com/u-boot@lists.denx.de/msg245911.html

Ley Foon Tan (16):
  arm: socfpga: Restructure clock manager driver
  arm: socfpga: Restructure reset manager driver
  arm: socfpga: Restructure system manager
  arm: socfpga: Restructure misc driver
  arm: socfpga: Add A10 macros
  arm: socfpga: Add reset driver support for Arria 10
  arm: socfpga: Add clock driver for Arria 10
  arm: socfpga: Add system manager for Arria 10
  arm: socfpga: Add sdram header file for Arria 10
  arm: socfpga: Add pinmux for Arria 10
  arm: socfpga: Add misc support for Arria 10
  arm: dts: Add dts and dtsi for Arria 10
  arm: socfpga: Add SPL support for Arria 10
  arm: socfpga: Add config and defconfig for Arria 10
  arm: socfpga: Add board files for the Arria10
  arm: socfpga: Enable build for Arria 10

 arch/arm/dts/Makefile  |1 +
 arch/arm/dts/socfpga_arria10.dtsi  |  869 
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |   38 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |  481 +
 arch/arm/mach-socfpga/Kconfig  |   10 +
 arch/arm/mach-socfpga/Makefile |   41 +-
 arch/arm/mach-socfpga/clock_manager.c  |  525 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 1096 
 .../{clock_manager.c => clock_manager_gen5.c}  |  137 +--
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |8 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  317 +-
 .../include/mach/clock_manager_arria10.h   |  224 
 .../mach/{clock_manager.h => clock_manager_gen5.h} |  151 +--
 arch/arm/mach-socfpga/include/mach/misc.h  |   31 +
 arch/arm/mach-socfpga/include/mach/pinmux.h|   17 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   50 +-
 .../include/mach/reset_manager_arria10.h   |  147 +++
 .../mach-socfpga/include/mach/reset_manager_gen5.h |   50 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |  380 +++
 .../arm/mach-socfpga/include/mach/system_manager.h |  202 ++--
 .../include/mach/system_manager_arria10.h  |   81 ++
 .../{system_manager.h => system_manager_gen5.h}|   39 +-
 arch/arm/mach-socfpga/misc.c   |  363 +--
 arch/arm/mach-socfpga/misc_arria10.c   |  259 +
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c}  |  152 +--
 arch/arm/mach-socfpga/pinmux_arria10.c |   96 ++
 arch/arm/mach-socfpga/reset_manager.c  |   93 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  383 +++
 .../{reset_manager.c => reset_manager_gen5.c}  |   48 +-
 arch/arm/mach-socfpga/spl.c|   56 +-
 .../{system_manager.c => system_manager_gen5.c}|6 +-
 board/altera/arria10-socdk/Kconfig |   18 +
 board/altera/arria10-socdk/Makefile|7 +
 board/altera/arria10-socdk/socfpga.c   |7 +
 configs/socfpga_arria10_defconfig  |   29 +
 include/configs/socfpga_arria10_socdk.h|   66 ++
 include/configs/socfpga_common.h   |   21 +-
 include/dt-bindings/reset/altr,rst-mgr-a10.h   |  110 ++
 38 files changed, 4817 insertions(+), 1792 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (85%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{clock_manager.h => 
clock_manager_gen5.h} (79%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
 copy arch/arm/ma

[U-Boot] [PATCH v7 01/16] arm: socfpga: Restructure clock manager driver

[Ley Foon Tan]

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   3 +-
 arch/arm/mach-socfpga/clock_manager.c  | 515 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 137 ++
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 316 +
 .../mach/{clock_manager.h => clock_manager_gen5.h} | 151 +++---
 arch/arm/mach-socfpga/spl.c|   3 +-
 6 files changed, 149 insertions(+), 976 deletions(-)
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (85%)
 copy arch/arm/mach-socfpga/include/mach/{clock_manager.h => 
clock_manager_gen5.h} (79%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b76de4c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -13,7 +13,8 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o 
clock_manager.o \
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
+  clock_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 29e18f8..8051995 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,10 +1,11 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include 
+#include 
 #include 
 #include 
 
@@ -13,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+void cm_wait_for_lock(u32 mask)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
+   u32 inter_val;
+   u32 retry = 0;
do {
inter_val = readl(&clock_manager_base->inter) & mask;
if (inter_val == mask)
@@ -29,510 +30,10 @@ static void cm_wait_for_lock(uint32_t mask)
 }
 
 /* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
+int cm_wait_for_fsm(void)
 {
-   while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
-
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, &clock_manager_base->bypass);
-   cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, &clock_manager_base->ctrl);
-   cm_wait_for_fsm();
-}
-
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
-{
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
-
-   writel(value, reg_address);
-
-   while (readl(reg_address) & mask)
-   ;
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * Assert/deassert outreset all.
- * Take all pll's out of bypass
- * Clear safe mode
- * set source main and peripheral clocks
- * Ungate clocks
- */
-
-void cm_basic_init(const struct cm_config * const cfg)
-{
-   unsigned long end;
-
-   /* Start by being paranoid and gate all sw managed clocks */
-
-   /*
-* We need to disable nandclk
-* and then do another apb access before disabling
-* gatting off the rest of the periperal clocks.
-*/
-   writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-   readl(&clock_manager_base->per_pll.en),
-   &clock_manager_base->per_pll.en);
-
-   /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE

[U-Boot] [PATCH v7 02/16] arm: socfpga: Restructure reset manager driver

[Ley Foon Tan]

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |  2 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 48 ++-
 .../mach-socfpga/include/mach/reset_manager_gen5.h | 50 
 arch/arm/mach-socfpga/reset_manager.c  | 93 +-
 .../{reset_manager.c => reset_manager_gen5.c}  | 48 +--
 5 files changed, 82 insertions(+), 159 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (76%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b76de4c..97819ac 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o
+  clock_manager_gen5.o 
reset_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..7592e11 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,34 +1,17 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef_RESET_MANAGER_H_
-#define_RESET_MANAGER_H_
+#ifndef _RESET_MANAGER_H_
+#define _RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
-void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-   u32 status;
-   u32 ctrl;
-   u32 counts;
-   u32 padding1;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;
-   u32 per2_mod_reset;
-   u32 brg_mod_reset;
-   u32 misc_mod_reset;
-   u32 padding2[12];
-   u32 tstscratch;
-};
-
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
@@ -55,28 +38,11 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
-/*
- * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... permodrst
- * 2 ... per2modrst
- * 3 ... brgmodrst
- * 4 ... miscmodrst
- */
-#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
-#define RSTMGR_NANDRSTMGR_DEFINE(1, 4)
-#define RSTMGR_QSPIRSTMGR_DEFINE(1, 5)
-#define RSTMGR_L4WD0   RSTMGR_DEFINE(1, 6)
-#define RSTMGR_OSC1TIMER0  RSTMGR_DEFINE(1, 8)
-#define RSTMGR_UART0   RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 18)
-#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 19)
-#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
-#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
-#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include 
+#endif
+
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
new file mode 100644
index 000..6d9cffe
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _RESET_MANAGER_GEN5_H_
+#define _RESET_MANAGER_GEN5_H_
+
+#include 
+
+void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 ctrl;
+   u32 counts;
+   u32 padding1;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;
+   u32 per2_mod_reset;
+   u32 brg_mod_reset;
+   u32 misc_mod_reset;
+   u32 padding2[12];
+   u32 tstscratch;
+};
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NANDRSTMGR_DEFIN

[U-Boot] [PATCH v7 04/16] arm: socfpga: Restructure misc driver

[Ley Foon Tan]

Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.

Change all uint32_t_to u32.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|   2 +-
 arch/arm/mach-socfpga/include/mach/misc.h |  25 ++
 arch/arm/mach-socfpga/misc.c  | 363 ++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 152 ++-
 4 files changed, 61 insertions(+), 481 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (72%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4980e51..e83da2e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
   clock_manager_gen5.o 
reset_manager_gen5.o \
-  system_manager_gen5.o
+  misc_gen5.o system_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..f344749
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+
+struct bsel {
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void);
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..00eff90 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -20,20 +21,21 @@
 #include 
 #include 
 
-#include 
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bsel bsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -72,207 +74,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   u32 physhift, reset;
-
-   if (of_reset_id == EMAC0_RESET) {
-   physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-   reset = SOCFPGA_RESET(EMAC0);
-   } else if (of_reset_id == EMAC1_RESET) {
-   physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-   reset = SOCFPGA_RESET(EMAC1);
-   } else {
-   printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
-   return;
-   }
-
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
-   /* configure to PHY interface select choosed */
-   setbits_le32(&sysmgr_regs->emacgrp_ctrl,
-phymode << physhift);
-
-   /* Release the EMAC controller from reset */
-   socfpga_per_reset(reset, 0);
-}
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-   if (!phymode)
-   return -EINVAL;
-
-   if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
-

[U-Boot] [PATCH v7 06/16] arm: socfpga: Add reset driver support for Arria 10

[Ley Foon Tan]

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   2 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h   | 147 
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 383 +
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 110 ++
 5 files changed, 644 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e83da2e..d81f003 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,6 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 7592e11..6591745 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -43,6 +43,8 @@ void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
new file mode 100644
index 000..7922db8
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _RESET_MANAGER_ARRIA10_H_
+#define _RESET_MANAGER_ARRIA10_H_
+
+#include 
+
+void socfpga_watchdog_disable(void);
+void socfpga_reset_deassert_noc_ddr_scheduler(void);
+int socfpga_is_wdt_in_reset(void);
+void socfpga_emac_manage_reset(ulong emacbase, u32 state);
+int socfpga_reset_deassert_bridges_handoff(void);
+void socfpga_reset_assert_fpga_connected_peripherals(void);
+void socfpga_reset_deassert_osc1wd0(void);
+void socfpga_reset_uart(int assert);
+int socfpga_bridges_reset(int enable);
+
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpumodrst;
+   u32 per0modrst;
+   u32 per1modrst;
+   u32 brgmodrst;
+   u32 sysmodrst;
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_NANDRSTMGR_DEFINE(1, 5)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSKBIT(0)
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSKBIT(2)
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
+#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
+#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MS

[U-Boot] [PATCH v7 07/16] arm: socfpga: Add clock driver for Arria 10

[Ley Foon Tan]

Add clock driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |3 +-
 arch/arm/mach-socfpga/clock_manager.c  |   10 +
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 1096 
 arch/arm/mach-socfpga/include/mach/clock_manager.h |3 +
 .../include/mach/clock_manager_arria10.h   |  224 
 5 files changed, 1335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d81f003..c494930 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,7 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+   reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 8051995..cb6ae03 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -19,7 +19,12 @@ void cm_wait_for_lock(u32 mask)
u32 inter_val;
u32 retry = 0;
do {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(&clock_manager_base->inter) & mask;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   inter_val = readl(&clock_manager_base->stat) & mask;
+#endif
+   /* Wait for stable lock */
if (inter_val == mask)
retry++;
else
@@ -44,7 +49,12 @@ int set_cpu_clk_info(void)
 
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
gd->bd->bi_dsp_freq = 0;
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
return 0;
 }
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
new file mode 100644
index 000..482b854
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -0,0 +1,1096 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 eosc1_hz;
+static u32 cb_intosc_hz;
+static u32 f2s_free_hz;
+static u32 cm_l4_main_clk_hz;
+static u32 cm_l4_sp_clk_hz;
+static u32 cm_l4_mp_clk_hz;
+static u32 cm_l4_sys_free_clk_hz;
+
+struct mainpll_cfg {
+   u32 vco0_psrc;
+   u32 vco1_denom;
+   u32 vco1_numer;
+   u32 mpuclk;
+   u32 mpuclk_cnt;
+   u32 mpuclk_src;
+   u32 nocclk;
+   u32 nocclk_cnt;
+   u32 nocclk_src;
+   u32 cntr2clk_cnt;
+   u32 cntr3clk_cnt;
+   u32 cntr4clk_cnt;
+   u32 cntr5clk_cnt;
+   u32 cntr6clk_cnt;
+   u32 cntr7clk_cnt;
+   u32 cntr7clk_src;
+   u32 cntr8clk_cnt;
+   u32 cntr9clk_cnt;
+   u32 cntr9clk_src;
+   u32 cntr15clk_cnt;
+   u32 nocdiv_l4mainclk;
+   u32 nocdiv_l4mpclk;
+   u32 nocdiv_l4spclk;
+   u32 nocdiv_csatclk;
+   u32 nocdiv_cstraceclk;
+   u32 nocdiv_cspdbclk;
+};
+
+struct perpll_cfg {
+   u32 vco0_psrc;
+   u32 vco1_denom;
+   u32 vco1_numer;
+   u32 cntr2clk_cnt;
+   u32 cntr2clk_src;
+   u32 cntr3clk_cnt;
+   u32 cntr3clk_src;
+   u32 cntr4clk_cnt;
+   u32 cntr4clk_src;
+   u32 cntr5clk_cnt;
+   u32 cntr5clk_src;
+   u32 cntr6clk_cnt;
+   u32 cntr6clk_src;
+   u32 cntr7clk_cnt;
+   u32 cntr8clk_cnt;
+   u32 cntr8clk_src;
+   u32 cntr9clk_cnt;
+   u32 emacctl_emac0sel;
+   u32 emacctl_emac1sel;
+   u32 emacctl_emac2sel;
+   u32 gpiodiv_gpiodbclk;
+};
+
+struct alteragrp_cfg {
+   u32 nocclk;
+   u32 mpuclk;
+};
+
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg)
+{
+   if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
+(u32 *)cfg, cfg_len)) {
+   /* could not find required property */
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int of_get_input_clks(const void *blob, int node, u32 *val)
+{
+   *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
+   if (!*val)
+   return -EINVAL;
+
+   return 0;
+}
+
+static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
+ struct perpll_cfg *per_cfg,
+ 

[U-Boot] [PATCH v7 05/16] arm: socfpga: Add A10 macros

[Ley Foon Tan]

Add i2c, timer and other A10 macros.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..7818aa5 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -29,17 +29,23 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
-- 
1.8.2.3

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[U-Boot] [PATCH v7 09/16] arm: socfpga: Add sdram header file for Arria 10

[Ley Foon Tan]

Add sdram header file for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
new file mode 100644
index 000..1d7b7c1
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
+#define _SOCFPGA_SDRAM_ARRIA10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   u32 caltiming5;
+   u32 caltiming6;
+   u32 caltiming7;
+   u32 caltiming8;
+   u32 caltiming9;
+   u32 caltiming10;
+   u32 dramaddrw;
+   u32 sideband0;
+   u32 sideband1;
+   u32 sideband2;
+   u32 sideband3;
+   u32 si

[U-Boot] [PATCH v7 08/16] arm: socfpga: Add system manager for Arria 10

[Ley Foon Tan]

Add system manager register struct and macros for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 74 +---
 .../include/mach/system_manager_arria10.h  | 81 ++
 2 files changed, 144 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 30f0bbe..e6d4280 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,18 +7,18 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
-#define SYSMGR_ECC_OCRAM_EN(1 << 0)
-#define SYSMGR_ECC_OCRAM_SERR  (1 << 3)
-#define SYSMGR_ECC_OCRAM_DERR  (1 << 4)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
+#define SYSMGR_ECC_OCRAM_ENBIT(0)
+#define SYSMGR_ECC_OCRAM_SERR  BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR  BIT(4)
 #define SYSMGR_FPGAINTF_USEFPGA0x1
-#define SYSMGR_FPGAINTF_SPIM0  (1 << 0)
-#define SYSMGR_FPGAINTF_SPIM1  (1 << 1)
-#define SYSMGR_FPGAINTF_EMAC0  (1 << 2)
-#define SYSMGR_FPGAINTF_EMAC1  (1 << 3)
-#define SYSMGR_FPGAINTF_NAND   (1 << 4)
-#define SYSMGR_FPGAINTF_SDMMC  (1 << 5)
+#define SYSMGR_FPGAINTF_SPIM0  BIT(0)
+#define SYSMGR_FPGAINTF_SPIM1  BIT(1)
+#define SYSMGR_FPGAINTF_EMAC0  BIT(2)
+#define SYSMGR_FPGAINTF_EMAC1  BIT(3)
+#define SYSMGR_FPGAINTF_NAND   BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC  BIT(5)
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
 
@@ -31,8 +31,60 @@
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0)
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   BIT(4)
+#define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8)
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  BIT(16)
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  BIT(20)
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  BIT(24)
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK  BIT(0)
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK  BIT(1)
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK  BIT(1)
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
new file mode 100644
index 000..f235aba
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SYSTEM_MANAGER_ARRIA10_H_
+#define _SYSTEM_MANAGER_ARRIA10_H_
+
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac[3];
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_va

[U-Boot] [PATCH v7 13/16] arm: socfpga: Add SPL support for Arria 10

[Ley Foon Tan]

Add SPL support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/spl.c | 53 +++--
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 0064fc8..71bae82 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -19,23 +19,32 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -183,3 +193,42 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void spl_board_init(void)
+{
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   socfpga_reset_uart(0);
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   socfpga_watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   socfpga_reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
+#endif
-- 
1.8.2.3

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[U-Boot] [PATCH v7 03/16] arm: socfpga: Restructure system manager

[Ley Foon Tan]

Restructure system manager in the preparation to support A10.
No functional change.

Change uint32_t to u32.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   5 +-
 .../arm/mach-socfpga/include/mach/system_manager.h | 128 ++---
 .../{system_manager.h => system_manager_gen5.h}|  39 +--
 .../{system_manager.c => system_manager_gen5.c}|   6 +-
 4 files changed, 22 insertions(+), 156 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{system_manager.h => 
system_manager_gen5.h} (73%)
 rename arch/arm/mach-socfpga/{system_manager.c => system_manager_gen5.c} (94%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 97819ac..4980e51 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -7,14 +7,15 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o 
reset_manager_gen5.o
+  clock_manager_gen5.o 
reset_manager_gen5.o \
+  system_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..30f0bbe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -1,120 +1,11 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2017 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef_SYSTEM_MANAGER_H_
-#define_SYSTEM_MANAGER_H_
-
-#ifndef __ASSEMBLY__
-
-void sysmgr_pinmux_init(void);
-void sysmgr_config_warmrstcfgio(int enable);
-
-void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
-#endif
-
-struct socfpga_system_manager {
-   /* System Manager Module */
-   u32 siliconid1; /* 0x00 */
-   u32 siliconid2;
-   u32 _pad_0x8_0xf[2];
-   u32 wddbg;  /* 0x10 */
-   u32 bootinfo;
-   u32 hpsinfo;
-   u32 parityinj;
-   /* FPGA Interface Group */
-   u32 fpgaintfgrp_gbl;/* 0x20 */
-   u32 fpgaintfgrp_indiv;
-   u32 fpgaintfgrp_module;
-   u32 _pad_0x2c_0x2f;
-   /* Scan Manager Group */
-   u32 scanmgrgrp_ctrl;/* 0x30 */
-   u32 _pad_0x34_0x3f[3];
-   /* Freeze Control Group */
-   u32 frzctrl_vioctrl;/* 0x40 */
-   u32 _pad_0x44_0x4f[3];
-   u32 frzctrl_hioctrl;/* 0x50 */
-   u32 frzctrl_src;
-   u32 frzctrl_hwctrl;
-   u32 _pad_0x5c_0x5f;
-   /* EMAC Group */
-   u32 emacgrp_ctrl;   /* 0x60 */
-   u32 emacgrp_l3master;
-   u32 _pad_0x68_0x6f[2];
-   /* DMA Controller Group */
-   u32 dmagrp_ctrl;/* 0x70 */
-   u32 dmagrp_persecurity;
-   u32 _pad_0x78_0x7f[2];
-   /* Preloader (initial software) Group */
-   u32 iswgrp_handoff[8];  /* 0x80 */
-   u32 _pad_0xa0_0xbf[8];  /* 0xa0 */
-   /* Boot ROM Code Register Group */
-   u32 romcodegrp_ctrl;/* 0xc0 */
-   u32 romcodegrp_cpu1startaddr;
-   u32 romcodegrp_initswstate;
-   u32 romcodegrp_initswlastld;
-   u32 romcodegrp_bootromswstate;  /* 0xd0 */
-   u32 __pad_0xd4_0xdf[3];
-   /* Warm Boot from On-Chip RAM Group */
-   u32 romcodegrp_warmramgrp_enable;   /* 0xe0 */
-   u32 romcodegrp_warmramgrp_datastart;
-   u32 romcodegrp_warmramgrp_length;
-   u32 romcodegrp_warmramgrp_execution;
-   u32 romcodegrp_warmramgrp_crc;  /* 0xf0 */
-   u32 __pad_0xf4_0xff[3];
-   /* Boot ROM Hardware Register Group */
-   u32 romhwgrp_ctrl;  /* 0x100 */
-   u32 _pad_0x104_0x107;
-   /* SDMMC Controller Group */
-   u32 sdmmcgrp_ctrl;
-   u32 sdmmcgrp_l3master;
-   /* NAND Flash Controller Register Group */
-   u32 nandgrp_bootstrap;  /* 0x110 */
-   u32 nandgrp_l3master;
-   /* USB Controller Group */
-   u32 usbgrp_l3master;
-   u32 _pad_0x11c_0x13f[9];
-   /* ECC Management Register Group */
-   u32 eccgrp_l2; 

[U-Boot] [PATCH v7 11/16] arm: socfpga: Add misc support for Arria 10

[Ley Foon Tan]

Add misc support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile|   1 +
 arch/arm/mach-socfpga/include/mach/misc.h |   6 +
 arch/arm/mach-socfpga/misc_arria10.c  | 259 ++
 3 files changed, 266 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 503b79f..4ce8eac 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -12,6 +12,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
pinmux_arria10.o\
+   misc_arria10.o  \
reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index f344749..0b65783 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -22,4 +22,10 @@ void socfpga_fpga_add(void);
 static inline void socfpga_fpga_add(void) {}
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
new file mode 100644
index 000..9d751f6
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3  0x08
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3  0x68
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7  0x18
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7  0x78
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3  0x98
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static struct pl310_regs *const pl310 =
+   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+#endif
+
+static struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode)
+{
+   u32 reset;
+
+   if (of_reset_id == EMAC0_RESET) {
+   reset = SOCFPGA_RESET(EMAC0);
+   } else if (of_reset_id == EMAC1_RESET) {
+   reset = SOCFPGA_RESET(EMAC1);
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+   } else {
+   printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+   return;
+   }
+
+   clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+
+   /* Release the EMAC controller from reset */
+   socfpga_per_reset(reset, 0);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, &noc_fw_ocram_base->region0);
+   writel(0x1, &noc_fw_ocram_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, &pl310->pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#else
+int arch_early_init_r(void)
+{
+   return 0;
+}
+#endif
+
+/*
+ * This function looking the 1st encounter UART peripheral,
+ * and then return its offset of the dedicated/shared IO pin
+ * mux. offset value (zero and above).
+ */
+static int find_peripheral_uart(const void *blob,
+   int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr = 0;
+   fdt_size_t size;
+   const u32 *cell;
+   u3

[U-Boot] [PATCH v7 10/16] arm: socfpga: Add pinmux for Arria 10

[Ley Foon Tan]

Add pinmux support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile  |  1 +
 arch/arm/mach-socfpga/include/mach/pinmux.h | 17 +
 arch/arm/mach-socfpga/pinmux_arria10.c  | 96 +
 3 files changed, 114 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c494930..503b79f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -11,6 +11,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+   pinmux_arria10.o\
reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..563a3db
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+#define PINMUX_UART0xD
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c 
b/arch/arm/mach-socfpga/pinmux_arria10.c
new file mode 100644
index 000..69d6a92
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux_arria10.c
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int do_pinctr_pin(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
+   if (!cell || len <= 0)
+   return -EFAULT;
+
+   debug("%p %d\n", cell, len);
+   for (; len > 0; len -= (2 * sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   return -EFAULT;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return -EINVAL;
+
+   node_name = fdt_get_name(blob, child, &len);
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name))
+   return do_pinctr_pin(blob, child, node_name);
+
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, &len);
+   }
+
+   return -EFAULT;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+   if (node < 0)
+   return -EINVAL;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return -EFAULT;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return -EFAULT;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+   if (node < 0)
+   return -EINVAL;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return -EFAULT;
+
+   return 0;
+}
-- 
1.8.2.3

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[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

This was rotting in for too long, might as well push it upstream ...

The following changes since commit 3c476d841daa491f87c8f07851038afbdf4d90a8:

  Merge git://git.denx.de/u-boot-fsl-qoriq (2017-04-18 11:36:06 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to 6bd041f00d5d80761852eae1ecb7879a27f3c289:

  arm: socfpga: add cyclone5 based de10-nano board (2017-04-25 12:46:44
+0200)


Dalon Westergreen (1):
  arm: socfpga: add cyclone5 based de10-nano board

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts |  68 ++
 arch/arm/mach-socfpga/Kconfig   |   7 +
 board/terasic/de10-nano/MAINTAINERS |   5 +
 board/terasic/de10-nano/Makefile|   9 ++
 board/terasic/de10-nano/qts/iocsr_config.h  | 660

 board/terasic/de10-nano/qts/pinmux_config.h | 219
+++
 board/terasic/de10-nano/qts/pll_config.h|  85 
 board/terasic/de10-nano/qts/sdram_config.h  | 344

 board/terasic/de10-nano/socfpga.c   |   6 +
 configs/socfpga_de10_nano_defconfig |  59 +
 include/configs/socfpga_de10_nano.h |  33 +
 12 files changed, 1496 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_nano.dts
 create mode 100644 board/terasic/de10-nano/MAINTAINERS
 create mode 100644 board/terasic/de10-nano/Makefile
 create mode 100644 board/terasic/de10-nano/qts/iocsr_config.h
 create mode 100644 board/terasic/de10-nano/qts/pinmux_config.h
 create mode 100644 board/terasic/de10-nano/qts/pll_config.h
 create mode 100644 board/terasic/de10-nano/qts/sdram_config.h
 create mode 100644 board/terasic/de10-nano/socfpga.c
 create mode 100644 configs/socfpga_de10_nano_defconfig
 create mode 100644 include/configs/socfpga_de10_nano.h
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[U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit 3c476d841daa491f87c8f07851038afbdf4d90a8:

  Merge git://git.denx.de/u-boot-fsl-qoriq (2017-04-18 11:36:06 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to 83cb46c286beb5406aaed2e0d5895719717804b3:

  ehci-ppc4xx: Prepare for usage of readl()/writel() accessors
(2017-04-25 12:50:13 +0200)


Alexey Brodkin (1):
  ehci-ppc4xx: Prepare for usage of readl()/writel() accessors

Heinrich Schuchardt (2):
  musb: properly detect failed initialization of controller
  usb: musb: avoid out of bound access in udc_setup_ep

 drivers/usb/host/ehci-ppc4xx.c| 1 +
 drivers/usb/musb-new/musb_uboot.c | 2 +-
 drivers/usb/musb/musb_udc.c   | 4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)
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[U-Boot] [PATCH v7 14/16] arm: socfpga: Add config and defconfig for Arria 10

[Ley Foon Tan]

Add config and defconfig for the Arria10 and update socfpga_common.h.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 configs/socfpga_arria10_defconfig   | 29 +++
 include/configs/socfpga_arria10_socdk.h | 66 +
 include/configs/socfpga_common.h| 21 ---
 3 files changed, 111 insertions(+), 5 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..46bda47
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..7ea780b
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,66 @@
+/*
+ *  Copyright (C) 2015-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+/* Booting Linux */
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x4000
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* The rest of the configuration is shared */
+#include 
+
+#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 107c6d5..da7e4ad 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -32,9 +32,13 @@
 #define CONFIG_SYS_MALLOC_LEN  (64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR   0x
 #define CONFIG_SYS_INIT_RAM_SIZE   0x1
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR   0xFFE0
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4 /* 256KB */
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET  \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR\
@@ -101,13 +105,14 @@
 /*
  * FPGA Driver
  */
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT  1
 #endif
-
+#endif
 /*
  * L4 OSC1 Timer 0
  */
@@ -207,11 +212,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE-4
-#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART0_ADDRESS
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK 100
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550_CLK 1
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_NS16550_CLK 5000
 #endif
 #define CONFIG_CONS_INDEX

[U-Boot] [PATCH v7 12/16] arm: dts: Add dts and dtsi for Arria 10

[Ley Foon Tan]

Device tree files for Arria 10

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/socfpga_arria10.dtsi  | 869 +
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  38 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 481 
 4 files changed, 1389 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 68d2791..cc31ae9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb 
\
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
+   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb\
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..377700d
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,869 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = &gmac0;
+   ethernet1 = &gmac1;
+   ethernet2 = &gmac2;
+   serial0 = &uart0;
+   serial1 = &uart1;
+   timer0 = &timer0;
+   timer1 = &timer1;
+   timer2 = &timer2;
+   timer3 = &timer3;
+   spi0 = &spi0;
+   spi1 = &spi1;
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <&L2>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <&L2>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <&intc>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clock

[U-Boot] [PATCH v7 16/16] arm: socfpga: Enable build for Arria 10

[Ley Foon Tan]

Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Kconfig  | 10 +
 arch/arm/mach-socfpga/Makefile | 46 ++
 2 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9bfee04..b36ffb1 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -37,6 +37,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -49,6 +52,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
@@ -94,6 +101,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -106,6 +114,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -119,6 +128,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4ce8eac..41b779c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,28 +2,48 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2017 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
-  fpga_manager.o board.o
+obj-y  += board.o
+obj-y  += clock_manager.o
+obj-y  += fpga_manager.o
+obj-y  += misc.o
+obj-y  += reset_manager.o
+obj-y  += timer.o
 
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
-   pinmux_arria10.o\
-   misc_arria10.o  \
-   reset_manager_arria10.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += clock_manager_gen5.o
+obj-y  += misc_gen5.o
+obj-y  += reset_manager_gen5.o
+obj-y  += scan_manager.o
+obj-y  += system_manager_gen5.o
+obj-y  += wrap_pll_config.o
+endif
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += clock_manager_arria10.o
+obj-y  += misc_arria10.o
+obj-y  += pinmux_arria10.o
+obj-y  += reset_manager_arria10.o
+endif
 
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += freeze_controller.o
+obj-y  += wrap_iocsr_config.o
+obj-y  += wrap_pinmux_config.o
+obj-y  += wrap_sdram_config.o
+endif
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  clock_manager_gen5.o 
reset_manager_gen5.o \
-  misc_gen5.o system_manager_gen5.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
-- 
1.8.2.3

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[U-Boot] [PATCH v7 15/16] arm: socfpga: Add board files for the Arria10

[Ley Foon Tan]

Add support for the Arria10 SoCDK.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c |  7 +++
 3 files changed, 32 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..8516633
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
1.8.2.3

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Re: [U-Boot] [PATCH v7 00/16] Add Intel Arria 10 SoC support

[Marek Vasut]

On 04/25/2017 08:44 PM, Ley Foon Tan wrote:
> This is the 7th version of patchset to adds support for Intel Arria 10 SoC.
> This is initial patchset enables the basic support for Arria 10 and other
> features will come after this.
> 
> This series is rebased on top of 
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git.
> 
> v6 -> v7 changes:
> -
> -  Revert change in socfpga_bridges_reset() for Gen5.
> 

OK, looks fine to me. I'd like T-B from either Dinh or Dalon on Gen5 and
then I'll pick this.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 00/22] x86: Add ACPI S3 resume support

[Stefan Roese]

Hi Bin,

On 25.04.2017 11:34, Bin Meng wrote:



>>> What do you mean by "display
>>> stays in power safe mode"? Is it a black screen, or is it just
>>> U-Boot's video output screen?
>>
>> Blank screen and the monitor does not wake up from power-safe
>> mode. I see the log on the serial console, since I've changed the
>> environment (stdio) to not use the LCD as the console in U-Boot.
>> U-Boot uses the console as a splash screen instead.
>>
> 
> Since you were seeing black screen I guess your U-Boot was not running
> the VGA BIOS for the Intel Baytrail IGD?

My U-Boot configuration runs the VGA BIOS via the "preboot" env
command:

=> printenv preboot 
preboot=load scsi 0:${ubuntu_part} ${loadaddr} /boot/logo/logo.bmp;bmp display 
${loadaddr}

> The LCD driver is not the
> Intel i915 graphics driver?

In Linux it is. But in the resume case, the preboot env command is
not run, so this explains why the screen is not initialized by
U-Boot (again).
 
 Jumping to OS waking vector 0009a1d0

 And the POST debug byte is also identical (0x40).

>>>
>>> These logs looks good. Nothing strange.
>>>
 Do you have any ideas, where this might come from? Could you
 perhaps check this on MinnoxMax as well, if such a setup also
 sometimes has problems with resuming? Is there anything that I could
 do to test this on my platform?

>>>
>>> To match your env, I will install a 16.04 from U-Boot for testing. Can
>>> you add the following kernel parameters for testing suspend/resume?
>>>
>>> "console=ttyS0,115200 initcall_debug ignore_loglevel no_console_suspend"
>>
>> Ah, this brings some infos. Here the resume log:
>>
>> [   49.810439] smpboot: CPU 3 is now offline
>> [   49.828153] PM: Calling kvm_suspend+0x0/0x30 [kvm]
>> [   49.833517] PM: Calling mce_syscore_suspend+0x0/0x20
>> [   49.839072] PM: Calling ledtrig_cpu_syscore_suspend+0x0/0x20
>> [   49.845404] PM: Calling acpi_processor_suspend+0x0/0x1e
>> [   49.851255] PM: Calling timekeeping_suspend+0x0/0x2a0
>> [   49.856925] PM: Calling irq_gc_suspend+0x0/0x70
>> [   49.861992] PM: Calling save_ioapic_entries+0x0/0x90
>> [   49.867738] PM: Calling i8259A_suspend+0x0/0x30
>> [   49.872806] PM: Calling fw_suspend+0x0/0x20
>> [   49.877484] PM: Calling lapic_suspend+0x0/0x1b0
>> ��
>>
>> U-Boot 2017.05-rc2-00122-gf6a9c0b4fd-dirty (Apr 24 2017 - 10:50:06 +0200)
>>
>> CPU: x86_64, vendor Intel, device 30679h
>> DRAM:  4 GiB
>> MMC:   ValleyView SDHCI: 0, ValleyView SDHCI: 1, ValleyView SDHCI: 2
>> SF: Detected w25q64cv with page size 256 Bytes, erase size 4 KiB, total 8 MiB
>> Model: congatec-QEVAL20-QA3-E3845
>> SCSI:  SATA link 0 timeout.
>> Target spinup took 0 ms.
>> AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
>> flags: 64bit ncq stag pm led clo pio slum part sxs
>> scanning bus for devices...
>>   Device 0: (1:0) Vendor: ATA Prod.: SanDisk Ultra II Rev: X411
>> Type: Hard Disk
>> Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)
>> Found 1 device(s).
>> Net:   e1000: 00:13:95:1c:51:e8
>>eth0: e1000#0
>> Jumping to OS waking vector 0009a1d0
>> [   49.882704] ACPI: Low-level resume complete
>> [   49.887483] PM: Restoring platform NVS memory
>> [   49.892361] PM: Calling bsp_resume+0x0/0x20
>> [   49.897040] PM: Calling lapic_resume+0x0/0x2b0
>> [   49.902035] PM: Calling irqrouter_resume+0x0/0x3f
>> [   49.907297] PM: Calling i8259A_resume+0x0/0x30
>> [   49.912393] PM: Calling i8237A_resume+0x0/0x90
>> [   49.917434] PM: Calling ioapic_resume+0x0/0xa0
>> [   49.922495] PM: Calling irq_gc_resume+0x0/0x60
>> [   49.927464] PM: Calling irq_pm_syscore_resume+0x0/0x20
>> [   49.933256] PM: Calling timekeeping_resume+0x0/0x200
>> [   49.938844] PM: Calling acpi_processor_resume+0x0/0x5c
>> [   49.944595] PM: Calling ledtrig_cpu_syscore_resume+0x0/0x20
>> [   49.950829] PM: Calling mce_syscore_resume+0x0/0x30
>> [   49.956291] PM: Calling mc_bp_resume+0x0/0x50
>> [   49.961193] PM: Calling kvm_resume+0x0/0x40 [kvm]
>> [   49.966523] Enabling non-boot CPUs ...
>> [   49.990192] x86: Booting SMP configuration:
>> [   49.994894] smpboot: Booting Node 0 Processor 1 APIC 0x2
>> [   50.011048]  cache: parent cpu1 should not be sleeping
>> [   50.017239] CPU1 is up
>> [   50.038380] smpboot: Booting Node 0 Processor 2 APIC 0x4
>> [   50.054552]  cache: parent cpu2 should not be sleeping
>> [   50.060685] CPU2 is up
>> [   50.082550] smpboot: Booting Node 0 Processor 3 APIC 0x6
>> [   50.098820]  cache: parent cpu3 should not be sleeping
>> [   50.104972] CPU3 is up
>> [   50.108534] ACPI: Waking up from system sleep state S3
>> [   50.114576] calling  :00:00.0+ @ 2269, parent: pci:00
>> [   50.114630] calling  :00:02.0+ @ 163, parent: pci:00
>> [   50.114728] calling  :00:11.0+ @ 2265, parent: pci:00
>> [   50.114759] calling  :00:12.0+ @ 2268, parent: pci:00
>> [   50.114800] calling  :00:13.0+ @ 159, parent: pci:00
>> [   50.114830] calling  :00:15.0+ @ 149, 

Re: [U-Boot] sunxi: Build issue with Bananapi_M2_Ultra

[Tom Rini]

On Tue, Apr 25, 2017 at 05:59:43PM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 25, 2017 at 4:46 PM, Chen-Yu Tsai  wrote:
> > Hi,
> >
> > On Tue, Apr 25, 2017 at 1:56 PM, Jagan Teki  
> > wrote:
> >> Hi,
> >>
> >> We're unable to build with buildman with gcc-4.9.x
> >>
> >>arm:  +   Bananapi_M2_Ultra
> >> +arm-unknown-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will
> >> not fit in region `.sram'
> >> +arm-unknown-linux-gnueabi-ld.bfd: region `.sram' overflowed by 716 bytes
> >> +make[2]: *** [spl/u-boot-spl] Error 1
> >> +make[1]: *** [spl/u-boot-spl] Error 2
> >>
> >> Any inputs?
> >
> > CC-ing Andre as he's probably interested in this as well.
> >
> > I normally build my stuff with Debian's 6.3 cross compiler. It seems
> > that people don't always use the latest stuff, So I did a comparison
> > between Linaro's 2016.02 5.3 and 2016.11 6.2.1 toolchains. I don't
> > have a 4.x toolchain at the moment.
> >
> > Long story short, the latter builds successfully, while the former fails.
> > However, the object file sizes don't vary much between the two. I think
> > the real difference is that the 6.2.1 toolchain comes with the GOLD linker.
> > It probably does a much better job at pruning out dead code.
> >
> > Appended is a list of object file sizes for the 5.3 toolchain, with
> > total sizes for the 6.2.1 toolchain for comparison.
> >
> > A few things pop up:
> >
> >   - spl/arch/arm/lib/interrupts.o
> > We are not using interrupts at all. Is this even necessary?
> > IIRC there was a patch to get rid of this from Tom (CC-ed).
> >
> >   - spl/common/dlmalloc.o
> > Why do we still need this when we have SYS_MALLOC_SIMPLE
> > enabled?
> >
> >   - spl/common/image.o
> > Almost half of this is description strings for U-boot legacy
> > images, which probably isn't used in SPL? Could we somehow
> > use macros to get rid of them?
> 
> Digging a bit deeper, I found that interrupts and dlmalloc were
> discarded by the linker. As far as C strings go, GCC 5.3 just
> dumps them all in the same section, which basically means all of
> them will get included, regardless of whether they are actually
> used or referenced. GCC 6 does a good job of splitting them by
> function, so all the C strings in one function get allocated to
> one section. If a function isn't used, it's text and rodata
> sections get dropped.
> 
> In a project I worked on in the past, a solution (or workaround)
> for this was to use named array (not pointer) symbols for each
> string. Each string would get tied to a symbol, and -fdata-sections
> would work properly with these.
> 
> IMHO upgrading to a newer toolchain is easier though.

Right and agreed.  This is
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303 which was resolved
with gcc-6.x.  That we keep hitting this form of problem (board X is OK
with gcc-6.x or later, fails to link with older) is why I finally did
https://patchwork.ozlabs.org/patch/751309/ and have moved travis-ci over
to gcc-6.3.1 for ARM.  I will be applying my patch for this release.

This in turn leads to needing to address lots of new warnings, and I
need to find some time to add a real testcase to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80428 as that is the bug I
filed over the warnings about "tab_seq[]" and "erase_seq[]" in
cli_readline.c

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Re: [U-Boot] Please pull u-boot-mips

[Tom Rini]

On Fri, Apr 21, 2017 at 05:02:14PM +0200, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> please pull two bugfixes for qemu_mips, thanks.
> 
> 
> The following changes since commit f6c1df44b815a08585e7fd3805a1db51a5955d09:
> 
>   Prepare v2017.05-rc2 (2017-04-17 18:16:49 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to 1967228b028b5ddf0b0b41806e5bd10e49e836a6:
> 
>   mips: qemu-mips/64: Expand malloc pool for CONFIG_SYS_BOOTPARAMS_LEN 
> (2017-04-21 13:54:47 +0200)
> 

Applied to u-boot/master, thanks!




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Re: [U-Boot] pull request: u-boot-uniphier/master

[Tom Rini]

On Sat, Apr 22, 2017 at 02:08:53AM +0900, Masahiro Yamada wrote:

> Hi Tom,
> 
> Here is a small pull request for UniPhier SoCs.
> Please pull!
> 
> - Add USB PHY settings
> - Use PSCI system reset when used with ARM Trusted Firmware
> - Improve boot log to show SCP status
> - Sync DT with Linux
> 
> 
> The following changes since commit 3c476d841daa491f87c8f07851038afbdf4d90a8:
> 
>   Merge git://git.denx.de/u-boot-fsl-qoriq (2017-04-18 11:36:06 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-uniphier.git master
> 
> for you to fetch changes up to 4e7f8de42642cd0036dc78bf0df293f105cb5267:
> 
>   ARM: dts: uniphier: sync Device Tree with Linux (2017-04-20 23:50:02 +0900)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH 1/2] armv8: ls1046ardb: Make NET independent of FMan

[York Sun]

This allows using PCIe NIC without enabling DPAA FMan.

Signed-off-by: York Sun 
CC: Mingkai Hu 
---
 board/freescale/ls1046ardb/Makefile |  2 +-
 include/configs/ls1046ardb.h| 15 +--
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/board/freescale/ls1046ardb/Makefile 
b/board/freescale/ls1046ardb/Makefile
index b92ed0b..4076558 100644
--- a/board/freescale/ls1046ardb/Makefile
+++ b/board/freescale/ls1046ardb/Makefile
@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1046ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 67ee626..40a5635 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -178,18 +178,20 @@
 #define CONFIG_ENV_SECT_SIZE   0x4 /* 256KB */
 #endif
 
+#define AQR105_IRQ_MASK0x8000
 /* FMan */
 #ifndef SPL_NO_FMAN
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
+
+#ifdef CONFIG_NET
 #define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE/* Include GbE speed/duplex detection */
-
 #define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_AQUANTIA
-#define AQR105_IRQ_MASK0x8000
+#endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_AQUANTIA
+#define CONFIG_PHYLIB_10G
 #define RGMII_PHY1_ADDR0x1
 #define RGMII_PHY2_ADDR0x2
 
@@ -200,6 +202,7 @@
 
 #define CONFIG_ETHPRIME"FM1@DTSEC3"
 #endif
+
 #endif
 
 /* QSPI device */
-- 
2.7.4

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[U-Boot] [PATCH 2/2] armv8: ls1043ardb: Make NET independent of FMan

[York Sun]

This allows using PCIe NIC without enabling DPAA FMan.

Signed-off-by: York Sun 
CC: Mingkai Hu 
---
 board/freescale/ls1043ardb/Makefile |  2 +-
 include/configs/ls1043ardb.h| 13 -
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/board/freescale/ls1043ardb/Makefile 
b/board/freescale/ls1043ardb/Makefile
index 2a4452e..930c690 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1043ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 5e570cd..5e5d1f6 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -250,16 +250,19 @@
 
 /* FMan */
 #ifndef SPL_NO_FMAN
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
+#define AQR105_IRQ_MASK0x4000
+
+#ifdef CONFIG_NET
 #define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE/* Include GbE speed/duplex detection */
-
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_AQUANTIA
-#define AQR105_IRQ_MASK0x4000
 
 #define RGMII_PHY1_ADDR0x1
 #define RGMII_PHY2_ADDR0x2
-- 
2.7.4

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[U-Boot] Please pull u-boot-fsl-qoriq master

[York Sun]

Tom,

The following changes since commit 3c476d841daa491f87c8f07851038afbdf4d90a8:

  Merge git://git.denx.de/u-boot-fsl-qoriq (2017-04-18 11:36:06 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-fsl-qoriq.git

for you to fetch changes up to fedebf0d08a7aa152f8f27de1d40eb036557c11b:

  armv8: layerscape: Fix DDR size calcuation for SPL build (2017-04-24 
09:07:12 -0700)



Alison Wang (1):
  arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033

Hou Zhiqiang (3):
  armv8: ls1043aqds: Integrate FSL PPA
  armv8: ls1043aqds: enable FSL PPA
  armv8: ls1046aqds: Integrate FSL PPA

Santan Kumar (1):
  armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b

Sumit Garg (3):
  armv8: fsl-layerscape: Support loading PPA header from eMMC/SD 
and NAND Flash

  armv8: fsl-layerscape: Add validation of PPA image from NAND and SD
  armv8: ls104xardb: Secure Boot: enable PPA support for eMMC/SD 
and NAND boot


York Sun (1):
  armv8: layerscape: Fix DDR size calcuation for SPL build

Yuantian Tang (1):
  arm: psci: make psci usable on single core socs

 arch/arm/cpu/armv8/cpu-dt.c | 13 ++---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   | 10 
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 35 ++--
 arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 72 
-

 arch/arm/cpu/armv8/sec_firmware.c   |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/mp.h   |  4 ++
 arch/arm/include/asm/armv8/sec_firmware.h   |  7 +++
 board/freescale/ls1021atwr/ls1021atwr.c |  1 +
 board/freescale/ls1043aqds/ddr.c|  4 +-
 board/freescale/ls1043aqds/ls1043aqds.c |  5 ++
 board/freescale/ls1046aqds/ddr.c|  4 +-
 board/freescale/ls1046aqds/ls1046aqds.c |  5 ++
 board/freescale/ls1046ardb/ddr.c|  4 +-
 board/freescale/ls2080ardb/eth_ls2080rdb.c  |  7 +++
 configs/ls1043aqds_defconfig|  1 +
 configs/ls1043aqds_lpuart_defconfig |  1 +
 configs/ls1043aqds_nand_defconfig   |  1 +
 configs/ls1043aqds_nor_ddr3_defconfig   |  1 +
 configs/ls1043aqds_qspi_defconfig   |  1 +
 configs/ls1043aqds_sdcard_ifc_defconfig |  1 +
 configs/ls1043aqds_sdcard_qspi_defconfig|  1 +
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig   |  1 +
 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig |  1 +
 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig |  1 +
 24 files changed, 148 insertions(+), 35 deletions(-)

Thanks.

York
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Re: [U-Boot] [PATCH 0/4] MIPS: call debug_uart_init right before board_init_f

[Álvaro Fernández Rojas]

I've just realized I sent this without v2 prefix.
Should I resend it?

El 24/04/2017 a las 19:03, Álvaro Fernández Rojas escribió:
> All MIPS boards that support debug uart are calling debug_uart_init right at
> the beginning of board_early_init_f.
> Instead of doing that, let's provide a generic call to debug_uart_init right
> before the call to board_init_f if debug uart is enabled.
> 
> v2: Introduce the changes suggested by Daniel Schwierzeck:
>  - Call debug_uart_init before low level init for boards with stack in SRAM.
> 
> Daniel Schwierzeck (1):
>   MIPS: call debug_uart_init right before board_init_f
> 
> Álvaro Fernández Rojas (3):
>   MIPS: QCA AP121: remove debug_uart_init call
>   MIPS: QCA AP143: remove debug_uart_init call
>   MIPS: tl-wdr4300: remove debug_uart_init call
> 
>  arch/mips/cpu/start.S  | 14 ++
>  board/qca/ap121/ap121.c|  3 ---
>  board/qca/ap143/ap143.c|  3 ---
>  board/tplink/wdr4300/wdr4300.c | 18 ++
>  4 files changed, 28 insertions(+), 10 deletions(-)
> 
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Re: [U-Boot] [PATCH 2/2][v4] nxp/ls2080ardb: Add QSPI-boot support

[York Sun]

On 04/25/2017 03:18 AM, Priyanka Jain wrote:

QSPI-boot is verified on LS20080ARDB RevF board


Typo here. It is LS2080ARDB.


with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS


Is the board marked as LS2088ARDB? Is the limitation on rev F board, or 
the boot method?



can not be access, so QIXIS flag is kept disabled

Signed-off-by: Priyanka Jain 
Signed-off-by: Suresh Gupta 
---
 Changes for v4: Updated copyright
 Changes for v3: Updated README

 Changes for v2: Incorporated Sun York's comments
   Introduced another patch to update qixis related code






diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 2155a89..6742816 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -12,6 +13,12 @@
 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX   2

+#ifdef CONFIG_FSL_QSPI
+#undef CONFIG_CMD_IMLS


This is a Kconfig option. Do it properly in your defconfig.


+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
+
 #define I2C_MUX_CH_VOL_MONITOR 0xa
 #define I2C_VOL_MONITOR_ADDR   0x38
 #define CONFIG_VOL_MONITOR_IR36021_READ
@@ -69,6 +76,7 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)

+#ifndef CONFIG_FSL_QSPI
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
@@ -157,7 +165,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_CMD_NAND

 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
 #define CONFIG_FSL_QIXIS   /* use common QIXIS code */
 #define QIXIS_LBMAP_SWITCH 0x06
 #define QIXIS_LBMAP_MASK   0x0f
@@ -250,7 +257,7 @@ unsigned long get_board_sys_clk(void);
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR0x580D0ULL
-
+#endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

 /*
@@ -263,11 +270,18 @@ unsigned long get_board_sys_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8

 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+#endif

 /*
  * RTC configuration
@@ -347,6 +361,27 @@ unsigned long get_board_sys_clk(void);
" 0x58080 \0"   \
BOOTENV
 #else
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+   "hwconfig=fsl_ddr:bank_intlv=auto\0"  \
+   "scriptaddr=0x8080\0" \
+   "kernel_addr_r=0x8100\0"  \
+   "pxefile_addr_r=0x8100\0" \
+   "fdt_addr_r=0x8800\0" \
+   "ramdisk_addr_r=0x8900\0" \
+   "loadaddr=0x8010\0"   \
+   "kernel_addr=0x10\0"  \
+   "ramdisk_addr=0x80\0" \


Where do you use ramdisk_addr?


+   "ramdisk_size=0x200\0"\
+   "fdt_high=0xa000\0"   \
+   "initrd_high=0x\0"\
+   "kernel_start=0x2110\0"   \
+   "mcmemsize=0x4000\0"  \
+   "fdtfile=fsl-ls2080a-rdb.dtb\0"   \


Where do you use fdtfile?

York

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Re: [U-Boot] [PATCH 0/4] MIPS: call debug_uart_init right before board_init_f

[Daniel Schwierzeck]

2017-04-25 17:48 GMT+02:00 Álvaro Fernández Rojas :
> I've just realized I sent this without v2 prefix.
> Should I resend it?

no, I've found the right patches in patchwork ;)

>
> El 24/04/2017 a las 19:03, Álvaro Fernández Rojas escribió:
>> All MIPS boards that support debug uart are calling debug_uart_init right at
>> the beginning of board_early_init_f.
>> Instead of doing that, let's provide a generic call to debug_uart_init right
>> before the call to board_init_f if debug uart is enabled.
>>
>> v2: Introduce the changes suggested by Daniel Schwierzeck:
>>  - Call debug_uart_init before low level init for boards with stack in SRAM.
>>
>> Daniel Schwierzeck (1):
>>   MIPS: call debug_uart_init right before board_init_f
>>
>> Álvaro Fernández Rojas (3):
>>   MIPS: QCA AP121: remove debug_uart_init call
>>   MIPS: QCA AP143: remove debug_uart_init call
>>   MIPS: tl-wdr4300: remove debug_uart_init call
>>
>>  arch/mips/cpu/start.S  | 14 ++
>>  board/qca/ap121/ap121.c|  3 ---
>>  board/qca/ap143/ap143.c|  3 ---
>>  board/tplink/wdr4300/wdr4300.c | 18 ++
>>  4 files changed, 28 insertions(+), 10 deletions(-)
>>



-- 
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Re: [U-Boot] [PATCH] patman: encode CC list to UTF-8

[Tom Rini]

On Sat, Apr 22, 2017 at 05:53:36PM -0600, Simon Glass wrote:
> +Tom
> 
> On 19 April 2017 at 07:24, Philipp Tomsich
>  wrote:
> >
> > This change encodes the CC list to UTF-8 to avoid failures on
> > maintainer-addresses that include non-ASCII characters (observed on
> > Debian 7.11 with Python 2.7.3).
> >
> > Without this, I get the following failure:
> >   Traceback (most recent call last):
> > File "tools/patman/patman", line 159, in 
> >   options.add_maintainers)
> > File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile
> >   print(commit.patch, ', '.join(set(list)), file=fd)
> >   UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in 
> > position 81: ordinal not in range(128)
> > from Heiko's email address:
> >   [..., u'"Heiko St\xfcbner" ', ...]
> >
> > While with this change added this encodes to:
> >   "=?UTF-8?q?Heiko=20St=C3=BCbner?= "
> >
> > Signed-off-by: Philipp Tomsich 
> > ---
> >
> >  tools/patman/series.py | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> Reviewed-by: Simon Glass 

Please put this in a PR for me, along with any other critical fixes to
the various python tools we have, thanks!

And also, do we need to perhaps whack something at a higher level, and
more consistently, about unicode?  This is, I gather, doing UTF-8 right.
In buildman we have a few patches to just translate to latin-1 instead.
We should do the same thing I think, and perhaps there's a higher level
up in the code where we need to do it too?  I don't know..

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Re: [U-Boot] [PATCH v1 0/2] DS1307 RTC update

[Tom Rini]

On Sun, Apr 23, 2017 at 09:38:58PM -0600, Simon Glass wrote:
> +Tom
> 
> Hi Chris,
> 
> On 21 April 2017 at 10:27, Chris Packham  wrote:
> >
> > The first patch is the addition of a KConfig option for the date
> > command. I haven't updated any boards to use the new option due to the
> > sheer number of boards that would affect. It's probably better if board
> > maintainers switch if/when they're ready.
> 
> You should be able to use moveconfig.py to do this automatically.
> 
> I'm not sure of the best method here.
> 
> Tom, do you expect people to run the tool or are you doing this
> yourself before you apply it?

It depends greatly on the complexity.  I appreciate it when people do
it and this is probably an easy one to move.  Thanks!

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Re: [U-Boot] [RFC PATCH] ext4: Fix comparision of unsigned expression with < 0

[Tom Rini]

On Tue, Apr 25, 2017 at 10:22:27AM +0530, Lokesh Vutla wrote:
> In file ext4fs.c funtion ext4fs_read_file() compares an
> unsigned expression with < 0 like below
> 
>   lbaint_t blknr;
>   blknr = read_allocated_block(&(node->inode), i);
>   if (blknr < 0)
>   return -1;
> 
> blknr is of type ulong/uint64_t. read_allocated_block() returns
> long int. So comparing blknr with < 0 will always be false. Instead
> declare blknr as long int.
> 
> Reported-by: Sunita Nadampalli 
> Signed-off-by: Lokesh Vutla 
> ---
>  fs/ext4/ext4fs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
> index 7187dcfb05..081509dbb4 100644
> --- a/fs/ext4/ext4fs.c
> +++ b/fs/ext4/ext4fs.c
> @@ -71,7 +71,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
>   blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
>  
>   for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
> - lbaint_t blknr;
> + long int blknr;
>   int blockoff = pos - (blocksize * i);
>   int blockend = blocksize;
>   int skipfirst = 0;

My only question is, did you catch that by inspection, clang, or a newer
than gcc-6.3 warning?  Also, fs/ext4/dev.c:63 is a similar problem, if
you'd like to non-RFC a v2.  Thanks!

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Re: [U-Boot] [PATCH 1/5] i.MX6Q: icorem6: Add modeboot env via board_late_init

[Jagan Teki]

Hi Stefano,

On Mon, Apr 17, 2017 at 9:18 PM, Jagan Teki  wrote:
> On Wed, Apr 12, 2017 at 9:27 PM, Stefano Babic  wrote:
>> On 07/04/2017 19:50, Jagan Teki wrote:
>>> Hi Stefano,
>>>
>>> On Mon, Mar 27, 2017 at 11:32 PM, Jagan Teki  wrote:
 From: Jagan Teki 

 Add runtime, modeboot env which is setting mmcboot, or
 nandboot based on the bootdevice so-that conditional
 macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
 be avoided in config files.

 Cc: Matteo Lisi 
 Cc: Michael Trimarchi 
 Cc: Stefano Babic 
 Signed-off-by: Jagan Teki 
>>>
>>> Can you take this series?
>>>
>>
>> I could take, but I am just asking if you do not find another way to
>> avoid code duplication. You have very similar boards, and code is simply
>> duplicated. Let's see Pathch 1/5 and Patch 3/5:
>>
>>
>> +int board_late_init(void)
>> +{
>> +   switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
>> +   IMX6_BMODE_SHIFT) {
>> +   case IMX6_BMODE_SD:
>> +   case IMX6_BMODE_ESD:
>> +   setenv("modeboot", "mmcboot");
>> +   break;
>> +   case IMX6_BMODE_NAND:
>> +   setenv("modeboot", "nandboot");
>> +   break;
>> +   default:
>> +   setenv("modeboot", "");
>> +   break;
>> +   }
>> +
>> +   return 0;
>> +}
>>
>> And patch 3/5:
>>
>> +int board_late_init(void)
>> +{
>> +   switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
>> +   IMX6_BMODE_SHIFT) {
>> +   case IMX6_BMODE_SD:
>> +   case IMX6_BMODE_ESD:
>> +   setenv("modeboot", "mmcboot");
>> +   break;
>> +   case IMX6_BMODE_NAND:
>> +   setenv("modeboot", "nandboot");
>> +   break;
>> +   default:
>> +   setenv("modeboot", "");
>> +   break;
>> +   }
>> +
>> +   return 0;
>> +}
>> +
>>
>>
>> Why do you not use the same factorization as for Freescale's boards ? A
>> board/engicam/common could contain shared code, and you reuse it among
>> boards. The same for the default environment: it is duplicated again.
>
> Yes, I understand completely. will factorized the code in coming MW.

Any help?

thanks!
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Re: [U-Boot] [PATCH v4 00/35] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

On Mon, Apr 17, 2017 at 6:58 PM, Jagan Teki  wrote:
> On Mon, Apr 10, 2017 at 4:43 AM, Fabio Estevam  wrote:
>> On Sun, Apr 9, 2017 at 4:12 PM, Jagan Teki  wrote:
>>
>>> Bcz we need to define dtb through CONFIG_DEFAULT_DEVICE_TREE
>>
>> Having 3 defconfigs for SPL is not good. Looks like a step in the
>> opposite direction.
>>
>> Can this limitation be changed?
>
> This isn't a limitation, all the defconfigs on various boards follows
> the same but except by giving dtb explicitly doing make, like
> make DEVICE_TREE=imx6l-sabresd

Any help?

thanks!
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[U-Boot] Pull request: u-boot-sunxi/master

[Jagan Teki]

Hi Tom,

Please take this PR, probably the last PR for the release.

thanks!
Jagan.

The following changes since commit f6c1df44b815a08585e7fd3805a1db51a5955d09:

  Prepare v2017.05-rc2 (2017-04-17 18:16:49 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to e8f86a026125ff2b2d6bd6eac73d2542852aab84:

  sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I (2017-04-25 
11:44:21 +0200)


Andreas Färber (1):
  sunxi: Fix arm64 fdtfile variable

Chen-Yu Tsai (13):
  sunxi: Split up long Kconfig lines
  sunxi: Add initial support for R40
  sunxi: Enable AXP221s in I2C mode with the R40 SoC
  sunxi: Fix watchdog reset function for R40
  sunxi: Add mmc[1-3] pinmux settings for R40
  sunxi: Set PLL lock enable bits for R40
  sunxi: Provide defaults for R40 DRAM settings
  gpio: sunxi: Add compatible string for R40 PIO
  sunxi: Use H3/A64 DRAM initialization code for R40
  sunxi: Enable SPL for R40
  sunxi: Fix CPUCFG address for R40
  sunxi: Add PSCI support for R40
  sunxi: Add support for Bananapi M2 Ultra

Icenowy Zheng (4):
  sunxi: add basic V3s support
  sunxi: add DTSI file for V3s
  sunxi: add support for Lichee Pi Zero
  sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I

Jelle van der Waa (1):
  sunxi: Add maintainer of the NanoPi NEO Air

Jernej Skrabec (3):
  sunxi: video: Split out TCON code
  sunxi: video: Convert lcdc to use struct display_timing
  sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

Mylène Josserand (9):
  sunxi: Move SUNXI_GMAC to Kconfig
  sunxi: icnova-a20-swac_defconfig: Remove AXP209_POWER
  sunxi: icnova-a20-swac_defconfig: Remove CMD_BMP from
  sunxi: mk802_defconfig: Remove SYS_EXTRA_OPTIONS
  sunxi: Convert SUNXI_EMAC to Kconfig
  sunxi: Convert CONFIG_RGMII to Kconfig
  sunxi: Convert CONFIG_SATAPWR to Kconfig
  sunxi: Convert CONFIG_MACPWR to Kconfig
  sunxi: Convert CONS_INDEX to Kconfig

 arch/arm/cpu/armv7/sunxi/psci.c |  35 ++-
 arch/arm/dts/Makefile   |   4 +
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts|  69 ++
 arch/arm/dts/sun8i-r40.dtsi | 183 +++
 arch/arm/dts/sun8i-v3s-licheepi-zero.dts|  83 +++
 arch/arm/dts/sun8i-v3s.dtsi | 284 
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h   |  56 +
 arch/arm/include/asm/arch-sunxi/cpu.h   |   1 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |   6 +-
 arch/arm/include/asm/arch-sunxi/display.h   | 103 -
 arch/arm/include/asm/arch-sunxi/dram.h  |   4 +-
 arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h |  20 +-
 arch/arm/include/asm/arch-sunxi/gpio.h  |   1 +
 arch/arm/include/asm/arch-sunxi/lcdc.h  | 128 +++
 arch/arm/include/asm/arch-sunxi/timer.h |   5 +-
 arch/arm/include/asm/arch-sunxi/watchdog.h  |   5 +-
 arch/arm/mach-sunxi/Makefile|   1 +
 arch/arm/mach-sunxi/board.c |  19 +-
 arch/arm/mach-sunxi/clock_sun6i.c   |  47 +++-
 arch/arm/mach-sunxi/cpu_info.c  |   4 +
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 121 --
 arch/arm/mach-sunxi/pmic_bus.c  |   7 +
 board/sunxi/Kconfig |  72 +-
 board/sunxi/MAINTAINERS |  16 ++
 board/sunxi/board.c |  48 +++-
 configs/A10-OLinuXino-Lime_defconfig|   3 +-
 configs/A10s-OLinuXino-M_defconfig  |   2 +-
 configs/A13-OLinuXinoM_defconfig|   1 -
 configs/A13-OLinuXino_defconfig |   1 -
 configs/A20-OLinuXino-Lime2_defconfig   |   4 +-
 configs/A20-OLinuXino-Lime_defconfig|   3 +-
 configs/A20-OLinuXino_MICRO_defconfig   |   3 +-
 configs/A20-Olimex-SOM-EVB_defconfig|   4 +-
 configs/Ampe_A76_defconfig  |   1 -
 configs/Bananapi_M2_Ultra_defconfig |  15 ++
 configs/Bananapi_defconfig  |   4 +-
 configs/Bananapro_defconfig |   4 +-
 configs/CHIP_defconfig  |   1 -
 configs/CHIP_pro_defconfig  |   2 +-
 configs/CSQ_CS908_defconfig |   2 +-
 configs/Colombus_defconfig  |   3 +-
 configs/Cubieboard2_defconfig   |   3 +-
 configs/Cubieboard_defconfig|   3 +-
 configs/Cubietruck_defconfig|   4 +-
 configs/Empire_electronix_d709_defconfig|   1 -
 configs/Empire_electronix_m712_defconfig|   1 -
 configs/Hummingbird_A31_defconfig   |   3 +-
 configs/Itead_Ibox_A20_defconfig|   3 +-
 

Re: [U-Boot] [PATCH v4 00/35] ARM: i.MX6: SabreSD: Add dts support

[Fabio Estevam]

Hi Jagan,

On Tue, Apr 25, 2017 at 3:35 PM, Jagan Teki  wrote:
>
>> This isn't a limitation, all the defconfigs on various boards follows
>> the same but except by giving dtb explicitly doing make, like
>> make DEVICE_TREE=imx6l-sabresd
>
> Any help?

Take imx6 cubox or imx6 wandboard as reference. We can run the same
single SPL + u-boot.img on mx6solo/dual/dual-lite/quad versions.

With the dts approach this is no longer possible, correct? In this
case I do not see a benefit in converting mx6sabresd to dts.
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Re: [U-Boot] [PATCH v4 0/7] am57xx: cl-som-am57x: fix usb

[Marek Vasut]

On 04/25/2017 03:09 AM, Tom Rini wrote:
> On Sun, Apr 23, 2017 at 11:18:04AM +0300, Uri Mashiach wrote:
>> Hello Tom,
>>
>> A gentle ping on this patch series.
>>
>> On 02/23/2017 03:39 PM, Uri Mashiach wrote:
>>> Various USB related comits for the CL-SOM-AM57x module.
>>>
>>> ---
>>> V1 -> V2: Replace commit "fix XHCI registers base address" with 
>>> "reintroduce the CONFIG_AM57XX symbol".
>>> V2 -> V3: * New commit "move CONFIG_DRA7XX to Kconfig"
>>>  * Replace commit "reintroduce the CONFIG_AM57XX symbol" with "xHCI 
>>> registers based on USB port index"
>>> V3 -> V4: Update commit "move CONFIG_DRA7XX to Kconfig"
>>>   Update commit "xHCI registers based on USB port index"
>>>
>>> Uri Mashiach (7):
>>>  arm: dra7xx: move CONFIG_DRA7XX to Kconfig
>>>  arm: usb: dra7xx: xHCI registers based on USB port index
>>>  usb: host: xhci-omap: fix double weak board_usb_init functions
>>>  arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocks
>>>  arm: am57xx: cl-som-am57x: fix USB scan
>>>  arm: am57xx: cl-som-am57x: enable USB storage
>>>  arm: am57xx: cl-som-am57x: enable USB commands
>>>
>>> arch/arm/mach-omap2/omap5/Kconfig  |  8 
>>> board/compulab/cl-som-am57x/cl-som-am57x.c | 10 --
>>> board/ti/am43xx/board.c|  4 ++--
>>> board/ti/am57xx/board.c|  4 ++--
>>> board/ti/dra7xx/evm.c  |  4 ++--
>>> configs/cl-som-am57x_defconfig |  2 ++
>>> configs/dra7xx_evm_defconfig   |  1 +
>>> configs/dra7xx_hs_evm_defconfig|  1 +
>>> drivers/usb/host/Kconfig   |  9 +
>>> drivers/usb/host/xhci-omap.c   | 19 +--
>>> include/configs/am57xx_evm.h   |  2 --
>>> include/configs/cl-som-am57x.h |  6 ++
>>> include/configs/dra7xx_evm.h   |  2 --
>>> include/linux/usb/xhci-omap.h  |  6 --
>>> scripts/config_whitelist.txt   |  1 -
>>> 15 files changed, 50 insertions(+), 29 deletions(-)
> 
> Marek?  Thanks!

Tom?  Thanks!

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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Tue, Apr 25, 2017 at 12:49:41PM +0200, Marek Vasut wrote:

> This was rotting in for too long, might as well push it upstream ...
> 
> The following changes since commit 3c476d841daa491f87c8f07851038afbdf4d90a8:
> 
>   Merge git://git.denx.de/u-boot-fsl-qoriq (2017-04-18 11:36:06 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 6bd041f00d5d80761852eae1ecb7879a27f3c289:
> 
>   arm: socfpga: add cyclone5 based de10-nano board (2017-04-25 12:46:44
> +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] power: twl4030: Add CONFIG_CMD_POWEROFF support

[Tom Rini]

On Mon, Apr 24, 2017 at 01:34:43PM -0500, Adam Ford wrote:

> With the addition of twl4030_power_off(), let's allow the 'poweroff' command
> to run this function when CONFIG_CMD_POWEROFF is enabled.
> 
> Tested on a DM3730 with twl4030 PMIC.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
> index 8866bf1..ab98d68 100644

Reviewed-by: Tom Rini 

... any chance you've got moving TWL4030 stuff to Kconfig on your TODO
list? :)

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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Tue, Apr 25, 2017 at 12:51:10PM +0200, Marek Vasut wrote:

> The following changes since commit 3c476d841daa491f87c8f07851038afbdf4d90a8:
> 
>   Merge git://git.denx.de/u-boot-fsl-qoriq (2017-04-18 11:36:06 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 83cb46c286beb5406aaed2e0d5895719717804b3:
> 
>   ehci-ppc4xx: Prepare for usage of readl()/writel() accessors
> (2017-04-25 12:50:13 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2] Kconfig: Enable FIT support by default for TI platforms

[Tom Rini]

On Fri, Apr 21, 2017 at 10:01:28AM -0500, Andrew F. Davis wrote:

> Almost all TI defconfigs enable this already, add this as a default
> and remove the explicit assignment.
> 
> Signed-off-by: Andrew F. Davis 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH] ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate Kconfig

[Tom Rini]

On Tue, Apr 25, 2017 at 01:10:11PM +0900, Masahiro Yamada wrote:

> In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs.
> Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this
> naming.
> 
> Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim
> down the arch/arm/Kconfig level.
> 
> Signed-off-by: Masahiro Yamada 

Reviewed-by: Tom Rini 

Thanks for doing that one for me!

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Re: [U-Boot] [PATCH] patman: encode CC list to UTF-8

[Simon Glass]

Hi Tom,

On 25 April 2017 at 11:12, Tom Rini  wrote:
>
> On Sat, Apr 22, 2017 at 05:53:36PM -0600, Simon Glass wrote:
> > +Tom
> >
> > On 19 April 2017 at 07:24, Philipp Tomsich
> >  wrote:
> > >
> > > This change encodes the CC list to UTF-8 to avoid failures on
> > > maintainer-addresses that include non-ASCII characters (observed on
> > > Debian 7.11 with Python 2.7.3).
> > >
> > > Without this, I get the following failure:
> > >   Traceback (most recent call last):
> > > File "tools/patman/patman", line 159, in 
> > >   options.add_maintainers)
> > > File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile
> > >   print(commit.patch, ', '.join(set(list)), file=fd)
> > >   UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in 
> > > position 81: ordinal not in range(128)
> > > from Heiko's email address:
> > >   [..., u'"Heiko St\xfcbner" ', ...]
> > >
> > > While with this change added this encodes to:
> > >   "=?UTF-8?q?Heiko=20St=C3=BCbner?= "
> > >
> > > Signed-off-by: Philipp Tomsich 
> > > ---
> > >
> > >  tools/patman/series.py | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > Reviewed-by: Simon Glass 
>
> Please put this in a PR for me, along with any other critical fixes to
> the various python tools we have, thanks!
>
> And also, do we need to perhaps whack something at a higher level, and
> more consistently, about unicode?  This is, I gather, doing UTF-8 right.
> In buildman we have a few patches to just translate to latin-1 instead.
> We should do the same thing I think, and perhaps there's a higher level
> up in the code where we need to do it too?  I don't know..

Actually I don't think we are quite there yet. This really needs a
test with all the different places strings can come from, to make sure
patman does the right thing.

Regards,
Simon
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Re: [U-Boot] [PATCH v3 0/6] sunxi: video: Add support for HDMI output on A64/H3/H5

[Jernej Škrabec]

Hi Maxime,

Dne torek, 25. april 2017 ob 10:57:05 CEST je Maxime Ripard napisal(a):
> On Mon, Apr 24, 2017 at 11:54:22PM +0200, Jernej Škrabec wrote:
> > Hi Maxime,
> > 
> > Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard 
napisal(a):
> > > Hi Jernej,
> > > 
> > > On Fri, Apr 21, 2017 at 07:24:12PM +0200, Jernej Škrabec wrote:
> > > > Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard 
napisal(a):
> > > > > Hi Jernej,
> > > > > 
> > > > > On Mon, Mar 27, 2017 at 07:22:28PM +0200, Jernej Skrabec wrote:
> > > > > > This series implements support for HDMI output. This is done using
> > > > > > DM video framework and sharing the HDMI controller code with
> > > > > > RK3288.
> > > > > > 
> > > > > > Patch 1 splits out TCON code which is completely reusable on
> > > > > > all Allwinner SoCs.
> > > > > > 
> > > > > > Patch 2 converts common TCON code to use DM video compatible
> > > > > > timing
> > > > > > structure.
> > > > > > 
> > > > > > Patch 3 adds all necessary clocks which are needed for Display
> > > > > > Engine 2, TCON and HDMI.
> > > > > 
> > > > > I merged all these patches...
> > > > > 
> > > > > > Patch 4 implement actual DE2 and HDMI driver and patch 5 disables
> > > > > > HDMI
> > > > > > on all boards which don't have it (default is on).
> > > > > 
> > > > > But not this one, since it creates a Kconfig warning due to the
> > > > > dependency of I2C_EDID on DM_I2C.
> > > > > 
> > > > > I think the current state of this discussion is that the i2c driver
> > > > > should be converted to the DM, which seems to be stalled at the
> > > > > moment.
> > > > > 
> > > > > Could you take in that patch and do the minor rework that were
> > > > > suggested by Simon so that we can get this in ?
> > 
> > Sorry I missed what was suggested by Simon?
> 
> You have the history there:
> https://patchwork.ozlabs.org/patch/734375/

Rework of this patch gives me a bit of a headache.
1. Should I remove DM reset and clk calls since they are not yet supported by 
sunxi? If so, where should clocks be enabled? In board config?

2. SPL code uses old I2C interface for setting regulators, so all code which 
is called only in SPL but compiled also for U-Boot proper needs to be wrapped 
inside "#ifdef CONFIG_SPL_BUILD" or is there a better way? Example for that is 
drivers/power/sy8106a.c

3. Even if we solve everything nicely, most boards don't have anything 
attached to I2C besides power regulators, so I2C busses won't be probed 
anyway. This feels like a step back since you can't use i2c command unless 
device with available DM driver is defined in DT.

Regards,
Jernej
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Re: [U-Boot] [PATCH 2/2] asm-generic: global_data: change timebase_l/h to unsigned int

[Peng Fan]

Hi Simon,

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Monday, April 24, 2017 11:38 AM
> To: Peng Fan 
> Cc: U-Boot Mailing List ; Tom Rini
> ; Eddie Cai ; Jagan Teki
> ; york sun ; Robert P. J. Day
> ; Michal Simek 
> Subject: Re: [PATCH 2/2] asm-generic: global_data: change timebase_l/h to
> unsigned int
> 
> Hi Peng,
> 
> On 19 April 2017 at 19:10, Peng Fan  wrote:
> > Change type of timebase_l/h to unsigned int.
> 
> What is the motivation for this, please?

From lib/time.c: ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;

This piece code is based on that timebase_h and timebase_l are 32bits width, I 
think.
But unsigned long are 64bits width on ARM64. I am not sure, but I suppose same 
case
on other archs.

Thanks,
Peng.

> 
> >
> > Signed-off-by: Peng Fan 
> > Cc: Simon Glass 
> > Cc: Eddie Cai 
> > Cc: Jagan Teki 
> > Cc: York Sun 
> > Cc: "Robert P. J. Day" 
> > Cc: Michal Simek 
> > Cc: Tom Rini 
> > ---
> >
> > Buildman shows the following build failure, but not related this patch.
> >  aarch64:  +   orangepi_pc2
> >  x86:  +   qemu-x86_64 qemu-x86_efi_payload64 chromebook_link64
> >
> >  include/asm-generic/global_data.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> 
> Regards,
> Simon
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Re: [U-Boot] [PATCH 1/6] dm: mmc: omap_hsmmc: Update to support of-platdata

[Tom Rini]

On Sat, Apr 22, 2017 at 12:20:43PM +0530, Lokesh Vutla wrote:

> This is to aid platforms that uses OF_PLATDATA.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 2/6] dm: mmc: omap_hsmmc: Add pre-reloc flag to the driver

[Tom Rini]

On Sat, Apr 22, 2017 at 12:20:44PM +0530, Lokesh Vutla wrote:

> For platforms that don't use device tree in SPL the only
> way to mark this driver as 'required by relocation' is
> with the DM_FLAG_PRE_RELOC flag. Add this to ensure that
> the driver is bound.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 3/6] configs: am335x_evm: Use omap2 generic spl load script

[Tom Rini]

On Mon, Apr 24, 2017 at 10:23:17AM -0500, Andrew F. Davis wrote:
> On 04/22/2017 01:50 AM, Lokesh Vutla wrote:
> > No reason to use a separate load script for am33xx than using
> > omap-common load script.
> > 
> > Signed-off-by: Lokesh Vutla 
> > ---
> >  include/configs/am335x_evm.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
> > index fc8a08f5b7..796d5c32e9 100644
> > --- a/include/configs/am335x_evm.h
> > +++ b/include/configs/am335x_evm.h
> > @@ -194,7 +194,7 @@
> >  
> >  /* USB gadget RNDIS */
> >  
> > -#define CONFIG_SPL_LDSCRIPT
> > "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
> > +#define CONFIG_SPL_LDSCRIPT
> > "arch/arm/mach-omap2/u-boot-spl.lds"
> 
> Can we make this change to all other am335x platforms? They all are
> copy/paste from this config and now need to also be updated. After that
> we should delete am33xx/u-boot-spl.lds.

Agreed.  It looks like d0b5d9da5de2 needs to be done to
arch/arm/mach-omap2/u-boot-spl.lds as well, btw.

-- 
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Re: [U-Boot] [PATCH 5/6] configs: am335x_evm: Enable SPL_DM

[Tom Rini]

On Sat, Apr 22, 2017 at 12:20:47PM +0530, Lokesh Vutla wrote:

> Enable SPL_DM on all AM335x based TI platforms.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 4/6] am33xx: Provide platform data for mmc

[Tom Rini]

On Sat, Apr 22, 2017 at 12:20:46PM +0530, Lokesh Vutla wrote:
> Signed-off-by: Lokesh Vutla 
> ---
>  board/ti/am335x/board.c | 32 
>  1 file changed, 32 insertions(+)
> 
> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
> index 3e842d3187..566183e669 100644
> --- a/board/ti/am335x/board.c
> +++ b/board/ti/am335x/board.c
> @@ -9,6 +9,7 @@
>   */
>  
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -26,6 +27,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -892,3 +894,33 @@ void board_fit_image_post_process(void **p_image, size_t 
> *p_size)
>   secure_boot_verify_image(p_image, p_size);
>  }
>  #endif
> +
> +#if !CONFIG_IS_ENABLED(OF_CONTROL)
> +static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
> + .base_addr = (struct hsmmc *)0x4806,

OK.  So, off the top of my head, from Adam's series about converting
omap3, OMAP_HSMMC1_BASE and company aren't defined correctly?  Or we're
playing games with that 0x100 offset?  I bring this up as since we have
defines for these base addresses already, we should make use of them,
but in this case first we'll have to do... something, yes?

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Re: [U-Boot] [PATCH 6/6] arm: am335x: Enable tiny printf in SPL

[Tom Rini]

On Sat, Apr 22, 2017 at 12:20:48PM +0530, Lokesh Vutla wrote:

> am335x_evm SPL is very close to its limit in SRAM space.
> Switch to use tiny printf to reclaim some size.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [EXT] Armada 385: PEX detection pulse width

[Rene Straub]

Hello Adam,

first of all thanks the quick reply. First trials with reduced pulse length, 
showed promising results. To better understand the root cause of the problem, 
it would be helpful if you explained us briefly what the register change 
actually performs. I/we understand that the problem is related to the process 
of Rx Detection (measuring voltage change on PCIe link after a common mode 
step). Maybe we can implement a board change (PCIe lane coupling capacitors) to 
improve the detection, even with the default pulse length of the A385.

Best regards
-Rene


-Original Message-
From: Adam Shobash [mailto:ad...@marvell.com] 
Sent: Sonntag, 23. April 2017 19:29
To: Stefan Eichenberger 
Cc: Assaf Hoffman ; Rene Straub 
; s...@denx.de; u-boot@lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hi Stefan,

In A385, the register to change the pulse width is 0xa0120 bits[7:6].
Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see 
if it solves the issue.

But, please note that we tested our platforms with the value 0x1 only and we 
cannot guarantee that after you change this value that it will work for all the 
devices/add in cards other than Atheros .

Thanks,
Adam

-Original Message-
From: Stefan Eichenberger [mailto:stefan.eichenber...@netmodule.com] 
Sent: Friday, April 21, 2017 11:51 AM
To: Adam Shobash
Cc: Assaf Hoffman; René Straub; s...@denx.de; u-boot@lists.denx.de
Subject: [EXT] Armada 385: PEX detection pulse width

External Email

--
Dear Adam,

On the mainline u-boot we found a commit which helps to fix a problem regarding 
PCIe and the Armada 370:
http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0251f2aea

We currently facing a similar problem with the Armada 385 and PCIe. The problem 
also appears with two different Atheros chipsets one (AR9280) gets never 
detected and the other one gets detected most of the time but not always 
(QCA9882). With Intel modules on the other hand, we can't reproduce the issue. 
It's the same behaviour as described in the commit above, the link training 
fails and therefore the link is signalized as down. If a link is successfully 
established (QCA9882) we don't see any errors during communication.

Do you know if we have the same possibility on the Armada 385 to tune the PCI 
Express pulse width as you proposed it for the Armada 370?
Unfortunately the PCIe Phy seems to be quite different to the one from the 
Armada 370.

Best regards
Stefan
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Re: [U-Boot] [EXT] Armada 385: PEX detection pulse width

[Adam Shobash]

Hi Rene,

These bits that I have sent changes the pulse width of the "detection pulse" 
during the detect state, and purpose of it is to measure the slew rate of the 
common mode voltage change and according to the slew rate it is decided whether 
there is a Termination(usually it is the Rx impedance of the peer device) 
connected to the transmitter or not.
Now, the slew rate is affected from several things:
1.) The Rx DC impedance of the peer device  - which the spec requires to be 
between 40 to 60 ohm single ended.
2.) The DC block capacitors , Marvell recommends to use 100nF(and the PCIE spec 
requires to use between 75nF to 220nF).
3.) And in Marvell devices it depends also in the sample point.

And, as you suggested I believe that if you change the coupling capacitors to a 
higher value(150nF/200nF) and keep the default value of the sample point it 
will also help.
The default settings of the sample point + using 100nF capacitors in Marvell 
devices are good for devices that meet the spec, so we recommend to not change 
any settings, but we noticed in some Atheros wifi devices that Marvell devices 
are not able to detect their terminations and only for these devices you can 
change the sample point(or the capacitors as you suggested).

Thanks,
Adam

-Original Message-
From: Rene Straub [mailto:rene.str...@netmodule.com] 
Sent: Tuesday, April 25, 2017 8:44 AM
To: Adam Shobash; Stefan Eichenberger
Cc: Assaf Hoffman; s...@denx.de; u-boot@lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hello Adam,

first of all thanks the quick reply. First trials with reduced pulse length, 
showed promising results. To better understand the root cause of the problem, 
it would be helpful if you explained us briefly what the register change 
actually performs. I/we understand that the problem is related to the process 
of Rx Detection (measuring voltage change on PCIe link after a common mode 
step). Maybe we can implement a board change (PCIe lane coupling capacitors) to 
improve the detection, even with the default pulse length of the A385.

Best regards
-Rene


-Original Message-
From: Adam Shobash [mailto:ad...@marvell.com] 
Sent: Sonntag, 23. April 2017 19:29
To: Stefan Eichenberger 
Cc: Assaf Hoffman ; Rene Straub 
; s...@denx.de; u-boot@lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hi Stefan,

In A385, the register to change the pulse width is 0xa0120 bits[7:6].
Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see 
if it solves the issue.

But, please note that we tested our platforms with the value 0x1 only and we 
cannot guarantee that after you change this value that it will work for all the 
devices/add in cards other than Atheros .

Thanks,
Adam

-Original Message-
From: Stefan Eichenberger [mailto:stefan.eichenber...@netmodule.com] 
Sent: Friday, April 21, 2017 11:51 AM
To: Adam Shobash
Cc: Assaf Hoffman; René Straub; s...@denx.de; u-boot@lists.denx.de
Subject: [EXT] Armada 385: PEX detection pulse width

External Email

--
Dear Adam,

On the mainline u-boot we found a commit which helps to fix a problem regarding 
PCIe and the Armada 370:
http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0251f2aea

We currently facing a similar problem with the Armada 385 and PCIe. The problem 
also appears with two different Atheros chipsets one (AR9280) gets never 
detected and the other one gets detected most of the time but not always 
(QCA9882). With Intel modules on the other hand, we can't reproduce the issue. 
It's the same behaviour as described in the commit above, the link training 
fails and therefore the link is signalized as down. If a link is successfully 
established (QCA9882) we don't see any errors during communication.

Do you know if we have the same possibility on the Armada 385 to tune the PCI 
Express pulse width as you proposed it for the Armada 370?
Unfortunately the PCIe Phy seems to be quite different to the one from the 
Armada 370.

Best regards
Stefan
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[U-Boot] [PATCH] config: remove CONFIG_SPI_FLASH_BAR from some platforms

[Suresh Gupta]

ls1012ardb, ls1046ardb, ls2080ardb has S25FS512S
flash which do not support Bank Address Register commands

Signed-off-by: Suresh Gupta 
---
 include/configs/ls1012a_common.h | 1 -
 include/configs/ls1046ardb.h | 1 -
 include/configs/ls2080ardb.h | 1 -
 3 files changed, 3 deletions(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 09f890d..0db926f 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -55,7 +55,6 @@
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_BAR
 
 #define FSL_QSPI_FLASH_SIZE(1 << 24)
 #define FSL_QSPI_FLASH_NUM 2
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 67ee626..66af039 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -208,7 +208,6 @@
 #define CONFIG_SPI_FLASH_SPANSION
 #define FSL_QSPI_FLASH_SIZE(1 << 26)
 #define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_BAR
 #endif
 #endif
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 2155a89..79a3d94 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -265,7 +265,6 @@ unsigned long get_board_sys_clk(void);
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
 
-- 
1.9.3

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Re: [U-Boot] [EXT] Armada 385: PEX detection pulse width

[Assaf Hoffman]

+ Torsten

-Original Message-
From: Adam Shobash 
Sent: Tuesday, April 25, 2017 10:26 AM
To: Rene Straub; Stefan Eichenberger
Cc: Assaf Hoffman; s...@denx.de; u-boot@lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hi Rene,

These bits that I have sent changes the pulse width of the "detection pulse" 
during the detect state, and purpose of it is to measure the slew rate of the 
common mode voltage change and according to the slew rate it is decided whether 
there is a Termination(usually it is the Rx impedance of the peer device) 
connected to the transmitter or not.
Now, the slew rate is affected from several things:
1.) The Rx DC impedance of the peer device  - which the spec requires to be 
between 40 to 60 ohm single ended.
2.) The DC block capacitors , Marvell recommends to use 100nF(and the PCIE spec 
requires to use between 75nF to 220nF).
3.) And in Marvell devices it depends also in the sample point.

And, as you suggested I believe that if you change the coupling capacitors to a 
higher value(150nF/200nF) and keep the default value of the sample point it 
will also help.
The default settings of the sample point + using 100nF capacitors in Marvell 
devices are good for devices that meet the spec, so we recommend to not change 
any settings, but we noticed in some Atheros wifi devices that Marvell devices 
are not able to detect their terminations and only for these devices you can 
change the sample point(or the capacitors as you suggested).

Thanks,
Adam

-Original Message-
From: Rene Straub [mailto:rene.str...@netmodule.com] 
Sent: Tuesday, April 25, 2017 8:44 AM
To: Adam Shobash; Stefan Eichenberger
Cc: Assaf Hoffman; s...@denx.de; u-boot@lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hello Adam,

first of all thanks the quick reply. First trials with reduced pulse length, 
showed promising results. To better understand the root cause of the problem, 
it would be helpful if you explained us briefly what the register change 
actually performs. I/we understand that the problem is related to the process 
of Rx Detection (measuring voltage change on PCIe link after a common mode 
step). Maybe we can implement a board change (PCIe lane coupling capacitors) to 
improve the detection, even with the default pulse length of the A385.

Best regards
-Rene


-Original Message-
From: Adam Shobash [mailto:ad...@marvell.com] 
Sent: Sonntag, 23. April 2017 19:29
To: Stefan Eichenberger 
Cc: Assaf Hoffman ; Rene Straub 
; s...@denx.de; u-boot@lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hi Stefan,

In A385, the register to change the pulse width is 0xa0120 bits[7:6].
Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see 
if it solves the issue.

But, please note that we tested our platforms with the value 0x1 only and we 
cannot guarantee that after you change this value that it will work for all the 
devices/add in cards other than Atheros .

Thanks,
Adam

-Original Message-
From: Stefan Eichenberger [mailto:stefan.eichenber...@netmodule.com] 
Sent: Friday, April 21, 2017 11:51 AM
To: Adam Shobash
Cc: Assaf Hoffman; René Straub; s...@denx.de; u-boot@lists.denx.de
Subject: [EXT] Armada 385: PEX detection pulse width

External Email

--
Dear Adam,

On the mainline u-boot we found a commit which helps to fix a problem regarding 
PCIe and the Armada 370:
http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0251f2aea

We currently facing a similar problem with the Armada 385 and PCIe. The problem 
also appears with two different Atheros chipsets one (AR9280) gets never 
detected and the other one gets detected most of the time but not always 
(QCA9882). With Intel modules on the other hand, we can't reproduce the issue. 
It's the same behaviour as described in the commit above, the link training 
fails and therefore the link is signalized as down. If a link is successfully 
established (QCA9882) we don't see any errors during communication.

Do you know if we have the same possibility on the Armada 385 to tune the PCI 
Express pulse width as you proposed it for the Armada 370?
Unfortunately the PCIe Phy seems to be quite different to the one from the 
Armada 370.

Best regards
Stefan
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[U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

As per data sheet, S25FS512S support Uniform sector option
or erase size of 256 kbytes and Page Programming buffer of
256 or 512 Bytes. So, flag SECT_4K have no significance
for this flash.

Signed-off-by: Suresh Gupta 
---
 drivers/mtd/spi/spi_flash_ids.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index edca94e..7ca33e8 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -101,7 +101,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
WR_QPP) },
{"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
WR_QPP) },
{"s25fs256s_64k",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
-   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
+   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | 
WR_QPP) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
{"s25fl512s_64k",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | 
WR_QPP) },
{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
-- 
1.9.3

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[U-Boot] [PATCH] LS1012A: change the size of flash

[Suresh Gupta]

LS1012A has S25FS512S flash of 64M size

Signed-off-by: Suresh Gupta 
---
 include/configs/ls1012a_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 0db926f..861cbc3 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -56,7 +56,7 @@
 #define QSPI0_AMBA_BASE0x4000
 #define CONFIG_SPI_FLASH_SPANSION
 
-#define FSL_QSPI_FLASH_SIZE(1 << 24)
+#define FSL_QSPI_FLASH_SIZESZ_64M
 #define FSL_QSPI_FLASH_NUM 2
 
 /*
-- 
1.9.3

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[U-Boot] [Turris Omnia] Is there a standard approach to write a driver for CryptoAuthentication/EEPROM chip?

[Marek Behún]

Hello,
I have few questions about upstreaming support for the Turris Omnia
into u-boot.

The Turris Omnia has (on I2C interface) an Atmel ATSHA204
CryptoAuthentication chip for storage of MAC adresses, device serial
number, device configuration (1 GB RAM vs 2 GB RAM). This data is
stored in the internal EEPROM of ATSHA204. The chip is capable of more:
for example there is also a random number generator. For more info see
http://www.atmel.com/Images/Atmel-8740-CryptoAuth-ATSHA204-Datasheet.pdf

I want to write support for the ATSHA204 for upstream U-Boot so that I
can then continue working on support for Turris Omnia. Currently we
have our internal branch of U-Boot, in which the ATSHA204 code is in
drivers/misc (see
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot/blob/master/drivers/misc/atsha204-i2c.c
).

My question: Does U-Boot have a standard approach how to write a driver
for such a chip? Does this device need to be defined in the Device Tree?

Thank you.

Marek
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[U-Boot] [PATCH] LS1088A: PPA Enable for ls1088a rdb and qds.

[Amrita Kumari]

Signed-off-by: Amrita Kumari 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
 board/freescale/ls1088a/ls1088a.c | 4 
 configs/ls1088aqds_qspi_defconfig | 1 +
 configs/ls1088ardb_qspi_defconfig | 1 +
 4 files changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 8270431..39e6832 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -193,6 +193,7 @@ config SYS_LS_PPA_FW_ADDR
depends on FSL_LS_PPA
default 0x4050 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x580a0 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+   default 0x20a0 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
default 0x6050 if SYS_LS_PPA_FW_IN_XIP
default 0x50 if SYS_LS_PPA_FW_IN_MMC
default 0x50 if SYS_LS_PPA_FW_IN_NAND
diff --git a/board/freescale/ls1088a/ls1088a.c 
b/board/freescale/ls1088a/ls1088a.c
index 034ef54..0cb715a 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../common/qixis.h"
 #include "ls1088a_qixis.h"
@@ -312,6 +313,9 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+   ppa_init();
+#endif
return 0;
 }
 
diff --git a/configs/ls1088aqds_qspi_defconfig 
b/configs/ls1088aqds_qspi_defconfig
index 3511d92..09c2ce1 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -25,3 +25,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1088ardb_qspi_defconfig 
b/configs/ls1088ardb_qspi_defconfig
index a0559a7..b7b3428 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -25,3 +25,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_LS_PPA=y
-- 
2.7.4

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[U-Boot] [Turris Omnia] Btrfs support status?

[Marek Behún]

Hello,

the Turris Omnia router uses btrfs as the main filesystem, from which
it also loads kernel and dts. We have an implementation in our internal
u-boot
(https://gitlab.labs.nic.cz/turris/turris-omnia-uboot/tree/master/fs/btrfs).

As I understand it, this code was already proposed for u-boot:
https://patchwork.ozlabs.org/patch/300593/ . Is this true? Why was it
not accepted? Does this code need to be rewritten, or something? Or is
there simply no interest in mainlining support for btrfs?

Thank you.

Marek Behun
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[U-Boot] "syntax error" after erasing flash sector

[Ohad Peleg]

hello, from the hush cli im trying to update the uboot within the uboot.
but after erasing a flash sector (which is succeded) i get: "syntax error"
 for every coomand.. im not sure why, uboot supposed to run from ram at
this point so why does it matter i erased the flash?
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Re: [U-Boot] [PATCH] patman: encode CC list to UTF-8

[Dr. Philipp Tomsich]

Hi Simon,

> On 25 Apr 2017, at 22:31, Simon Glass  wrote:
> 
> Hi Tom,
> 
> On 25 April 2017 at 11:12, Tom Rini  wrote:
>> 
>> On Sat, Apr 22, 2017 at 05:53:36PM -0600, Simon Glass wrote:
>>> +Tom
>>> 
>>> On 19 April 2017 at 07:24, Philipp Tomsich
>>>  wrote:
 
 This change encodes the CC list to UTF-8 to avoid failures on
 maintainer-addresses that include non-ASCII characters (observed on
 Debian 7.11 with Python 2.7.3).
 
 Without this, I get the following failure:
  Traceback (most recent call last):
File "tools/patman/patman", line 159, in 
  options.add_maintainers)
File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile
  print(commit.patch, ', '.join(set(list)), file=fd)
  UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in 
 position 81: ordinal not in range(128)
 from Heiko's email address:
  [..., u'"Heiko St\xfcbner" ', ...]
 
 While with this change added this encodes to:
  "=?UTF-8?q?Heiko=20St=C3=BCbner?= "
 
 Signed-off-by: Philipp Tomsich 
 ---
 
 tools/patman/series.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
>>> 
>>> Reviewed-by: Simon Glass 
>> 
>> Please put this in a PR for me, along with any other critical fixes to
>> the various python tools we have, thanks!
>> 
>> And also, do we need to perhaps whack something at a higher level, and
>> more consistently, about unicode?  This is, I gather, doing UTF-8 right.
>> In buildman we have a few patches to just translate to latin-1 instead.
>> We should do the same thing I think, and perhaps there's a higher level
>> up in the code where we need to do it too?  I don't know..
> 
> Actually I don't think we are quite there yet. This really needs a
> test with all the different places strings can come from, to make sure
> patman does the right thing.

On the topic of ‘different places strings can come from’, here’s another
change from my WIP tree that fixes some other UTF-8 issues in patman
and may point you towards another trouble spot:

@@ -229,14 +229,16 @@ class Series(dict):
raise_on_error=raise_on_error)
 if add_maintainers:
 list += get_maintainer.GetMaintainer(commit.patch)
+list = [s.encode('utf-8') for s in list]
 all_ccs += list
-print(commit.patch, ', '.join(set(list)).encode('utf-8'), file=fd)
+print(commit.patch, ', '.join(set(list)), file=fd)
 self._generated_cc[commit.patch] = list
 
 if cover_fname:
 cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
-cc_list = ', '.join([x.decode('utf-8') for x in set(cover_cc + 
all_ccs)])
-print(cover_fname, cc_list.encode('utf-8'), file=fd)
+cover_cc = [s.encode('utf-8') for s in cover_cc]
+cc_list = ', '.join([x for x in set(cover_cc + all_ccs)])
+print(cover_fname, cc_list, file=fd)
 
 fd.close()
 return fname


Regards,
Philipp.
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[U-Boot] [U-boot] use of CONFIG_SYS_EARLY_PCI_INIT with DM PCI

[Suneel Garapati]

Hi Simon,

Request your inputs on below query -

Boards I work on have most of the devices on PCI bus, driver model
support enabled, would like to use CONFIG_SYS_EARLY_PCI_INIT to call
pci_init but the below snippet would hinder.

 #ifdef CONFIG_PCI
 static int initr_pci(void)
 {
-#ifndef CONFIG_DM_PCI
pci_init();
-#endif


Is this change valid or should create another config item for driver
model based early pci init?

Regards,
Suneel
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Re: [U-Boot] [PATCH 4/6] am33xx: Provide platform data for mmc

[Adam Ford]

On Tue, Apr 25, 2017 at 4:10 PM, Tom Rini  wrote:
> On Sat, Apr 22, 2017 at 12:20:46PM +0530, Lokesh Vutla wrote:
>> Signed-off-by: Lokesh Vutla 
>> ---
>>  board/ti/am335x/board.c | 32 
>>  1 file changed, 32 insertions(+)
>>
>> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
>> index 3e842d3187..566183e669 100644
>> --- a/board/ti/am335x/board.c
>> +++ b/board/ti/am335x/board.c
>> @@ -9,6 +9,7 @@
>>   */
>>
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -26,6 +27,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -892,3 +894,33 @@ void board_fit_image_post_process(void **p_image, 
>> size_t *p_size)
>>   secure_boot_verify_image(p_image, p_size);
>>  }
>>  #endif
>> +
>> +#if !CONFIG_IS_ENABLED(OF_CONTROL)
>> +static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
>> + .base_addr = (struct hsmmc *)0x4806,
>
> OK.  So, off the top of my head, from Adam's series about converting
> omap3, OMAP_HSMMC1_BASE and company aren't defined correctly?  Or we're
> playing games with that 0x100 offset?  I bring this up as since we have
> defines for these base addresses already, we should make use of them,
> but in this case first we'll have to do... something, yes?
>

The base address for the AM335xx he has listed is correct at 0x480600,
however the offset is 0x100.  Without without my patch I would expect
this to correctly.  SYSCONFIG is at offset 0x110 and for OMAP3 the
offset would be 0x10.  His patch looks like it supports the condition
without OF_CONTROL, so maybe using a #define here would be
appropriate, however without OF_CONFIG, I am guessing my patch would
break stuff.

I only did my series to eliminate the #ifdef stuff, but we might have
to add something like && !define (OF_CONTROL) to my series.

If you want to pull his in, I can rebase and resubmit my series
against his.  I don't have an AM33xx or OMAP4+ to test, I only have a
DM3730 to test.

adam
> --
> Tom
>
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[U-Boot] [PATCH v4 01/20] SPL: FIT: refactor FDT loading

[Andre Przywara]

Currently the SPL FIT loader uses the spl_fit_select_fdt() function to
find the offset to the right DTB within the FIT image.
For this it iterates over all subnodes of the /configuration node in
the FIT tree and compares all "description" strings therein using a
board specific matching function.
If that finds a match, it uses the string in the "fdt" property of that
subnode to locate the matching subnode in the /images node, which points
to the DTB data.
Now this works very well, but is quite specific to cover this particular
use case. To open up the door for a more generic usage, let's split this
function into:
1) a function that just returns the node offset for the matching
   configuration node (spl_fit_find_config_node())
2) a function that returns the image data any given property in a given
   configuration node points to, additionally using a given index into
   a possbile list of strings (spl_fit_select_index())
This allows us to replace the specific function above by asking for the
image the _first string of the "fdt" property_ in the matching
configuration subnode points to.

This patch introduces no functional changes, it just refactors the code
to allow reusing it later.

(diff is overly clever here and produces a hard-to-read patch, so I
recommend to throw a look at the result instead).

Signed-off-by: Andre Przywara 
Reviewed-by: Lokesh Vutla 
Reviewed-by: Simon Glass 
---
 common/spl/spl_fit.c | 88 ++--
 1 file changed, 57 insertions(+), 31 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aae556f..67372ca 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -22,13 +22,16 @@ static ulong fdt_getprop_u32(const void *fdt, int node, 
const char *prop)
return fdt32_to_cpu(*cell);
 }
 
-static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
+/*
+ * Iterate over all /configurations subnodes and call a platform specific
+ * function to find the matching configuration.
+ * Returns the node offset or a negative error number.
+ */
+static int spl_fit_find_config_node(const void *fdt)
 {
-   const char *name, *fdt_name;
-   int conf, node, fdt_node;
-   int len;
+   const char *name;
+   int conf, node, len;
 
-   *fdt_offsetp = 0;
conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
if (conf < 0) {
debug("%s: Cannot find /configurations node: %d\n", __func__,
@@ -50,39 +53,61 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
continue;
 
debug("Selecting config '%s'", name);
-   fdt_name = fdt_getprop(fdt, node, FIT_FDT_PROP, &len);
-   if (!fdt_name) {
-   debug("%s: Cannot find fdt name property: %d\n",
- __func__, len);
-   return -EINVAL;
-   }
 
-   debug(", fdt '%s'\n", fdt_name);
-   fdt_node = fdt_subnode_offset(fdt, images, fdt_name);
-   if (fdt_node < 0) {
-   debug("%s: Cannot find fdt node '%s': %d\n",
- __func__, fdt_name, fdt_node);
-   return -EINVAL;
+   return node;
+   }
+
+   return -ENOENT;
+}
+
+static int spl_fit_select_index(const void *fit, int images, int *offsetp,
+   const char *type, int index)
+{
+   const char *name, *str;
+   int node, conf_node;
+   int len, i;
+
+   *offsetp = 0;
+   conf_node = spl_fit_find_config_node(fit);
+   if (conf_node < 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("No matching DT out of these options:\n");
+   for (node = fdt_first_subnode(fit, conf_node);
+node >= 0;
+node = fdt_next_subnode(fit, node)) {
+   name = fdt_getprop(fit, node, "description", &len);
+   printf("   %s\n", name);
}
+#endif
+   return conf_node;
+   }
 
-   *fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
-   len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-   debug("FIT: Selected '%s'\n", name);
+   name = fdt_getprop(fit, conf_node, type, &len);
+   if (!name) {
+   debug("cannot find property '%s': %d\n", type, len);
+   return -EINVAL;
+   }
 
-   return len;
+   str = name;
+   for (i = 0; i < index; i++) {
+   str = strchr(str, '\0') + 1;
+   if (!str || (str - name >= len)) {
+   debug("no string for index %d\n", index);
+   return -E2BIG;
+   }
}
 
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   printf("No matching DT out of these options:\n");
-   for (node = fdt_first_subnode(fdt, conf);
-node >= 0;
-  

[U-Boot] [PATCH v4 00/20] SPL: extend FIT loading support

[Andre Przywara]

Another round of smaller fixes for the SPL FIT loading series and the
respective patches to enable this feature on 64-bit Allwinner SoCs.
The README has been changed to address all 64-bit Allwinner boards and
has consequently been renamed to README.sunxi64. Also we can now point
U-Boot to the ARM Trusted Firmware build by specifying the filename in
the BL31 environment variable. If this is not set, we default to look
for bl31.bin in U-Boot's build directory.
The other minor fixes are detailed in the Changelog below.
---

The first five patches introduce the core of the extened SPL FIT loading
support, see below for a description. Patch 6 fixes a Kconfig dependency
to simplify the usage of this option.
Patches 7-10 make some room in the sunxi 64-bit SPL to allow
compiling in the FIT loading bits. Patch 11 and 12 let the SPL choose
the proper DT from the FIT image.
The next two patches add the infrastructure and an actual generator script,
so the FIT image is automatically created at build time.
Patches 14, 15 and 16 enable the SPL FIT support for Allwinner 64-bit SoCs in
general and for the Pine64 and OrangePi PC 2 in particular.
The following two patches store a DT file name in the SPL header, so
U-Boot can easily pick the proper DT when scanning the FIT image.
The idea is that this DT name should stay with the board, ideally on
eMMC or SPI flash. So both U-Boot and a firmware update tool could
identify a board, updating with compatible firmware while keeping the
DT name in place. Ideally a board vendor would once seed this name
onto on-board storage like SPI flash.
I kept those two patches in, as the work on replacing mksunxiboot with
an mkimage extension is not ready yet. Feel free to drop those from
the series if this is a problem.
The penultimate patch updates the Pine64 README file to document the current
way of building U-Boot, which now includes the ARM Trusted Firmware build
in its image.
The last patch moves the maintainership from Hans over to me.

I would be delighted if that series could get merged into the sunxi tree.
This finally enables the fully open source firmware for the 64-bit
Allwinner SoCs (including the ATF binary).

This series is based on current sunxi/master.

Cheers,
Andre.

---
Currently the FIT format is not used to its full potential in the SPL:
It only loads the first image from the /images node and appends the
proper FDT.
Some boards and platforms would benefit from loading more images before
starting U-Boot proper, notably Allwinner A64 and ARMv8 Rockchip boards,
which use an ARM Trusted Firmware (ATF) image to be executed before U-Boot.

This series tries to solve this in a board agnostic and generic way:
We extend the SPL FIT loading scheme to allow loading multiple images.
So apart from loading the image which is referenced by the "firmware"
property in the respective configuration node and placing the DTB right
behind it, we iterate over all strings in the "loadable" property.
Each image referenced there will be loaded to its specified load address.
The entry point U-Boot eventually branches to will be taken from the
first image to explicitly provide the "entry" property, or, if none
of them does so, from the load address of the "firmware" image.
This keeps the scheme compatible with the FIT images our Makefile creates
automatically at the moment.
Apart from the already mentioned ATF scenario this opens up more usage
scenarios, of which the commit message of patch 04/11 lists some.
The remaining patches prepare ane finally enable this scheme for the 64-bit
Allwinner boards.

Changelog v3 ... v4:
- [01/20]: return proper error codes instead of just -1 (+Simon's RB)
- [02/20]: improve kernel-doc comment (+Simon's RB)
- [03/20]: return proper error codes instead of just -1 (+Simon's RB)
- [04/20]: improve kernel-doc comment and error codes (+Simon's RB)
- [05/20]: add example .its source file (+Simon's RB)
- [10,11,12/20]: add Maxime's Acked-by
- [14/20]: add BL31 environment variable (+Maxime's Acked-by)
- [15/20]: drop unneeded OrangePi PC2 change
- [16/20]: add Maxime's Acked-by
- [19/20]: rewrite to be more generic, rename to README.sunxi64
- [20/20]: new patch to change maintainership

Changelog v2 ... v3:
- new patch 06/19 to improve SPL_FIT Kconfig dependencies
- rename symbol in mksunxiboot (SUNXI_SRAM instead of SUN4I_SRAM)
- enable SPL_LOAD_FIT for all Allwinner A64 and H5 boards in Kconfig
- add only CONFIG_OF_LIST to defconfigs (patch 15/19)

Changelog v1 ... v2:
- Add some function comments to spl_fit.c (patch 1-5)
- Improve error handling in SPL FIT code (patch 1-5)
- Fix bisectability (observing entry-point property)
- add documentation to doc/uImage.FIT/howto.txt
- fix Freescale CCN504 build failure
- (no changes in the last 10 patches)
- update README.pine64 (new last patch)
- add Reviewed-by's from Simon and Lokesh

--
Andre Przywara (19):
  SPL: FIT: refactor FDT loading
  SPL: FIT: rework U-Boot image loading
  SPL: FIT: improve error handling
  SPL

[U-Boot] [PATCH v4 04/20] SPL: FIT: factor out spl_load_fit_image()

[Andre Przywara]

At the moment we load two images from a FIT image: the actual U-Boot
image and the .dtb file. Both times we have very similar code, that deals
with alignment requirements the media we load from imposes upon us.
Factor out this code into a new function, which we just call twice.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 common/spl/spl_fit.c | 162 +--
 1 file changed, 80 insertions(+), 82 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index ecd42d8..9d9338c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -159,19 +159,81 @@ static int get_aligned_image_size(struct spl_load_info 
*info, int data_size,
return (data_size + info->bl_len - 1) / info->bl_len;
 }
 
+/**
+ * spl_load_fit_image(): load the image described in a certain FIT node
+ * @info:  points to information about the device to load data from
+ * @sector:the start sector of the FIT image on the device
+ * @fit:   points to the flattened device tree blob describing the FIT
+ * image
+ * @base_offset: the beginning of the data area containing the actual
+ * image data, relative to the beginning of the FIT
+ * @node:  offset of the DT node describing the image to load (relative
+ * to @fit)
+ * @image_info:will be filled with information about the loaded image
+ * If the FIT node does not contain a "load" (address) property,
+ * the image gets loaded to the address pointed to by the
+ * load_addr member in this struct.
+ *
+ * Return: 0 on success or a negative error number.
+ */
+static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
+ void *fit, ulong base_offset, int node,
+ struct spl_image_info *image_info)
+{
+   ulong offset;
+   size_t length;
+   ulong load_addr, load_ptr;
+   void *src;
+   ulong overhead;
+   int nr_sectors;
+   int align_len = ARCH_DMA_MINALIGN - 1;
+
+   offset = fdt_getprop_u32(fit, node, "data-offset");
+   if (offset == FDT_ERROR)
+   return -ENOENT;
+   offset += base_offset;
+   length = fdt_getprop_u32(fit, node, "data-size");
+   if (length == FDT_ERROR)
+   return -ENOENT;
+   load_addr = fdt_getprop_u32(fit, node, "load");
+   if (load_addr == FDT_ERROR && image_info)
+   load_addr = image_info->load_addr;
+   load_ptr = (load_addr + align_len) & ~align_len;
+
+   overhead = get_aligned_image_overhead(info, offset);
+   nr_sectors = get_aligned_image_size(info, length, offset);
+
+   if (info->read(info, sector + get_aligned_image_offset(info, offset),
+  nr_sectors, (void*)load_ptr) != nr_sectors)
+   return -EIO;
+   debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
+ (unsigned long)length);
+
+   src = (void *)load_ptr + overhead;
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+   board_fit_image_post_process(&src, &length);
+#endif
+
+   memcpy((void*)load_addr, src, length);
+
+   if (image_info) {
+   image_info->load_addr = load_addr;
+   image_info->size = length;
+   image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
+   }
+
+   return 0;
+}
+
 int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
 {
int sectors;
-   ulong size, load;
+   ulong size;
unsigned long count;
-   int node, images;
-   void *load_ptr;
-   int fdt_offset, fdt_len;
-   int data_offset, data_size;
+   struct spl_image_info image_info;
+   int node, images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
-   int src_sector;
-   void *dst, *src;
 
/*
 * Figure out where the external images start. This is the base for the
@@ -223,46 +285,13 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
return -1;
}
 
-   /* Get its information and set up the spl_image structure */
-   data_offset = fdt_getprop_u32(fit, node, "data-offset");
-   if (data_offset == FDT_ERROR)
-   return -ENOENT;
-   data_size = fdt_getprop_u32(fit, node, "data-size");
-   if (data_size == FDT_ERROR)
-   return -ENOENT;
-   load = fdt_getprop_u32(fit, node, "load");
-   debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
-   spl_image->load_addr = load;
-   spl_image->entry_point = load;
-   spl_image->os = IH_OS_U_BOOT;
-
-   /*
-* Work out where to place the image. We read it so that the first
-* byte will be at 'load'. This may mean we need to load it starting
-* before then, since we can only read whole blocks.
-*/
-   data_off

[U-Boot] [PATCH v4 02/20] SPL: FIT: rework U-Boot image loading

[Andre Przywara]

Currently the SPL FIT loader always looks only for the first image in
the /images node a FIT tree, which it loads and later executes.

Generalize this by looking for a "firmware" property in the matched
configuration subnode, or, if that does not exist, for the first string
in the "loadables" property. Then using the string in that property,
load the image of that name from the /images node.
This still loads only one image at the moment, but refactors the code to
allow extending this in a following patch.
To simplify later re-usage, we also generalize the spl_fit_select_index()
function to not return the image location, but just the node offset.

Signed-off-by: Andre Przywara 
Reviewed-by: Lokesh Vutla 
Reviewed-by: Simon Glass 
---
 common/spl/spl_fit.c | 46 --
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 67372ca..85af980 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -60,14 +60,25 @@ static int spl_fit_find_config_node(const void *fdt)
return -ENOENT;
 }
 
-static int spl_fit_select_index(const void *fit, int images, int *offsetp,
-   const char *type, int index)
+/**
+ * spl_fit_get_image_node(): By using the matching configuration subnode,
+ * retrieve the name of an image, specified by a property name and an index
+ * into that.
+ * @fit:   Pointer to the FDT blob.
+ * @images:Offset of the /images subnode.
+ * @type:  Name of the property within the configuration subnode.
+ * @index: Index into the list of strings in this property.
+ *
+ * Return: the node offset of the respective image node or a negative
+ * error number.
+ */
+static int spl_fit_get_image_node(const void *fit, int images,
+ const char *type, int index)
 {
const char *name, *str;
int node, conf_node;
int len, i;
 
-   *offsetp = 0;
conf_node = spl_fit_find_config_node(fit);
if (conf_node < 0) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -104,10 +115,7 @@ static int spl_fit_select_index(const void *fit, int 
images, int *offsetp,
return -EINVAL;
}
 
-   *offsetp = fdt_getprop_u32(fit, node, "data-offset");
-   len = fdt_getprop_u32(fit, node, "data-size");
-
-   return len;
+   return node;
 }
 
 static int get_aligned_image_offset(struct spl_load_info *info, int offset)
@@ -193,15 +201,22 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (count == 0)
return -EIO;
 
-   /* find the firmware image to load */
+   /* find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
return -1;
}
-   node = fdt_first_subnode(fit, images);
+
+   /* find the U-Boot image */
+   node = spl_fit_get_image_node(fit, images, "firmware", 0);
if (node < 0) {
-   debug("%s: Cannot find first image node: %d\n", __func__, node);
+   debug("could not find firmware image, trying loadables...\n");
+   node = spl_fit_get_image_node(fit, images, "loadables", 0);
+   }
+   if (node < 0) {
+   debug("%s: Cannot find u-boot image node: %d\n",
+ __func__, node);
return -1;
}
 
@@ -243,10 +258,13 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
memcpy(dst, src, data_size);
 
/* Figure out which device tree the board wants to use */
-   fdt_len = spl_fit_select_index(fit, images, &fdt_offset,
-  FIT_FDT_PROP, 0);
-   if (fdt_len < 0)
-   return fdt_len;
+   node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
+   if (node < 0) {
+   debug("%s: cannot find FDT node\n", __func__);
+   return node;
+   }
+   fdt_offset = fdt_getprop_u32(fit, node, "data-offset");
+   fdt_len = fdt_getprop_u32(fit, node, "data-size");
 
/*
 * Read the device tree and place it after the image. There may be
-- 
2.8.2

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[U-Boot] [PATCH v4 08/20] armv8: SPL: only compile GIC code if needed

[Andre Przywara]

Not every SoC needs to set up the GIC interrupt controller, so link
think code only when the respective config option is set.
This shaves off some bytes from the SPL code size.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 arch/arm/lib/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 6e96cfb..4efa37b 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -44,7 +44,9 @@ ifdef CONFIG_CPU_V7M
 obj-y  += interrupts_m.o
 else ifdef CONFIG_ARM64
 obj-y  += ccn504.o
+ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
 obj-y  += gic_64.o
+endif
 obj-y  += interrupts_64.o
 else
 obj-y  += interrupts.o
-- 
2.8.2

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[U-Boot] [PATCH v4 05/20] SPL: FIT: allow loading multiple images

[Andre Przywara]

So far we were not using the FIT image format to its full potential:
The SPL FIT loader was just loading the first image from the /images
node plus one of the listed DTBs.
Now with the refactored loader code it's easy to load an arbitrary
number of images in addition to the two mentioned above.
As described in the FIT image source file format description, iterate
over all images listed at the "loadables" property in the configuration
node and load every image at its desired location.
This allows to load any kind of images:
- firmware images to execute before U-Boot proper (for instance
  ARM Trusted Firmware (ATF))
- firmware images for management processors (SCP, arisc, ...)
- firmware images for devices like WiFi controllers
- bit files for FPGAs
- additional configuration data
- kernels and/or ramdisks
The actual usage of this feature would be platform and/or board specific.

Also update the FIT documentation to mention the new SPL feature and
provide an example .its file to demonstrate its features.

Signed-off-by: Andre Przywara 
Reviewed-by: Lokesh Vutla 
Reviewed-by: Simon Glass 
---
 common/spl/spl_fit.c | 42 -
 doc/uImage.FIT/howto.txt | 21 +++
 doc/uImage.FIT/multi_spl.its | 89 
 3 files changed, 150 insertions(+), 2 deletions(-)
 create mode 100644 doc/uImage.FIT/multi_spl.its

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 9d9338c..4c42a96 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -234,6 +234,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_image_info image_info;
int node, images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
+   int index = 0;
 
/*
 * Figure out where the external images start. This is the base for the
@@ -278,6 +279,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
node = spl_fit_get_image_node(fit, images, "loadables", 0);
+   /*
+* If we pick the U-Boot image from "loadables", start at
+* the second image when later loading additional images.
+*/
+   index = 1;
}
if (node < 0) {
debug("%s: Cannot find u-boot image node: %d\n",
@@ -305,6 +311,38 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 * Align the destination address to ARCH_DMA_MINALIGN.
 */
image_info.load_addr = spl_image->load_addr + spl_image->size;
-   return spl_load_fit_image(info, sector, fit, base_offset, node,
- &image_info);
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+&image_info);
+   if (ret < 0)
+   return ret;
+
+   /* Now check if there are more images for us to load */
+   for (; ; index++) {
+   node = spl_fit_get_image_node(fit, images, "loadables", index);
+   if (node < 0)
+   break;
+
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+&image_info);
+   if (ret < 0)
+   continue;
+
+   /*
+* If the "firmware" image did not provide an entry point,
+* use the first valid entry point from the loadables.
+*/
+   if (spl_image->entry_point == FDT_ERROR &&
+   image_info.entry_point != FDT_ERROR)
+   spl_image->entry_point = image_info.entry_point;
+   }
+
+   /*
+* If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
+* Makefile will set it to 0 and it will end up as the entry point
+* here. What it actually means is: use the load address.
+*/
+   if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0)
+   spl_image->entry_point = spl_image->load_addr;
+
+   return 0;
 }
diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt
index 14e316f..2988a52 100644
--- a/doc/uImage.FIT/howto.txt
+++ b/doc/uImage.FIT/howto.txt
@@ -44,6 +44,27 @@ image source file mkimage + dtctransfer to 
target
+---> image file > bootm
 image data file(s)
 
+SPL usage
+-
+
+The SPL can make use of the new image format as well, this traditionally
+is used to ship multiple device tree files within one image. Code in the SPL
+will choose the one matching the current board and append this to the
+U-Boot proper binary to be automatically used up by it.
+Aside from U-Boot proper and one device tree blob the SPL can load multiple,
+arbitrary image files as well. These binaries should be specified in their
+own subnode under the /ima

[U-Boot] [PATCH v4 07/20] tools: mksunxiboot: allow larger SPL binaries

[Andre Przywara]

mksunxiboot limits the size of the resulting SPL binaries to pretty
conservative values to cover all SoCs and all boot media (NAND).
It turns out that we have limit checks in place in the build process,
so mksunxiboot can be relaxed and allow packaging binaries up to the
actual 32KB the mask boot ROM actually imposes.
This allows to have a bigger SPL, which is crucial for AArch64 builds.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 tools/mksunxiboot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 0f0b003..111d74a 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -48,8 +48,8 @@ int gen_check_sum(struct boot_file_head *head_p)
 #define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
 #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
 
-#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
-#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
+#define SUNXI_SRAM_SIZE 0x8000 /* SoC with smaller size are limited before */
+#define SRAM_LOAD_MAX_SIZE (SUNXI_SRAM_SIZE - sizeof(struct boot_file_head))
 
 /*
  * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned
-- 
2.8.2

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[U-Boot] [PATCH v4 03/20] SPL: FIT: improve error handling

[Andre Przywara]

At the moment we ignore any errors due to missing FIT properties,
instead go ahead and calculate our addresses with the -1 return value.
Fix this and bail out if any of the mandatory properties are missing.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 common/spl/spl_fit.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 85af980..ecd42d8 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,14 +11,17 @@
 #include 
 #include 
 
+#define FDT_ERROR ((ulong)(-1))
+
 static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
 {
const u32 *cell;
int len;
 
cell = fdt_getprop(fdt, node, prop, &len);
-   if (len != sizeof(*cell))
-   return -1U;
+   if (!cell || len != sizeof(*cell))
+   return FDT_ERROR;
+
return fdt32_to_cpu(*cell);
 }
 
@@ -222,7 +225,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
/* Get its information and set up the spl_image structure */
data_offset = fdt_getprop_u32(fit, node, "data-offset");
+   if (data_offset == FDT_ERROR)
+   return -ENOENT;
data_size = fdt_getprop_u32(fit, node, "data-size");
+   if (data_size == FDT_ERROR)
+   return -ENOENT;
load = fdt_getprop_u32(fit, node, "load");
debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
spl_image->load_addr = load;
@@ -265,6 +272,10 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
}
fdt_offset = fdt_getprop_u32(fit, node, "data-offset");
fdt_len = fdt_getprop_u32(fit, node, "data-size");
+   if (fdt_offset == FDT_ERROR || fdt_len == FDT_ERROR) {
+   debug("%s: cannot load FDT data\n" __func__);
+   return -ENOENT;
+   }
 
/*
 * Read the device tree and place it after the image. There may be
-- 
2.8.2

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[U-Boot] [PATCH v4 09/20] armv8: fsl: move ccn504 code into FSL Makefile

[Andre Przywara]

The generic ARMv8 assembly code contains routines for setting up
a CCN interconnect, though the Freescale SoCs are the only user.
Link this code only for Freescale targets, this saves some precious
bytes in the chronically tight SPL.

Signed-off-by: Andre Przywara 
---
 arch/arm/lib/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 4efa37b..82596e7 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,7 +43,7 @@ obj-y += stack.o
 ifdef CONFIG_CPU_V7M
 obj-y  += interrupts_m.o
 else ifdef CONFIG_ARM64
-obj-y  += ccn504.o
+obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o
 ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
 obj-y  += gic_64.o
 endif
-- 
2.8.2

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[U-Boot] [PATCH v4 12/20] sunxi: SPL: add FIT config selector for Pine64 boards

[Andre Przywara]

For a board or platform to support FIT loading in the SPL, it has to
provide a board_fit_config_name_match() routine, which helps to select
one of possibly multiple DTBs contained in a FIT image.
Provide a simple function which chooses the DT name U-Boot was
configured with.
If the DT name is one of the two Pine64 versions, determine the exact
model by checking the DRAM size.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Acked-by: Maxime Ripard 
---
 board/sunxi/board.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index c6fcb4c..5bb7b53 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -749,3 +749,26 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
return 0;
 }
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   const char *cmp_str;
+
+#ifdef CONFIG_DEFAULT_DEVICE_TREE
+   cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
+#else
+   return 0;
+#endif
+
+/* Differentiate the two Pine64 board DTs by their DRAM size. */
+   if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
+   if ((gd->ram_size > 512 * 1024 * 1024))
+   return !strstr(name, "plus");
+   else
+   return !!strstr(name, "plus");
+   } else {
+   return strcmp(name, cmp_str);
+   }
+}
+#endif
-- 
2.8.2

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[U-Boot] [PATCH v4 06/20] Kconfig: fix SPL_FIT dependency

[Andre Przywara]

SPL_FIT obviously requires libfdt in SPL, so let Kconfig express that by
selecting SPL_OF_LIBFDT.
Also make the actual options that users want (SPL signature and SPL FIT
loading) visible in the menu and let them select the SPL_FIT as a
requirement.
Also remove the now redundant SPL_OF_LIBFDT from those Kconfigs that had
it in for the SPL FIT loading feature.

Signed-off-by: Andre Przywara 
---
 Kconfig  | 4 +++-
 configs/am335x_evm_defconfig | 1 -
 configs/evb-rk3399_defconfig | 1 -
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Kconfig b/Kconfig
index 1cf990d..deacec4 100644
--- a/Kconfig
+++ b/Kconfig
@@ -208,15 +208,17 @@ config FIT_IMAGE_POST_PROCESS
 config SPL_FIT
bool "Support Flattened Image Tree within SPL"
depends on SPL
+   select SPL_OF_LIBFDT
 
 config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
-   depends on SPL_FIT
depends on SPL_DM
+   select SPL_FIT
select SPL_RSA
 
 config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT"
+   select SPL_FIT
help
  Normally with the SPL framework a legacy image is generated as part
  of the build. This contains U-Boot along with information as to
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index ab7b9aa..525d07e 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -57,4 +57,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_RSA=y
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index cef8506..34cfed3 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -4,7 +4,6 @@ CONFIG_ROCKCHIP_RK3399=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_ATF_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF_TEXT_BASE=0x0001
-- 
2.8.2

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[U-Boot] [PATCH v4 13/20] Makefile: add rules to generate SPL FIT images

[Andre Przywara]

Some platforms require more complex U-Boot images than we can easily
generate via the mkimage command line, for instance to load additional
image files.
Introduce a CONFIG_SPL_FIT_SOURCE and CONFIG_SPL_FIT_GENERATOR symbol,
which can either hold an .its source file describing the image layout,
or, in the second case, a generator tool (script) to create such
a source file. This script gets passed the list of device tree files
from the CONFIG_OF_LIST variable.
A platform or board can define either of those in their defconfig file
to allow an easy building of such an image.

Signed-off-by: Andre Przywara 
---
 Kconfig  | 17 +
 Makefile | 20 
 2 files changed, 37 insertions(+)

diff --git a/Kconfig b/Kconfig
index deacec4..335392f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -241,6 +241,23 @@ config SPL_FIT_IMAGE_POST_PROCESS
  injected into the FIT creation (i.e. the blobs would have been pre-
  processed before being added to the FIT image).
 
+config SPL_FIT_SOURCE
+   string ".its source file for U-Boot FIT image"
+   depends on SPL_FIT
+   help
+ Specifies a (platform specific) FIT source file to generate the
+ U-Boot FIT image. This could specify further image to load and/or
+ execute.
+
+config SPL_FIT_GENERATOR
+   string ".its file generator script for U-Boot FIT image"
+   depends on SPL_FIT
+   help
+ Specifies a (platform specific) script file to generate the FIT
+ source file used to build the U-Boot FIT image file. This gets
+ passed a list of supported device tree file stub names to
+ include in the generated image.
+
 endif # FIT
 
 config OF_BOARD_SETUP
diff --git a/Makefile b/Makefile
index 131d62e..61f18c9 100644
--- a/Makefile
+++ b/Makefile
@@ -831,6 +831,10 @@ quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
 
+quiet_cmd_mkfitimage = MKIMAGE $@
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f 
$(U_BOOT_ITS) -E $@ \
+   $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+
 quiet_cmd_cat = CAT $@
 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 
@@ -950,6 +954,19 @@ quiet_cmd_cpp_cfg = CFG $@
 cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
 
+# Boards with more complex image requirments can provide an .its source file
+# or a generator script
+ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
+U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+else
+ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
+U_BOOT_ITS := u-boot.its
+$(U_BOOT_ITS): FORCE
+   $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
+   $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
+endif
+endif
+
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
@@ -982,6 +999,9 @@ u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl 
u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
 
+u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+   $(call if_changed,mkfitimage)
+
 u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
 
-- 
2.8.2

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[U-Boot] [PATCH v4 20/20] sunxi: Move maintainership for Pine64

[Andre Przywara]

After speaking to Hans at FOSDEM, he is fine with transferring the
maintainership of the Pine64 boards over to me.

Signed-off-by: Andre Przywara 
---
 board/sunxi/MAINTAINERS | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index f39402b..fae8282 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -72,7 +72,6 @@ F:configs/q8_a33_tablet_1024x600_defconfig
 F: include/configs/sun9i.h
 F: configs/Merrii_A80_Optimus_defconfig
 F: include/configs/sun50i.h
-F: configs/pine64_plus_defconfig
 
 A20-OLIMEX-SOM-EVB BOARD
 M: Marcus Cooper 
@@ -263,6 +262,11 @@ M: Andre Przywara 
 S: Maintained
 F: configs/orangepi_pc2_defconfig
 
+PINE64 BOARDS
+M: Andre Przywara 
+S: Maintained
+F: configs/pine64_plus_defconfig
+
 R16 EVB PARROT BOARD
 M: Quentin Schulz 
 S: Maintained
-- 
2.8.2

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