The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.
With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.
Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
drivers/clk/rockchip/clk_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index ac658b9..4e807f1 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -747,6 +747,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru,
uint clk_id)
u32 div, con;
switch (clk_id) {
+ case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->clksel_con[16]);
break;
@@ -772,6 +773,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
int aclk_emmc = 198*MHz;
switch (clk_id) {
+ case HCLK_SDMMC:
case SCLK_SDMMC:
/* Select clk_sdmmc source from GPLL by default */
src_clk_div = GPLL_HZ / set_rate;
@@ -861,6 +863,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return 0;
+ case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
rate = rk3399_mmc_get_clk(priv->cru, clk->id);
@@ -898,6 +901,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong
rate)
switch (clk->id) {
case 0 ... 63:
return 0;
+ case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
--
1.9.1
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