The patch adds initial support for the Freescale mx53evk board.
SD/MMC boot is supported
Signed-off-by:Jason Liu <r64...@freescale.com>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
arch/arm/include/asm/arch-mx53/sys_proto.h | 30 ++
board/freescale/mx53evk/Makefile | 49 ++++
board/freescale/mx53evk/config.mk | 24 ++
board/freescale/mx53evk/flash_header.S | 120 ++++++++
board/freescale/mx53evk/mx53evk.c | 411 ++++++++++++++++++++++++++++
include/configs/mx53evk.h | 186 +++++++++++++
9 files changed, 828 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a13d28..d104821 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -152,6 +152,10 @@ Fred Fan <fanyef...@gmail.com>
mx51evk i.MX51
+Jason Liu <liu.h.ja...@gmail.com>
+
+ mx53evk i.MX53
+
Thomas Frieden <thom...@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
diff --git a/MAKEALL b/MAKEALL
index 2527352..7b9069a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -643,6 +643,7 @@ LIST_ARM11=" \
LIST_ARM_CORTEX_A8=" \
devkit8000 \
mx51evk \
+ mx53evk \
omap3_beagle \
omap3_overo \
omap3_evm \
diff --git a/Makefile b/Makefile
index c26e491..da312c4 100644
--- a/Makefile
+++ b/Makefile
@@ -3301,6 +3301,9 @@ mx31pdk_nand_config : unconfig
mx51evk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51
+mx53evk_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53evk freescale mx53
+
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
diff --git a/arch/arm/include/asm/arch-mx53/sys_proto.h
b/arch/arm/include/asm/arch-mx53/sys_proto.h
new file mode 100644
index 0000000..bf500a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx53/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_cpu_rev(void);
+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+
+#endif
diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile
new file mode 100644
index 0000000..3da299f
--- /dev/null
+++ b/board/freescale/mx53evk/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <l...@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := mx53evk.o
+SOBJS := flash_header.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53evk/config.mk
b/board/freescale/mx53evk/config.mk
new file mode 100644
index 0000000..e990c06
--- /dev/null
+++ b/board/freescale/mx53evk/config.mk
@@ -0,0 +1,24 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
+TEXT_BASE = 0x77800000
diff --git a/board/freescale/mx53evk/flash_header.S
b/board/freescale/mx53evk/flash_header.S
new file mode 100644
index 0000000..3d77627
--- /dev/null
+++ b/board/freescale/mx53evk/flash_header.S
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_FLASH_HEADER
+
+#define CPU_2_BE_32(l) \
+ ((((l) & 0x000000FF) << 24) | \
+ (((l) & 0x0000FF00) << 8) | \
+ (((l) & 0x00FF0000) >> 8) | \
+ (((l) & 0xFF000000) >> 24))
+
+#define MXC_DCD_ITEM(i, addr, val) \
+dcd_node_##i: \
+ .word CPU_2_BE_32(addr) ; \
+ .word CPU_2_BE_32(val) ; \
+
+.section ".text.flasheader", "x"
+ .org 0x400
+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v: .word _start
+reserv1: .word 0x0
+dcd_ptr: .word dcd_hdr
+boot_data_ptr: .word boot_data
+self_ptr: .word ivt_header
+app_code_csf: .word 0x0
+reserv2: .word 0x0
+
+boot_data: .word 0x77800000
+image_len: .word 256 * 1024
+plugin: .word 0x0
+
+dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */
+
+/* DCD */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00200000)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00200000)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x06000000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
+MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2b2f3031)
+MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333)
+MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x098, 0x00000f00)
+MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800)
+MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x07c, 0x01310132)
+MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x080, 0x0133014b)
+MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x018, 0x000016d0)
+MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x000, 0xc4110000)
+MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2)
+MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22)
+MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x014, 0x00c70092)
+MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x030, 0x009f000e)
+MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
+MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
+MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
+MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
+MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x00008031)
+MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0)
+MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
+MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
+MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
+MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030)
+MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031)
+MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x00468031)
+MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
+MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
+MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
+MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x00008039)
+MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138)
+MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
+MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
+MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
+MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038)
+MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039)
+MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
+MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
+MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
+
+#endif
diff --git a/board/freescale/mx53evk/mx53evk.c
b/board/freescale/mx53evk/mx53evk.c
new file mode 100644
index 0000000..0723cdf
--- /dev/null
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx53_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC3_BASE_ADDR, 1},
+};
+#endif
+
+u32 inline get_board_rev(void)
+{
+
+ return (system_rev >> 8) & 0xF;
+}
+
+inline void set_board_rev(int rev)
+{
+ system_rev |= (rev & 0xF) << 8;
+}
+
+u32 inline get_sys_rev(void)
+{
+
+ return system_rev;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ /* UART1 RXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4);
+ mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+ /* UART1 TXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4);
+}
+
+static void setup_iomux_fec(void)
+{
+ /*FEC_MDIO*/
+ mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC);
+ mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+ /*FEC_MDC*/
+ mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004);
+
+ /* FEC RXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180);
+
+ /* FEC RXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180);
+
+ /* FEC TXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004);
+
+ /* FEC TXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004);
+
+ /* FEC TX_EN */
+ mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004);
+
+ /* FEC TX_CLK */
+ mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180);
+
+ /* FEC RX_ER */
+ mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180);
+
+ /* FEC CRS */
+ mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180);
+}
+
+#ifdef CONFIG_MXC_SPI
+void spi_io_init(struct imx_spi_dev_t *dev)
+{
+ switch (dev->base) {
+ case CSPI1_BASE_ADDR:
+ /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */
+ mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3);
+
+ /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3);
+
+ if (dev->ss == 0) {
+ /* de-select SS1 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4);
+
+ /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3);
+ } else if (dev->ss == 1) {
+ /* de-select SS0 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4);
+
+ /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2);
+ }
+
+ /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
+
+ break;
+ case CSPI2_BASE_ADDR:
+ default:
+
+ break;
+ }
+}
+#endif
+
+#ifdef CONFIG_I2C_MXC
+static void setup_core_voltages(void)
+{
+ unsigned char buf[4] = { 0 };
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* Set core voltage VDDGP to 1.1V */
+ buf[0] = 0x45;
+ buf[1] = 0x4a;
+ buf[2] = 0x54;
+ if (i2c_write(0x8, 24, 1, buf, 3))
+ return;
+
+ /* Set DDR voltage VDDA to 1.225V */
+ buf[0] = 0;
+ buf[1] = 0x63;
+ buf[2] = 0x1a;
+ if (i2c_write(0x8, 26, 1, buf, 3))
+ return;
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ *cd = 0;
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ u32 index;
+ s32 status = 0;
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+ ++index) {
+ switch (index) {
+ case 0:
+ mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA0,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA1,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA2,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA3,
+ IOMUX_CONFIG_ALT0);
+
+ mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
+ break;
+ case 1:
+ mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+ IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_IORDY,
+ IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_DATA8,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA9,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA10,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA11,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA0,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA1,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA2,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA3,
+ IOMUX_CONFIG_ALT4);
+
+ mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
+
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return status;
+ break;
+ }
+ status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ }
+
+ return status;
+}
+#endif
+
+static enum boot_device get_boot_device(void)
+{
+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
+ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+ enum boot_device boot_dev;
+
+ switch (bt_mem_ctl) {
+ case 0x0:
+ if (bt_mem_type)
+ boot_dev = ONE_NAND_BOOT;
+ else
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case 0x2:
+ if (bt_mem_type)
+ boot_dev = SATA_BOOT;
+ else
+ boot_dev = PATA_BOOT;
+ break;
+ case 0x3:
+ if (bt_mem_type)
+ boot_dev = SPI_NOR_BOOT;
+ else
+ boot_dev = I2C_BOOT;
+ break;
+ case 0x4:
+ case 0x5:
+ boot_dev = SD_BOOT;
+ break;
+ case 0x6:
+ case 0x7:
+ boot_dev = MMC_BOOT;
+ break;
+ case 0x8 ... 0xf:
+ boot_dev = NAND_BOOT;
+ break;
+ default:
+ boot_dev = UNKNOWN_BOOT;
+ break;
+ }
+
+ return boot_dev;
+}
+
+int board_init(void)
+{
+ system_rev = get_cpu_rev();
+
+ gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+#ifdef CONFIG_I2C_MXC
+ setup_i2c(CONFIG_SYS_I2C_PORT);
+ setup_core_voltages();
+#endif
+
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX53EVK ");
+
+ puts("Boot Reason: [");
+
+ switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
+ case 0x0001:
+ puts("POR");
+ break;
+ case 0x0009:
+ puts("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ puts("WDOG");
+ break;
+ default:
+ puts("unknown");
+ }
+ puts("]\n");
+
+ puts("Boot Device: ");
+ switch (get_boot_device()) {
+ case WEIM_NOR_BOOT:
+ printf("NOR\n");
+ break;
+ case ONE_NAND_BOOT:
+ printf("ONE NAND\n");
+ break;
+ case PATA_BOOT:
+ printf("PATA\n");
+ break;
+ case SATA_BOOT:
+ printf("SATA\n");
+ break;
+ case I2C_BOOT:
+ printf("I2C\n");
+ break;
+ case SPI_NOR_BOOT:
+ printf("SPI NOR\n");
+ break;
+ case SD_BOOT:
+ printf("SD\n");
+ break;
+ case MMC_BOOT:
+ printf("MMC\n");
+ break;
+ case NAND_BOOT:
+ printf("NAND\n");
+ break;
+ case UNKNOWN_BOOT:
+ default:
+ printf("UNKNOWN\n");
+ break;
+ }
+
+ return 0;
+}
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
new file mode 100644
index 0000000..3a556b6
--- /dev/null
+++ b/include/configs/mx53evk.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_EVK
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX53_HCLK_FREQ 24000000
+#define CONFIG_MX53_CLK32 32768
+#define CONFIG_SYS_PLL2_FREQ 600
+#define CONFIG_SYS_AHB_PODF 4
+#define CONFIG_SYS_AXIA_PODF 1
+#define CONFIG_SYS_AXIB_PODF 2
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+#define CONFIG_FLASH_HEADER
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX53_UART1
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+
+/*
+ * MMC Configs
+ */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS
\
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif
--
1.7.0.4
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