The patch add header files to support the Freescale i.MX53
processor, setting definitions for internal registers.

Signed-off-by:Jason Liu <r64...@freescale.com>
---
 arch/arm/include/asm/arch-mx53/asm-offsets.h |   52 ++
 arch/arm/include/asm/arch-mx53/crm_regs.h    |  708 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx53/imx-regs.h    |  193 +++++++
 3 files changed, 953 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx53/asm-offsets.h 
b/arch/arm/include/asm/arch-mx53/asm-offsets.h
new file mode 100644
index 0000000..c44968a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx53/asm-offsets.h
@@ -0,0 +1,52 @@
+/*
+ * needed for arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S
+ *
+ * These should be auto-generated
+ */
+/* CCM */
+#define CLKCTL_CCR              0x00
+#define CLKCTL_CCDR             0x04
+#define CLKCTL_CSR              0x08
+#define CLKCTL_CCSR             0x0C
+#define CLKCTL_CACRR            0x10
+#define CLKCTL_CBCDR            0x14
+#define CLKCTL_CBCMR            0x18
+#define CLKCTL_CSCMR1           0x1C
+#define CLKCTL_CSCMR2           0x20
+#define CLKCTL_CSCDR1           0x24
+#define CLKCTL_CS1CDR           0x28
+#define CLKCTL_CS2CDR           0x2C
+#define CLKCTL_CDCDR            0x30
+#define CLKCTL_CHSCCDR          0x34
+#define CLKCTL_CSCDR2           0x38
+#define CLKCTL_CSCDR3           0x3C
+#define CLKCTL_CSCDR4           0x40
+#define CLKCTL_CWDR             0x44
+#define CLKCTL_CDHIPR           0x48
+#define CLKCTL_CDCR             0x4C
+#define CLKCTL_CTOR             0x50
+#define CLKCTL_CLPCR            0x54
+#define CLKCTL_CISR             0x58
+#define CLKCTL_CIMR             0x5C
+#define CLKCTL_CCOSR            0x60
+#define CLKCTL_CGPR             0x64
+#define CLKCTL_CCGR0            0x68
+#define CLKCTL_CCGR1            0x6C
+#define CLKCTL_CCGR2            0x70
+#define CLKCTL_CCGR3            0x74
+#define CLKCTL_CCGR4            0x78
+#define CLKCTL_CCGR5            0x7C
+#define CLKCTL_CCGR6            0x80
+#define CLKCTL_CCGR7            0x84
+#define CLKCTL_CMEOR            0x88
+
+/* DPLL */
+#define PLL_DP_CTL      0x00
+#define PLL_DP_CONFIG   0x04
+#define PLL_DP_OP       0x08
+#define PLL_DP_MFD      0x0C
+#define PLL_DP_MFN      0x10
+#define PLL_DP_HFS_OP   0x1C
+#define PLL_DP_HFS_MFD  0x20
+#define PLL_DP_HFS_MFN  0x24
+
diff --git a/arch/arm/include/asm/arch-mx53/crm_regs.h 
b/arch/arm/include/asm/arch-mx53/crm_regs.h
new file mode 100644
index 0000000..cd39055
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx53/crm_regs.h
@@ -0,0 +1,708 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX53_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX53_CRM_REGS_H__
+
+#define MXC_CCM_BASE   CCM_BASE_ADDR
+
+/* DPLL register mapping structure */
+struct mxc_pll_reg {
+       u32 ctrl;
+       u32 config;
+       u32 op;
+       u32 mfd;
+       u32 mfn;
+       u32 mfn_minus;
+       u32 mfn_plus;
+       u32 hfs_op;
+       u32 hfs_mfd;
+       u32 hfs_mfn;
+       u32 mfn_togc;
+       u32 destat;
+};
+/* Register maping of CCM*/
+struct mxc_ccm_reg {
+       u32 ccr;        /* 0x0000 */
+       u32 ccdr;
+       u32 csr;
+       u32 ccsr;
+       u32 cacrr;      /* 0x0010*/
+       u32 cbcdr;
+       u32 cbcmr;
+       u32 cscmr1;
+       u32 cscmr2;     /* 0x0020 */
+       u32 cscdr1;
+       u32 cs1cdr;
+       u32 cs2cdr;
+       u32 cdcdr;      /* 0x0030 */
+       u32 chscdr;
+       u32 cscdr2;
+       u32 cscdr3;
+       u32 cscdr4;     /* 0x0040 */
+       u32 cwdr;
+       u32 cdhipr;
+       u32 cdcr;
+       u32 ctor;       /* 0x0050 */
+       u32 clpcr;
+       u32 cisr;
+       u32 cimr;
+       u32 ccosr;      /* 0x0060 */
+       u32 cgpr;
+       u32 CCGR0;
+       u32 CCGR1;
+       u32 CCGR2;      /* 0x0070 */
+       u32 CCGR3;
+       u32 CCGR4;
+       u32 CCGR5;
+       u32 CCGR6;      /* 0x0080 */
+       u32 cmeor;
+};
+
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN            (0x1 << 12)
+#define MXC_CCM_CCR_CAMP2_EN           (0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN           (0x1 << 9)
+#define MXC_CCM_CCR_OSCNT_OFFSET               0
+#define MXC_CCM_CCR_OSCNT_MASK         (0xFF << 0)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_IPU_HS_MASK       (0x1 << 21)
+#define MXC_CCM_CCDR_EMI_HS_INT2_MASK  (0x1 << 20)
+#define MXC_CCM_CCDR_EMI_HS_INT1_MASK  (0x1 << 19)
+#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK  (0x1 << 18)
+#define MXC_CCM_CCDR_EMI_HS_FAST_MASK  (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK       (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSR_READY         (0x1 << 5)
+#define MXC_CCM_CSR_LVS_VALUE          (0x1 << 4)
+#define MXC_CCM_CSR_CAMP2_READY                (0x1 << 3)
+#define MXC_CCM_CSR_CAMP1_READY                (0x1 << 2)
+#define MXC_CCM_CSR_TEMP_MON_ALARM     (0x1 << 1)
+#define MXC_CCM_CSR_REF_EN_B           (0x1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_LP_APM_SEL_OFFSET         10
+#define MXC_CCM_CCSR_LP_APM_SEL                (0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL   (0x1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET           7
+#define MXC_CCM_CCSR_STEP_SEL_MASK     (0x3 << 7)
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET          5
+#define MXC_CCM_CCSR_PLL2_PODF_MASK    (0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET          3
+#define MXC_CCM_CCSR_PLL3_PODF_MASK    (0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL   (0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL   (0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL   (0x1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET          0
+#define MXC_CCM_CACRR_ARM_PODF_MASK    (0x7 << 0)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET                30
+#define MXC_CCM_CBCDR_DDR_HF_SEL               (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET                  27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK            (0x7 << 27)
+#define MXC_CCM_CBCDR_EMI_CLK_SEL      (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL   (0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET          22
+#define MXC_CCM_CBCDR_EMI_PODF_MASK    (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET                19
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK  (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET                16
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK  (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET          13
+#define MXC_CCM_CBCDR_NFC_PODF_MASK    (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET          10
+#define MXC_CCM_CBCDR_AHB_PODF_MASK    (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET          8
+#define MXC_CCM_CBCDR_IPG_PODF_MASK    (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET      6
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK        (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET      3
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK        (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET       0
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7 << 0)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET             16
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK       (0x3 << 16)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET           14
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK     (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET            12
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK      (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET               10
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK         (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET           8
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK     (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET           6
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK     (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET               4
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK         (0x3 << 4)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL    (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL_OFFSET     1
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL       (0x1 << 0)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL_OFFSET                0
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET         30
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK   (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET         28
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK   (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET          26
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL         (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET             24
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK       (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET           22
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK     (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET     20
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL          (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL          (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET     16
+#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             14
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK       (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK       (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL            (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL            (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET          8
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK    (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL         (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET             4
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK       (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET            2
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK      (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL    (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL    (0x1 << 0)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)    (26+n*3)
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)      (0x7 << (26+n*3))
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET                24
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK  (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET                22
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK  (0x3 << 22)
+#define MXC_CCM_CSCMR2_ASRC_CLK_SEL            (0x1 << 21)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK       (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET            16
+#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK      (0x7 << 16)
+#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET             14
+#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK       (0x3 << 14)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET             12
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK       (0x3 << 12)
+#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV         (0x1 << 11)
+#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV         (0x1 << 10)
+#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL         (0x1 << 9)
+#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL         (0x1 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              6
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                (0x3 << 6)
+#define MXC_CCM_CSCMR2_SPDIF1_COM              (1 << 5)
+#define MXC_CCM_CSCMR2_SPDIF0_COM              (1 << 4)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET           2
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK     (0x3 << 2)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET           0
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK     (0x3 << 0)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET            22
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK      (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET            19
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK      (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET            16
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK      (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET                     14
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK               (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET            11
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK      (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET                  8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET                  6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET                    3
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK              (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET                    0
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x7 << 0)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET                    25
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK              (0x3F << 25)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET                        22
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK          (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET                        16
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK          (0x3F << 16)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET                    9
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK              (0x7 << 9)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET                    6
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET                    0
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK              (0x3F << 0)
+
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET                        22
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK          (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET                        16
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK          (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET                    6
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET                    0
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK              (0x3F << 0)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET                      28
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                        (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET                   25
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET                   19
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x3F << 19)
+#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET                      16
+#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK                        (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET                   9
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET                      6
+#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK                        (0x7 << 6)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET                      3
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                        (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET                      0
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                        (0x7 << 0)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET                   6
+#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK             (0x3 << 6)
+#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET                   4
+#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK             (0x3 << 4)
+#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET              2
+#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK                (0x3 << 2)
+#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET              0
+#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK                (0x3 << 0)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET                    28
+#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK              (0x7 << 28)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET                    25
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK              (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET                    19
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK              (0x3F << 19)
+#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET                    9
+#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK              (0x3F << 9)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET                    6
+#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET                    0
+#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK              (0x3F << 0)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET                   16
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK             (0x7 << 16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET                   9
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET                    6
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET                    0
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK              (0x3F << 0)
+
+/* Define the bits in register CSCDR4 */
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET               16
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK         (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET               9
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK         (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET               6
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK         (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET               0
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK         (0x3F << 0)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (0x1 << 16)
+#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY             (0x1 << 8)
+#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                   (0x1 << 7)
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                        (0x1 << 6)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (0x1 << 5)
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY       (0x1 << 4)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                   (0x1 << 3)
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                   (0x1 << 2)
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                 (0x1 << 1)
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                 (0x1 << 0)
+
+/* Define the bits in register CDCR */
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER            (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET               0
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK         (0x3 << 0)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS               (0x1 << 27)
+#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS               (0x1 << 27)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS                        (0x1 << 26)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS                        (0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS               (0x1 << 24)
+#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS           (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS           (0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS           (0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS           (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS                        (0x1 << 19)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                        (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS               (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS               (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN                     (0x1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                                9
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK                  (0x3 << 9)
+#define MXC_CCM_CLPCR_VSTBY                            (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC                      (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS                            (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM               (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET                      3
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                        (0x3 << 3)
+#define MXC_CCM_CLPCR_LPM_OFFSET                       0
+#define MXC_CCM_CLPCR_LPM_MASK                         (0x3 << 0)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED                   (0x1 << 26)
+#define MXC_CCM_CISR_TEMP_MON_ALARM                    (0x1 << 25)
+#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED                        (0x1 << 23)
+#define MXC_CCM_CISR_PER_CLK_SEL_LOADED                        (0x1 << 22)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED       (0x1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED                   (0x1 << 20)
+#define MXC_CCM_CISR_EMI_PODF_LOADED                   (0x1 << 19)
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED                 (0x1 << 18)
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED                 (0x1 << 17)
+#define MXC_CCM_CISR_DIVIDER_LOADED                    (0x1 << 16)
+#define MXC_CCM_CISR_COSC_READY                                (0x1 << 6)
+#define MXC_CCM_CISR_CKIH2_READY                       (0x1 << 5)
+#define MXC_CCM_CISR_CKIH_READY                                (0x1 << 4)
+#define MXC_CCM_CISR_FPM_READY                         (0x1 << 3)
+#define MXC_CCM_CISR_LRF_PLL3                          (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2                          (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1                          (0x1 << 0)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (0x1 << 26)
+#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM               (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED           (0x1 << 23)
+#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED           (0x1 << 22)
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED  (0x1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED              (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED         (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED            (0x1 << 18)
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED            (0x1 << 17)
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED               (0x1 << 16)
+#define MXC_CCM_CIMR_MASK_COSC_READY                   (0x1 << 6)
+#define MXC_CCM_CIMR_MASK_CAMP2_READY                  (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CAMP1_READY                  (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_LRF_PLL4                     (0x1 << 3)
+#define MXC_CCM_CIMR_MASK_LRF_PLL3                     (0x1 << 2)
+#define MXC_CCM_CIMR_MASK_LRF_PLL2                     (0x1 << 1)
+#define MXC_CCM_CIMR_MASK_LRF_PLL1                     (0x1 << 0)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                   (0x1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                          21
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK                    (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                          16
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK                    (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN                          (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                          4
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK                    (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                          0
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK                    (0xF << 0)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL                 (0x1 << 24)
+#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN                  (0x1 << 23)
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (0x1 << 4)
+#define MXC_CCM_CGPR_FPM_SEL                           (0x1 << 3)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET                   0
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK             (0x7 << 0)
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK                   (0x3 << 0)
+#define MXC_CCM_CCGR0_CG15_OFFSET                      30
+#define MXC_CCM_CCGR0_CG15_MASK                        (0x3 << 30)
+#define MXC_CCM_CCGR0_CG14_OFFSET                      28
+#define MXC_CCM_CCGR0_CG14_MASK                        (0x3 << 28)
+#define MXC_CCM_CCGR0_CG13_OFFSET                      26
+#define MXC_CCM_CCGR0_CG13_MASK                        (0x3 << 26)
+#define MXC_CCM_CCGR0_CG12_OFFSET                      24
+#define MXC_CCM_CCGR0_CG12_MASK                        (0x3 << 24)
+#define MXC_CCM_CCGR0_CG11_OFFSET                      22
+#define MXC_CCM_CCGR0_CG11_MASK                        (0x3 << 22)
+#define MXC_CCM_CCGR0_CG10_OFFSET                      20
+#define MXC_CCM_CCGR0_CG10_MASK                        (0x3 << 20)
+#define MXC_CCM_CCGR0_CG9_OFFSET                       18
+#define MXC_CCM_CCGR0_CG9_MASK                 (0x3 << 18)
+#define MXC_CCM_CCGR0_CG8_OFFSET                       16
+#define MXC_CCM_CCGR0_CG8_MASK                 (0x3 << 16)
+#define MXC_CCM_CCGR0_CG7_OFFSET                       14
+#define MXC_CCM_CCGR0_CG6_OFFSET                       12
+#define MXC_CCM_CCGR0_CG5_OFFSET                       10
+#define MXC_CCM_CCGR0_CG5_MASK                 (0x3 << 10)
+#define MXC_CCM_CCGR0_CG4_OFFSET                       8
+#define MXC_CCM_CCGR0_CG4_MASK                 (0x3 << 8)
+#define MXC_CCM_CCGR0_CG3_OFFSET                       6
+#define MXC_CCM_CCGR0_CG3_MASK                 (0x3 << 6)
+#define MXC_CCM_CCGR0_CG2_OFFSET                       4
+#define MXC_CCM_CCGR0_CG2_MASK                 (0x3 << 4)
+#define MXC_CCM_CCGR0_CG1_OFFSET                       2
+#define MXC_CCM_CCGR0_CG1_MASK                 (0x3 << 2)
+#define MXC_CCM_CCGR0_CG0_OFFSET                       0
+#define MXC_CCM_CCGR0_CG0_MASK                 (0x3 << 0)
+
+#define MXC_CCM_CCGR1_CG15_OFFSET              30
+#define MXC_CCM_CCGR1_CG14_OFFSET              28
+#define MXC_CCM_CCGR1_CG13_OFFSET              26
+#define MXC_CCM_CCGR1_CG12_OFFSET              24
+#define MXC_CCM_CCGR1_CG11_OFFSET              22
+#define MXC_CCM_CCGR1_CG10_OFFSET              20
+#define MXC_CCM_CCGR1_CG9_OFFSET               18
+#define MXC_CCM_CCGR1_CG8_OFFSET               16
+#define MXC_CCM_CCGR1_CG7_OFFSET               14
+#define MXC_CCM_CCGR1_CG6_OFFSET               12
+#define MXC_CCM_CCGR1_CG5_OFFSET               10
+#define MXC_CCM_CCGR1_CG4_OFFSET               8
+#define MXC_CCM_CCGR1_CG3_OFFSET               6
+#define MXC_CCM_CCGR1_CG2_OFFSET               4
+#define MXC_CCM_CCGR1_CG1_OFFSET               2
+#define MXC_CCM_CCGR1_CG0_OFFSET               0
+
+#define MXC_CCM_CCGR2_CG15_OFFSET              30
+#define MXC_CCM_CCGR2_CG14_OFFSET              28
+#define MXC_CCM_CCGR2_CG13_OFFSET              26
+#define MXC_CCM_CCGR2_CG12_OFFSET              24
+#define MXC_CCM_CCGR2_CG11_OFFSET              22
+#define MXC_CCM_CCGR2_CG10_OFFSET              20
+#define MXC_CCM_CCGR2_CG9_OFFSET               18
+#define MXC_CCM_CCGR2_CG8_OFFSET               16
+#define MXC_CCM_CCGR2_CG7_OFFSET               14
+#define MXC_CCM_CCGR2_CG6_OFFSET               12
+#define MXC_CCM_CCGR2_CG5_OFFSET               10
+#define MXC_CCM_CCGR2_CG4_OFFSET               8
+#define MXC_CCM_CCGR2_CG3_OFFSET               6
+#define MXC_CCM_CCGR2_CG2_OFFSET               4
+#define MXC_CCM_CCGR2_CG1_OFFSET               2
+#define MXC_CCM_CCGR2_CG0_OFFSET               0
+
+#define MXC_CCM_CCGR3_CG15_OFFSET              30
+#define MXC_CCM_CCGR3_CG14_OFFSET              28
+#define MXC_CCM_CCGR3_CG13_OFFSET              26
+#define MXC_CCM_CCGR3_CG12_OFFSET              24
+#define MXC_CCM_CCGR3_CG11_OFFSET              22
+#define MXC_CCM_CCGR3_CG10_OFFSET              20
+#define MXC_CCM_CCGR3_CG9_OFFSET               18
+#define MXC_CCM_CCGR3_CG8_OFFSET               16
+#define MXC_CCM_CCGR3_CG7_OFFSET               14
+#define MXC_CCM_CCGR3_CG6_OFFSET               12
+#define MXC_CCM_CCGR3_CG5_OFFSET               10
+#define MXC_CCM_CCGR3_CG4_OFFSET               8
+#define MXC_CCM_CCGR3_CG3_OFFSET               6
+#define MXC_CCM_CCGR3_CG2_OFFSET               4
+#define MXC_CCM_CCGR3_CG1_OFFSET               2
+#define MXC_CCM_CCGR3_CG0_OFFSET               0
+
+#define MXC_CCM_CCGR4_CG15_OFFSET              30
+#define MXC_CCM_CCGR4_CG14_OFFSET              28
+#define MXC_CCM_CCGR4_CG13_OFFSET              26
+#define MXC_CCM_CCGR4_CG12_OFFSET              24
+#define MXC_CCM_CCGR4_CG11_OFFSET              22
+#define MXC_CCM_CCGR4_CG10_OFFSET              20
+#define MXC_CCM_CCGR4_CG9_OFFSET               18
+#define MXC_CCM_CCGR4_CG8_OFFSET               16
+#define MXC_CCM_CCGR4_CG7_OFFSET               14
+#define MXC_CCM_CCGR4_CG6_OFFSET               12
+#define MXC_CCM_CCGR4_CG5_OFFSET               10
+#define MXC_CCM_CCGR4_CG4_OFFSET               8
+#define MXC_CCM_CCGR4_CG3_OFFSET               6
+#define MXC_CCM_CCGR4_CG2_OFFSET               4
+#define MXC_CCM_CCGR4_CG1_OFFSET               2
+#define MXC_CCM_CCGR4_CG0_OFFSET               0
+
+#define MXC_CCM_CCGR5_CG15_OFFSET              30
+#define MXC_CCM_CCGR5_CG14_OFFSET              28
+#define MXC_CCM_CCGR5_CG14_MASK                (0x3 << 28)
+#define MXC_CCM_CCGR5_CG13_OFFSET              26
+#define MXC_CCM_CCGR5_CG13_MASK                (0x3 << 26)
+#define MXC_CCM_CCGR5_CG12_OFFSET              24
+#define MXC_CCM_CCGR5_CG12_MASK                (0x3 << 24)
+#define MXC_CCM_CCGR5_CG11_OFFSET              22
+#define MXC_CCM_CCGR5_CG11_MASK                (0x3 << 22)
+#define MXC_CCM_CCGR5_CG10_OFFSET              20
+#define MXC_CCM_CCGR5_CG10_MASK                (0x3 << 20)
+#define MXC_CCM_CCGR5_CG9_OFFSET               18
+#define MXC_CCM_CCGR5_CG9_MASK         (0x3 << 18)
+#define MXC_CCM_CCGR5_CG8_OFFSET               16
+#define MXC_CCM_CCGR5_CG8_MASK         (0x3 << 16)
+#define MXC_CCM_CCGR5_CG7_OFFSET               14
+#define MXC_CCM_CCGR5_CG7_MASK         (0x3 << 14)
+#define MXC_CCM_CCGR5_CG6_OFFSET               12
+#define MXC_CCM_CCGR5_CG6_MASK         (0x3 << 12)
+#define MXC_CCM_CCGR5_CG5_OFFSET               10
+#define MXC_CCM_CCGR5_CG4_OFFSET               8
+#define MXC_CCM_CCGR5_CG3_OFFSET               6
+#define MXC_CCM_CCGR5_CG2_OFFSET               4
+#define MXC_CCM_CCGR5_CG2_MASK         (0x3 << 4)
+#define MXC_CCM_CCGR5_CG1_OFFSET               2
+#define MXC_CCM_CCGR5_CG0_OFFSET               0
+
+#define MXC_CCM_CCGR6_CG15_OFFSET              30
+#define MXC_CCM_CCGR6_CG14_OFFSET              28
+#define MXC_CCM_CCGR6_CG14_MASK                (0x3 << 28)
+#define MXC_CCM_CCGR6_CG13_OFFSET              26
+#define MXC_CCM_CCGR6_CG13_MASK                (0x3 << 26)
+#define MXC_CCM_CCGR6_CG12_OFFSET              24
+#define MXC_CCM_CCGR6_CG12_MASK                (0x3 << 24)
+#define MXC_CCM_CCGR6_CG11_OFFSET              22
+#define MXC_CCM_CCGR6_CG11_MASK                (0x3 << 22)
+#define MXC_CCM_CCGR6_CG10_OFFSET              20
+#define MXC_CCM_CCGR6_CG10_MASK                (0x3 << 20)
+#define MXC_CCM_CCGR6_CG9_OFFSET               18
+#define MXC_CCM_CCGR6_CG9_MASK         (0x3 << 18)
+#define MXC_CCM_CCGR6_CG8_OFFSET               16
+#define MXC_CCM_CCGR6_CG8_MASK         (0x3 << 16)
+#define MXC_CCM_CCGR6_CG7_OFFSET               14
+#define MXC_CCM_CCGR6_CG7_MASK         (0x3 << 14)
+#define MXC_CCM_CCGR6_CG6_OFFSET               12
+#define MXC_CCM_CCGR6_CG6_MASK         (0x3 << 12)
+#define MXC_CCM_CCGR6_CG5_OFFSET               10
+#define MXC_CCM_CCGR6_CG4_OFFSET               8
+#define MXC_CCM_CCGR6_CG3_OFFSET               6
+#define MXC_CCM_CCGR6_CG2_OFFSET               4
+#define MXC_CCM_CCGR6_CG2_MASK         (0x3 << 4)
+#define MXC_CCM_CCGR6_CG1_OFFSET               2
+#define MXC_CCM_CCGR6_CG0_OFFSET               0
+
+#define MXC_CCM_CCGR7_CG15_OFFSET              30
+#define MXC_CCM_CCGR7_CG14_OFFSET              28
+#define MXC_CCM_CCGR7_CG14_MASK                (0x3 << 28)
+#define MXC_CCM_CCGR7_CG13_OFFSET              26
+#define MXC_CCM_CCGR7_CG13_MASK                (0x3 << 26)
+#define MXC_CCM_CCGR7_CG12_OFFSET              24
+#define MXC_CCM_CCGR7_CG12_MASK                (0x3 << 24)
+#define MXC_CCM_CCGR7_CG11_OFFSET              22
+#define MXC_CCM_CCGR7_CG11_MASK                (0x3 << 22)
+#define MXC_CCM_CCGR7_CG10_OFFSET              20
+#define MXC_CCM_CCGR7_CG10_MASK                (0x3 << 20)
+#define MXC_CCM_CCGR7_CG9_OFFSET               18
+#define MXC_CCM_CCGR7_CG9_MASK         (0x3 << 18)
+#define MXC_CCM_CCGR7_CG8_OFFSET               16
+#define MXC_CCM_CCGR7_CG8_MASK         (0x3 << 16)
+#define MXC_CCM_CCGR7_CG7_OFFSET               14
+#define MXC_CCM_CCGR7_CG7_MASK         (0x3 << 14)
+#define MXC_CCM_CCGR7_CG6_OFFSET               12
+#define MXC_CCM_CCGR7_CG6_MASK         (0x3 << 12)
+#define MXC_CCM_CCGR7_CG5_OFFSET               10
+#define MXC_CCM_CCGR7_CG4_OFFSET               8
+#define MXC_CCM_CCGR7_CG3_OFFSET               6
+#define MXC_CCM_CCGR7_CG2_OFFSET               4
+#define MXC_CCM_CCGR7_CG2_MASK         (0x3 << 4)
+#define MXC_CCM_CCGR7_CG1_OFFSET               2
+#define MXC_CCM_CCGR7_CG0_OFFSET               0
+
+#define MXC_GPC_BASE           (IO_ADDRESS(GPC_BASE_ADDR))
+#define MXC_DPTC_LP_BASE       (MXC_GPC_BASE + 0x80)
+#define MXC_DPTC_GP_BASE       (MXC_GPC_BASE + 0x100)
+#define MXC_DVFS_CORE_BASE     (MXC_GPC_BASE + 0x180)
+#define MXC_DVFS_PER_BASE      (MXC_GPC_BASE + 0x1C4)
+#define MXC_PGC_IPU_BASE       (MXC_GPC_BASE + 0x220)
+#define MXC_PGC_VPU_BASE       (MXC_GPC_BASE + 0x240)
+#define MXC_PGC_GPU_BASE       (MXC_GPC_BASE + 0x260)
+#define MXC_SRPG_NEON_BASE     (MXC_GPC_BASE + 0x280)
+#define MXC_SRPG_ARM_BASE      (MXC_GPC_BASE + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE   (MXC_GPC_BASE + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE   (MXC_GPC_BASE + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE  (MXC_GPC_BASE + 0x2E0)
+#define MXC_SRPG_EMI_BASE      (MXC_GPC_BASE + 0x300)
+
+/* DVFS CORE */
+#define MXC_DVFSTHRS           (MXC_DVFS_CORE_BASE + 0x00)
+#define MXC_DVFSCOUN           (MXC_DVFS_CORE_BASE + 0x04)
+#define MXC_DVFSSIG1           (MXC_DVFS_CORE_BASE + 0x08)
+#define MXC_DVFSSIG0           (MXC_DVFS_CORE_BASE + 0x0C)
+#define MXC_DVFSGPC0           (MXC_DVFS_CORE_BASE + 0x10)
+#define MXC_DVFSGPC1           (MXC_DVFS_CORE_BASE + 0x14)
+#define MXC_DVFSGPBT           (MXC_DVFS_CORE_BASE + 0x18)
+#define MXC_DVFSEMAC           (MXC_DVFS_CORE_BASE + 0x1C)
+#define MXC_DVFSCNTR           (MXC_DVFS_CORE_BASE + 0x20)
+#define MXC_DVFSLTR0_0         (MXC_DVFS_CORE_BASE + 0x24)
+#define MXC_DVFSLTR0_1         (MXC_DVFS_CORE_BASE + 0x28)
+#define MXC_DVFSLTR1_0         (MXC_DVFS_CORE_BASE + 0x2C)
+#define MXC_DVFSLTR1_1         (MXC_DVFS_CORE_BASE + 0x30)
+#define MXC_DVFSPT0            (MXC_DVFS_CORE_BASE + 0x34)
+#define MXC_DVFSPT1            (MXC_DVFS_CORE_BASE + 0x38)
+#define MXC_DVFSPT2            (MXC_DVFS_CORE_BASE + 0x3C)
+#define MXC_DVFSPT3            (MXC_DVFS_CORE_BASE + 0x40)
+
+/* DVFS PER */
+#define MXC_DVFSPER_LTR0       (MXC_DVFS_PER_BASE)
+#define MXC_DVFSPER_LTR1       (MXC_DVFS_PER_BASE + 0x04)
+#define MXC_DVFSPER_LTR2       (MXC_DVFS_PER_BASE + 0x08)
+#define MXC_DVFSPER_LTR3       (MXC_DVFS_PER_BASE + 0x0C)
+#define MXC_DVFSPER_LTBR0      (MXC_DVFS_PER_BASE + 0x10)
+#define MXC_DVFSPER_LTBR1      (MXC_DVFS_PER_BASE + 0x14)
+#define MXC_DVFSPER_PMCR0      (MXC_DVFS_PER_BASE + 0x18)
+#define MXC_DVFSPER_PMCR1      (MXC_DVFS_PER_BASE + 0x1C)
+
+/* GPC */
+#define MXC_GPC_CNTR           (MXC_GPC_BASE + 0x0)
+#define MXC_GPC_PGR            (MXC_GPC_BASE + 0x4)
+#define MXC_GPC_VCR            (MXC_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU         (MXC_GPC_BASE + 0xC)
+#define MXC_GPC_NEON           (MXC_GPC_BASE + 0x10)
+
+/* PGC */
+#define MXC_PGC_IPU_PGCR       (MXC_PGC_IPU_BASE + 0x0)
+#define MXC_PGC_IPU_PGSR       (MXC_PGC_IPU_BASE + 0xC)
+#define MXC_PGC_VPU_PGCR       (MXC_PGC_VPU_BASE + 0x0)
+#define MXC_PGC_VPU_PGSR       (MXC_PGC_VPU_BASE + 0xC)
+#define MXC_PGC_GPU_PGCR       (MXC_PGC_GPU_BASE + 0x0)
+#define MXC_PGC_GPU_PGSR       (MXC_PGC_GPU_BASE + 0xC)
+
+#define MXC_PGCR_PCR           1
+#define MXC_SRPGCR_PCR         1
+#define MXC_EMPGCR_PCR         1
+#define MXC_PGSR_PSR           1
+
+
+#define MXC_CORTEXA8_PLAT_LPC_DSM      (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM  (1 << 1)
+
+/* SRPG */
+#define MXC_SRPG_NEON_SRPGCR   (MXC_SRPG_NEON_BASE + 0x0)
+#define MXC_SRPG_NEON_PUPSCR   (MXC_SRPG_NEON_BASE + 0x4)
+#define MXC_SRPG_NEON_PDNSCR   (MXC_SRPG_NEON_BASE + 0x8)
+
+#define MXC_SRPG_ARM_SRPGCR    (MXC_SRPG_ARM_BASE + 0x0)
+#define MXC_SRPG_ARM_PUPSCR    (MXC_SRPG_ARM_BASE + 0x4)
+#define MXC_SRPG_ARM_PDNSCR    (MXC_SRPG_ARM_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
+
+#define MXC_SRPG_MEGAMIX_SRPGCR        (MXC_SRPG_MEGAMIX_BASE + 0x0)
+#define MXC_SRPG_MEGAMIX_PUPSCR        (MXC_SRPG_MEGAMIX_BASE + 0x4)
+#define MXC_SRPG_MEGAMIX_PDNSCR        (MXC_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MXC_SRPGC_EMI_SRPGCR   (MXC_SRPGC_EMI_BASE + 0x0)
+#define MXC_SRPGC_EMI_PUPSCR   (MXC_SRPGC_EMI_BASE + 0x4)
+#define MXC_SRPGC_EMI_PDNSCR   (MXC_SRPGC_EMI_BASE + 0x8)
+
+#endif                         /* __ARCH_ARM_MACH_MX53_CRM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx53/imx-regs.h 
b/arch/arm/include/asm/arch-mx53/imx-regs.h
new file mode 100644
index 0000000..104fae4
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx53/imx-regs.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX53_H__
+#define __ASM_ARCH_MXC_MX53_H__
+
+#define __REG(x)        (*((volatile u32 *)(x)))
+#define __REG16(x)      (*((volatile u16 *)(x)))
+#define __REG8(x)       (*((volatile u8 *)(x)))
+
+#define IRAM_BASE_ADDR         0xF8000000      /* internal ram */
+#define NFC_BASE_ADDR_AXI      0xF7FF0000      /* NAND flash AXI */
+#define TZIC_BASE_ADDR         0x0FFFC000
+
+#define DEBUG_BASE_ADDR                0x40000000
+
+#define ETB_BASE_ADDR          (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR          (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR         (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR         (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR         (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR         (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR         (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR   (DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR        0x50000000
+
+#define MMC_SDHC1_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR        (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR        (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00014000)
+#define ESAI_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00018000)
+#define MMC_SDHC3_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR                (SPBA0_BASE_ADDR + 0x00028000)
+#define ASRC_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0002C000)
+#define ATA_DMA_BASE_ADDR      (SPBA0_BASE_ADDR + 0x00030000)
+#define SPBA_CTRL_BASE_ADDR    (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR        0x53F00000
+
+#define OTG_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR                (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR                (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000C0000)
+#define CAN1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000C8000)
+#define CAN2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000CC000)
+#define SRC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D8000)
+#define GPIO5_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E4000)
+#define ATA_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000E8000)
+#define I2C3_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000EC000)
+#define UART4_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000F0000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR                0x63F00000
+
+#define PLL1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00088000)
+#define PLL4_BASE_ADDR         (AIPS2_BASE_ADDR + 0x0008C000)
+#define UART5_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00090000)
+#define AHBMAX_BASE_ADDR       (AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000D0000)
+#define RTC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define M4IF_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DBF00)
+#define MLB_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000F8000)
+#define PTP_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000FC000)
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR         0x70000000
+#define CSD1_BASE_ADDR         0xB0000000
+
+/* Assuming 24MHz input clock with doubler ON */
+/*                            MFI         PDF */
+#define DP_OP_850       ((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_850      (48 - 1)
+#define DP_MFN_850      41
+
+#define DP_OP_800       ((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_800      (3 - 1)
+#define DP_MFN_800      1
+
+#define DP_OP_700       ((7 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_700      (24 - 1)
+#define DP_MFN_700      7
+
+#define DP_OP_600       ((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_600      (4 - 1)
+#define DP_MFN_600      1
+
+#define DP_OP_665       ((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_665      (96 - 1)
+#define DP_MFN_665      89
+
+#define DP_OP_532       ((5 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_532      (24 - 1)
+#define DP_MFN_532      13
+
+#define DP_OP_400       ((8 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_400      (3 - 1)
+#define DP_MFN_400      1
+
+#define DP_OP_216       ((6 << 4) + ((3 - 1)  << 0))
+#define DP_MFD_216      (4 - 1)
+#define DP_MFN_216      3
+
+#define CHIP_REV_1_0            0x10
+#define PLATFORM_ICGC           0x14
+
+#ifndef __ASSEMBLER__
+
+enum boot_device {
+       WEIM_NOR_BOOT,
+       ONE_NAND_BOOT,
+       PATA_BOOT,
+       SATA_BOOT,
+       I2C_BOOT,
+       SPI_NOR_BOOT,
+       SD_BOOT,
+       MMC_BOOT,
+       NAND_BOOT,
+       UNKNOWN_BOOT
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif                         /*  __ASM_ARCH_MXC_MX53_H__ */
-- 
1.7.0.4

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