ond call is silently coercing the ref clock
to be gpsdo, without any indication even a debug print statement (in the MPM
periph_manager code).
Thanks & Cheers,
--
David Raeman
Synoptic Engineering
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If you could start out with both 10MHz and PPS using GPS signal, set all clocks
to the same time (e.g., zero) at the common PPS, and then switch to using
external ref, it might be possible. My understanding is that the only thing
the PPS is needed for is setting the common time. In other words,
Seeing the same behavior using UHD 4.1.0.1 on my N320 and E320, using internal
clock and time sources:
$ ./lib/uhd/examples/test_timed_commands --args addr=192.168.10.2
Creating the usrp device with: addr=192.168.10.2...
[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100;
UHD_4.1.0.HEAD-0-
.. Now that I look closely at test_timed_commands, I'm more confused. My
understand of set_command_time is that it sets an FPGA register of the future
time at which to process subsequent commands, but none of the calls will block.
If the application wants to wait for the timed command to occur,
places (e.g.
DEFAULT_FRAME_SIZE in dpdk_common.cpp). In the meantime, my temporary solution
is to locally revert commit a629ce3a46 until it can be confirmed with DPDK with
10GbE.
Cheers,
--
David Raeman
Synoptic Engineering
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Generally speaking you cannot do better than about 25 Msps over a 1GbE link. By
default the samples are signed 16-bit I/Q pairs, which means 32 bits per
sample. At 25 Msps, that means the total data throughput is 800 Mbps – which is
starting to approach the bandwidth over the 1 Gbps link.
If yo
onfirm?
Thanks!
--
David Raeman
Synoptic Engineering
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Thanks all – I think that all makes sense. So the input clock is AC coupled,
which strips the DC component, then the level is clamped by the diodes. Thus
the TI chip always gets a clipped sinewave regardless of what the input signal
looked like..
___
uild the kernel bits, not the
full filesystem. I'd appreciate any thoughts on whether this type of
customization is generally done, and any pointers on the quickest/easiest
approach. :)
Thanks,
David
--
David Raeman
Synoptic Engineering
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USRP-u
t I'd appreciate feedback on
any known-good solutions here.
Thanks!
--
David Raeman
Synoptic Engineering
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Thanks Wade – I can confirm these worked.
Best,
David
From: Wade Fife
Sent: Thursday, April 21, 2022 3:29 PM
To: David Raeman
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Substitute power plug part for USRP E320?
Hi David,
I think the Kycon KPPX-4P is compatible, but I've
Hi all,
Is it possible to programmatically determine the "rfnoc_chdr_clk" rate from a
UHD application? More specifically, I have a custom RFNoC block clocked from
rfnoc_chdr_clk, and I'd like to programmatically determine its clock rate from
the associated custom software driver so I can conver
on't see it exposed anywhere in the API. So, as it is now, it might be easier
to just do a lookup based on the type of USRP. I don't know if there's an easy
way to get to that register.
Wade
On Wed, Apr 27, 2022 at 9:57 AM Marcus D. Leech
mailto:patchvonbr...@gmail.com>> wro
e the B2xx models also use the AD9361 and already
support this, my inclination is to copy similar logic for E3xx. Just wanted to
make sure I'm not missing any hiccups that might explain why support was
excluded for these radios.
Thanks,
David
--
David Raeman
Synop
There is a motherboard sensor that you can query to check the ‘ref_locked’
status.
However, I had noted its behavior during clock loss is inconsistent across
models. In UHD 4.1 (and I’m working from memory here), some models (e.g. E320)
check a digital lock-detect signal and always report the c
The error string is also suspicious.. *IDN? is a command used to identify lab
instruments that implement SCPI protocols, and I’m not familiar with any GPS
receiver that interfaces using SCPI. Is it possible you have some kind of
instrument-control service on your computer (LabView, Keysight IO,
.. Sorry, just realized the GPSDO apparently does use SCPI-99 commands. :)
From: David Raeman
Sent: Wednesday, June 1, 2022 12:51 PM
To: Marcus D. Leech ; usrp-users@lists.ettus.com
Subject: RE: [USRP-users] Re: GPS invalid reply
The error string is also suspicious.. *IDN? is a command used to
Hi Jon, you might try deallocating the original smart pointer before creating a
new one, i.e. call m_dev.reset() before remaking the device. If you're not
familiar with it, note the use of dot instead of arrow operator, since this
operation is on the smart pointer itself and not the object it's
Hi Jon, I did some poking around in the code, and I don't believe the E320
supports that feature. On B2xx radios, if you don't specify an explicit master
clock rate it has logic to determine an ideal rate based on the sampling rate,
and it exposes an auto_tick_rate property to toggle that behavi
> > I don't know the limitation of the N310 embedded ARM to have an
> > opinion in embedded mode.
>
> Not a chance that it could support anything more than about 10Msps at the
> outside.
The E320 docs also mention 10Msps max to the embedded ARM processor, and I
found that to be strange. What's th
F4002 PLL. The internal clock
runs at 20MHz, but I was able to try an external clock at that rate (required a
2-line patch to UHD) and it didn't make a difference. The only other USRP I
have on hand is an N320, and this issue does not seem to happen on that radio
model when I use the same
he
> > periodic phase issues on both the external clock cases, but not the
> > internal clock case.
> >
> > Is this a known issue? Any speculation on what might cause this effect
> > when using an external clock? I can't fi
> In case you try turning off GPSDO on E320 please share info if it helps.
Hi Piotr,
I was able to disable the power rail for the GPSDO and confirmed it resolves
this issue. So the problem is correlated with GPSDO activity in some way, even
though its TCXO net is de-selected at the clock se
Hi Jim,
I ran into what sounds like the same issue using N320s operating at nearly the
same center frequency. I was able to isolate a fix (some tweaks in the LMX2592
configuration), and my PR was folded into UHD 4.2. I believe another, unrelated
fix for N320 tuning was also committed in UHD 4.2
erested in following any further
research/improvements that reduce phase noise on either radio architecture.
Best,
David
From: Jim Palladino
Sent: Wednesday, November 2, 2022 1:33 PM
To: David Raeman ; Marcus D. Leech
; USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Re: N320 LO stability proble
in/procedure to rebuild the libraries on the radio?
Thanks,
--
David Raeman
Synoptic Engineering
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.. Nevermind on the final point, and kudos to Ettus for providing a very easy
approach for rebuilding the on-radio MPM libraries here:
https://files.ettus.com/manual/page_usrp_e3xx.html#e3xx_software_dev_mpm_native
From: David Raeman
Sent: Wednesday, January 11, 2023 1:45 PM
To: usrp-users
d I'm now seeing the stable phase relationship across receive windows
for separate radios with common clock.
Cheers,
-David
From: Marcus D. Leech
Sent: Wednesday, January 11, 2023 5:33 PM
On 11/01/2023 13:45, David Raeman wrote:
I’m working on a project that involves phase-coherent recept
Hi Yasir,
I also have some E320 units which are rev 7 and were delivered about a month
ago – they do not have newest firmware flashed into the MCU’s RO image, which I
believe is what matters for auto-boot. You can confirm the version by using the
USB connection to the microcontroller’s command-
I've also struggled against stubborn TX underrun issues and have had some
success using dedicated CPU cores to make large improvements. My configuration
is quite different than yours, but perhaps this'll be a helpful lead.
I have a custom multithreaded application that manages four E320 radios f
Note that because you are running these commands via sudo, the results may be
in root’s home directory.
From: zhou via USRP-users
Sent: Tuesday, May 9, 2023 12:53 PM
To: usrp-users@lists.ettus.com; Marcus D. Leech
Subject: [USRP-users] Re: Can't find calibration file for X310
Thanks for your
Hi Ofer, does the probe work if you specify the radio's IP address? e.g.
something like:
uhd_usrp_probe --args addr=192.168.10.2
If that syntax works, then you might try switching between the SFP+ port (via
copper adapter) and the native RJ45. My memory could be mistaken here, but I
v
Hello,
I'm looking for advice on toggling an E320 GPIO pin at a specific
uhd::time_spec_t. My use case is a UHD application that starts a long transmit
burst at a known timespec, then later toggles a pin at a time corresponding to
the Nth sample being transmitted. The pin controls an external R
blocks), and it’s unclear to me whether those pokes could get blocked in a
queue behind a timed command. Assuming so, I might be able to sequence
interactions to avoid that case.
Thanks again,
-David
From: Rob Kossler
Sent: Thursday, September 21, 2023 4:26 PM
To: David Raeman
Cc: usrp-users
Hi Devin,
If you have some grace time to play with upon getting a reset condition, you
could let the queued TX burst(s) finish before proceeding with your reset
logic. After you’ve provided a packet to tx_streamer->send() where
end_of_burst=true, the radio provides an acknowledgement after the
Hi Shane,
I've had success using DPDK with ~200Msps rates over a QSFP+ link to a USRP
N320. I still have the uhd.conf file from that project but do not have the
hardware on hand to try anything.
One difference is that my uhd.conf used only underscores, not dashes. UHD's key
matching in /host/l
Hi Brian,
One approach that worked for me – there’s an EEPROM flag you can set so that
the N320 automatically boots when power is applied [1]. Then plug the N320 into
an Ethernet-controlled power switch, and you can cause it to boot remotely by
enabling power via network control.
Hope this hel
Hello,
I am also using multiple distributed E320s for an application that uses the
integrated GPSDO to have a common sense of time for precise TOA estimation. I
don't have the measurements at my fingertips at the moment, but I found that
synchronization was substantially better using a high-qua
don't mind
changing resistor populations if there is a reason to. Or any other suggestions
around this topic?
Thank you,
David Raeman
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change. I may try this on one radio and
see if it helps improve consistency..
-David
From: Marcus D. Leech
Sent: Wednesday, June 5, 2024 8:56 AM
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Re: GPS fix behavior on USRP E320
On 05/06/2024 08:43, David Raeman via USRP-users wrote:
Hello
.
So not an SDR issue, but perhaps this thread may help a USRP user in the
future..
[1] https://www.usb.org/sites/default/files/327216.pdf
From: Marcus D. Leech
Sent: Wednesday, June 5, 2024 7:59 PM
To: David Raeman ; usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Re: GPS fix behavior on
Hi Emre,
You can use UHD 4.6 with a USRP E320. However, the version on your host
computer and on the USRP must be the same. You will need to update the E320
filesystem to also be on UHD 4.6. There are instructions in the “E320 Getting
Started Guide”.
Hope this helps,
David
From: Emre YILDIZ
Any chance you’re using timed commands elsewhere in your application? IIRC,
there is one command FIFO, and a timed command that is waiting to start will
block anything that comes in behind it, even if you didn’t intend for those
other actions to wait. Except for timed streamer transfers, which a
Hi Marino, a couple quick thoughts:
1. My previous message was based on legacy USRP architecture - I think with
RFNoC radios, each block may have its own command queue. So the behavior may be
different than mentioned in my earlier reply.
2. I think setting the command time to "lastPPS + s
Hi John,
You might investigate whether the “ATR” GPIO functionality built into UHD will
work for your application. It can automatically transition GPIO pins to
different states during transmission and reception.
If that doesn’t work for your use case, I’ve had success using the software
GPIO A
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