This is very helpful, thanks for the response Piotr! I was starting to speculate that maybe there is some cross-talk in the clocking front-end switch (U55), enough to quasi-periodically perturb the PLL. I don't believe UHD turns off the GPSDO's TCXO when the external clock is selected, so they'd both be coming into the switch ports. This is complete speculation, but I don't see many avenues for how the internal and external clocking paths differ.
Even though the E320's GPSDO cannot be removed, I can experiment with explicitly powering it down. Thanks for the suggestion! Cheers, David > -----Original Message----- > From: Piotr Krysik <per...@o2.pl> > Sent: Wednesday, September 7, 2022 9:31 AM > To: usrp-users@lists.ettus.com > Subject: [USRP-users] Re: E320: Periodic phase jumps w/ any external clock? > > Hi David, > > I've seen something similar on USRP B210 when I tried to use external 10MHz > reference clock and there was GPSDO inside of the device. There was longer > time between phase jumps: > https://lists.ettus.com/empathy/attachment/277949 > > Look at the "Phase jumps in USRP B210 with GPSDO" topic from 2017 for > more: > https://lists.ettus.com/empathy/thread/5N6RUTKSFPCL3C47WQMAAZKTD6 > FMSWAT?hash=6RMPOPLWPZXSBKXMUV7YAP5DLGD6WGGM#6RMPOPLW > PZXSBKXMUV7YAP5DLGD6WGGM > > Removing GPSDO module solved the issue for me. Disabling GPSDO on E320 > might be much harder as it is built-in to the device. > > Best Regards, > Piotr Krysik > > W dniu 02.09.2022 o 17:21, David Raeman pisze: > > > > Hi all, > > > > I'm working on a project that involves modeling an incoming signal's > > phase as a stochastic process, and I'm seeing a weird phase artifact > > on the E320. It looks like a slow periodic phase perturbation – my > > best guess is something pulling a PLL, because it always returns back > > to a settled state. It occurs with any external clock, but not when > > using the internal clock. I either need to find a way to correct the > > behavior, or to understand the root cause so I can confidently > > consider a different USRP that won’t exhibit this behavior. > > > > I confirmed the same behavior on 3 different E320 radios, first using > > an external OCXO (3Vpp bipolar sinewave) and then using a benchtop > > function generator to create 10MHz square or sinewave clocks. In all > > cases with external clock, the phase artifact can be observed. > > > > I am using only UHD utilities, two radios, and simple offline > > processing of the samples: > > > > (1) Cable radio A (transmitter, an E320) to radio B (receiver, any > > USRP) with 30dB inline attenuation. Determine appropriate gains on > > both radios to ensure the receiver will receive a robust, unsaturated > > signal level. > > > > (2) Radio A uses UHD’s tx_waveforms utility to send a 150kHz sine wave > > with 400MHz carrier frequency and 500kHz sampling rate, where > > reference clock can be internal (no problem) or external (problem). > > > > (3) Radio B uses UHD’s rx_samples_to_file utility to capture 10 > > seconds of data at the same frequency and sampling rate, always using > > internal clock. > > > > This is repeated for various clock options on the transmitter, > > everything else held constant. In a theoretically ideal system, the > > unwrapped phase of the received baseband sinewave should be a line, > > but in reality it'll wander due to imperfect clocks, noise, and other > > systems effects. I want to see the wander, so my processing is: > > > > (1) Compute the unwrapped phase over the 10 seconds of the captured > > I/Q samples. > > > > (2) Compute the best-fit linear trend line of the unwrapped phase, and > > subtract it > > > > (3) Plot the unwrapped phase residuals > > > > Here are some images showing internal clock, external OCXO, and > > external function generator square wave: < > > https://imageshack.com/a/u1YW7/1 >. For all three cases I’m showing > > the unwrapped phase residuals over the full 10 seconds, and then plot > > zoomed into two seconds to show more detail. You can clearly see the > > periodic phase issues on both the external clock cases, but not the > > internal clock case. > > > > Is this a known issue? Any speculation on what might cause this effect > > when using an external clock? I can't figure out what the internal > > TXCO does that is distinct here-- they both feed into the same ADF4002 > > PLL. The internal clock runs at 20MHz, but I was able to try an > > external clock at that rate (required a 2-line patch to UHD) and it > > didn't make a difference. The only other USRP I have on hand is an > > N320, and this issue does not seem to happen on that radio model when > > I use the same OCXO. > > > > Thank you, > > > > -- > > > > David Raeman > > > > Synoptic Engineering > > > > > > _______________________________________________ > > USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe > > send an email to usrp-users-le...@lists.ettus.com > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an > email to usrp-users-le...@lists.ettus.com _______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
