Re: [USRP-users] Creating RFNOC block that changes stream rate

Hi Andrew, You'll need to have a Xilinx USB programmer (or Digilent JTAG-HS3 probably works too), purchase this kit https://www.ettus.com/product/details/E-JTAG-4, and follow these instructions: https://www.ettus.com/content/files/E-Series_JTAG-AVR_Cable_Getting_Started_Guide_.pdf. For setting up

Re: [USRP-users] Creating RFNOC block that changes stream rate

Hi Andrew, Have you tried using Chipscope to see where the issue is at in your code? You want to look at the tvalid and tready AXI stream control signals to pinpoint where your data flow stalls (i.e. tvalid = 1 and tready = 0). Once you know where the stall is located, I can provide more advice.

Re: [USRP-users] rfnoc build works for E310, doesn't meet timing with X310

Hey Jason, Do you need to be able to run the block at 200 MSPS? If not, I would suggest changing all instances of ce_clk to bus_clk in your block. bus_clk runs at ~187.5 MHz versus ~214 MHz for ce_clk, so it could give you the extra margin you need to make timing. You can also make the change by

Re: [USRP-users] RFNoC block fpga control source issues

Hi Sam, Interesting find. Fundamentally, chdr_frame was designed to buffer and release on packet boundaries. This is due to the crossbar being packet switched and ensures packets flow through the crossbar at full rate. Generally, that is only important for sample data, which could have large packe

Re: [USRP-users] RFNoC block fpga control source issues

Hey Sam, There have been some changes to noc_shell, maybe they are related to your issue. If you want to try to debug this on the FPGA, I suggest using chipscope on the file cmd_pkt_proc.v. That is the state machine that receives command packets and issues settings bus writes. You should be able t

Re: [USRP-users] RFNoC block fpga control source issues

How does your testbench work? Do you add the radio core block, send timed commands to it, and see the outputs toggle? On Sat, Oct 20, 2018 at 1:05 PM Samuel Prager wrote: > Hi Jonathon, > > Thanks for the response! Yes I’m using ce_clk and ce_rst. Thanks for > sharing your code — the only real d

Re: [USRP-users] RFNoC block fpga control source issues

Hi Sam, I am using command packets to tune the DDC block's DSP frequency. Are you using ce_clk and ce_rst for clock and reset? Here is my code if you want to take a look: https://pastebin.com/1AeHFb0J. Also, it might be worth trying your code on a release tag like v3.13.0.2 in case master has a re

Re: [USRP-users] X300 FP GPIO with RFNoC API

Hey Ryan, I have a PR that adds custom I/O support for RFNoC blocks with FPGPIO support as part of that. It is still being looked at internally at Ettus, but I'll send you a patch to try it out. Jonathon On Fri, Oct 5, 2018, 5:59 AM Ryan Marlow via USRP-users < usrp-users@lists.ettus.com> wrote:

Re: [USRP-users] RFNoC OFDM blocks error building FPGA image

Hi Sarah, I have submitted a pull request with some OFDM improvements including a fix for this issue, hopefully it will be merged soon. I'll send you the patch set to try out in the meantime. Jonathon On Fri, Sep 28, 2018 at 11:05 AM Sarah Tran via USRP-users < usrp-users@lists.ettus.com> wrote:

Re: [USRP-users] max usable SPP on the E310

Hey Jason, Yes 512 is the max SPP, due to the 4k max DMA transfer size. To support larger FFTs, you could modify the FFT noc block to split up the frames between multiple packets and issue an EOB on the last packet. I have tried that in the past and had some success. Jonathon On Tue, Sep 25, 201

Re: [USRP-users] general RFNoC timing question

Hey Jason, In regards to your original post, I wonder if the issue is due to the split stream block. Perhaps it has a bubble state and cannot keep up at full rate. Have you tried moving the Keep One in N before the split stream? Jonathon On Tue, Sep 25, 2018 at 10:07 PM Jason Matusiak via USRP-u

Re: [USRP-users] Pulling in AXI_FFT into a OOT module and block

I see now. Simulation is a bit different than building images. To prevent building every IP for every simulation, the exact IP you want to use needs to be added to the test bench Makefile. It is pretty easy. Add the following to the test bench Makefile in rfnoc/testbenches//Makefile: LIB_IP_DIR =

Re: [USRP-users] Pulling in AXI_FFT into a OOT module and block

Hi Rich, The standard Ettus in-tree Vivado IP, which includes the axi_fft, is automatically included. You do not need to do anything. Have you went through the RFNoC getting started guide ( https://kb.ettus.com/Getting_Started_with_RFNoC_Development)? I think that will help you understand the FPGA

Re: [USRP-users] Phase Representation: Using Xilinx CORDIC IP with RFNoC

Hey Steve, The complex_to_mag_phase 32-bit output is a concatenation: [31:16] phase, [15:0] magnitude. There is also complex_to_magphase_int16_int24 if you want 24-bit phase, mag. The phase value is in scaled radians. If you want a different phase precision, you will need to create a new CORDIC I

Re: [USRP-users] Pulling in AXI_FFT into a OOT module and block

If you only need integer decimation, noc_block_ddc should have everything you need or close to it. Averaging across FFTs can be done with noc_block_vector_iir. For an example, check out the flowgraph rfnoc_vector_iir.grc in gr-ettus. Jonathon On Tue, Sep 4, 2018 at 3:23 PM Rich Maes wrote: > I’

Re: [USRP-users] Pulling in AXI_FFT into a OOT module and block

Hey Rich, Do you want to customize the FFT IP or use it as is? If you are using it as is, there is no need to do anything. All in-tree code and IP is automatically included as part of the FPGA build. If you want to customize it, I suggest copying the FFT IP into your OOT and using https://github.c

Re: [USRP-users] Problem running RFNoC testbench all of a sudden

Hey Jason, I ran into this problem too when I had a syntax error in sim_rfnoc_lib.svh (I was messing around with the core RFNoC testbench infrastructure code). After I fixed my typo, it went away. I suspect this is just a bug in xsim. Jonathon On Wed, Aug 8, 2018 at 9:52 PM Jason Matusiak via US

Re: [USRP-users] packet size for RFNOC testbenches

Hey Jason, You could try testing with noc_block_skeleton. It only does a loopback and has a self checking testbench. Jonathon On Mon, Aug 20, 2018, 11:48 PM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I have been trying to figure out an issue with my block for a while,

Re: [USRP-users] about rfnoc nocshell

Hi Carry, Unless you left out some more details, it sounds like you just want to transmit. In that case you should use the regular UHD API and you can ignore my previous suggestions. Take a look at the examples tx_waveforms.cpp and tx_samples_from_file.cpp for how to use the UHD API. Jonathon On

Re: [USRP-users] Debugging RFNoC siggen

Hi Koen, Your block should not wait on tready, that is a violation of the AXI spec. Some blocks actually wait for tvalid to be asserted before asserting tready (that is permitted by the spec), which would cause a deadlock in your situation. You can work around that by putting an axi_flip_flop in t

Re: [USRP-users] about rfnoc nocshell

Hi. Yes, but you should leave that one alone and setup your own datamover on another HP AXI port. What do you want to accomplish? Jonathon On Sun, Aug 5, 2018 at 11:44 AM, carry chen wrote: > > Thanks Jonathon! > Does uhd fpga use datamover access PS DDR now? > > Best Regards, > Carry > > _

Re: [USRP-users] noc_block_null_source_sink module

You cannot have a block with 0 inputs or 0 outputs from the HDL perspective. You will always have at least 1 input and 1 output. You can tie off the unused input or output though. Also, in your GRC XML, you can choose not to declare the output or input. Check out uhd_rfnoc_siggen.xml, which works j

Re: [USRP-users] RFNoC flowgraph runs right the second time

Hey Jason, Have you tried using a smaller SPP such as 256? Jonathon On Thu, Jul 26, 2018 at 2:39 AM, Jason Matusiak via USRP-users wrote: > So, somehow I got things working for the first run in a certain situation. > I attached 2 pictures to show my flowgraphs. Again, my LBT block is > current

Re: [USRP-users] about rfnoc nocshell

Hi, 1) You cannot reduce noc_shell resource usage much. You can try putting all your custom logic in just one RFNoC block, that way you do not incur the overhead of multiple noc_shell instances. 2) Do you mean "Can I access PS DDR memory directly from the FPGA fabric?" If so, yes you can via the H

Re: [USRP-users] noc_block_null_source_sink module

Hey Jason, The block is functionally complete, in fact I think it was the first block ever made. There is a UHD C++ example, rfnoc_nullsource_ce_rx.cpp, that uses it. A block controller and GRC xml for GNU Radio needs to be created though. Jonathon On Wed, Jul 18, 2018 at 4:38 AM, Jason Matusiak

Re: [USRP-users] Possible to enable via RFNoC block via RFNoC

Hey Jason, You can send a command packet to another block via noc_shell's cmd_out port. Command packets basically encapsulate a settings bus write. In the payload of the command packet, the upper 32 bits are the settings register address and the lower 32 bits are the data. Also, the block will rep

Re: [USRP-users] Problem with the most recent UHD changes building

Hey Jason, The fix was pushed recently and builds fine for me now. Jonathon On Tue, Jul 3, 2018, 2:27 AM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I just tried to pull down and build a fresh RFNoC install and it keeps > failing. I think this is related to the commit

Re: [USRP-users] X310 Register's Memory Capability

Hi Steve, USE_EMBEDDED_REGS_COEFFS means that the filter will attempt to infer the DSP48's embedded registers (specifically register B) for storing coefficients. You should refer to Xilinx's DSP48 design doc https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf. Using

Re: [USRP-users] Timeout On Chan 0 Error

Hi Peter, Does the testbench you make as part of the tutorial work? Jonathon On Wed, May 23, 2018, 12:09 PM Peter Sanchez via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > I have a USRP X310 and just finished going through the RFNoC Getting > Started tutorial. After uploading th

Re: [USRP-users] RFNoC: FIR Filter final tap never gets written to settings register

Hey Andrew, The next line in fir_block_ctrl_impl.cpp sends the final tap: sr_write(SR_RELOAD_TLAST, uint32_t(taps.back())); The half a sample shift is odd though. On Sat, Apr 21, 2018, 6:23 AM Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> wrote: > On 04/20/2018 12:01 PM, switchla

Re: [USRP-users] problem to work witth source file and RFnoC block and FIR block

> I want to use this block with 1,000 coefficients, but when I tried to do so > I saw that the maximum possible is only 41 coefficients. > > Does anybody know if Ettus has any solution to use FIR with 1,000 > coefficients? The number of taps is an adjustable parameter in the FIR filter block's Ver

Re: [USRP-users] bug using rx_stream constructor inside a loop ...

Hello Matis, Can you turn on full UHD logging and pastebin the output? Jonathon On Fri, Apr 6, 2018, 4:28 PM Matis Alun via USRP-users < usrp-users@lists.ettus.com> wrote: > Le 05/04/2018 à 16:29, Marcus D. Leech via USRP-users a écrit : > > On 04/05/2018 04:55 AM, Matis Alun via USRP-users wr

Re: [USRP-users] file_souce block for RFNoC

Hi, The file_source and file_sink blocks (and corresponding RFNoC blocks) are only useful for simulations. File I/O is not a sythensizable operation. Jonathon On Thu, Apr 5, 2018, 7:17 AM Xingjian Chen via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi there, > > I find the "file_source"

Re: [USRP-users] Rfnoc over flow

Hi Snehasish, How long do you record samples? Do the overflows occur immediately? Are they continuous, bursty, only at the beginning? What rate can you run at without overflows? I would suggest running "benchmark_rate --rx_rate 25.6e6 --duration 600" and "uhd_fft --samp-rate 25.6e6 --freq 2.4e9".

Re: [USRP-users] RFNoC Block with two inputs and one output.

Hi Mark, Are you getting a specific error message in GRC? You'll need to post more details for someone to help you. Jonathon On Wed, Dec 13, 2017 at 4:46 AM, Mark Luscombe via USRP-users wrote: > Hi all, > > My next question ;-) > > I want to create a RFNoC Block with two SC16 inputs and one SC

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

Hi Tien, Run 'make xsim' in the same directory as the testbench. Jonathon On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < usrp-users@lists.ettus.com> wrote: Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simul

Re: [USRP-users] RFNoC: Synthesizing a block containing modules from uhd-fpga

Hi Adam, Can you post your testbench makefile? Jonathon On Jan 10, 2018 5:07 PM, "Adam Parower via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hello everyone, > > > I am trying to create a custom RFNoC block that is similar to the built-in > DUC block. As such, it depends on the cordic_t