Hi Tien, Run 'make xsim' in the same directory as the testbench.
Jonathon On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < usrp-users@lists.ettus.com> wrote: Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simulate the built-in RFNoC block? I see the simulate file (for example noc_block_fft_tb.sv) but not sure how to run it.. Thank you very much for the help. Best, Tien On Mon, Jan 22, 2018 at 10:55 AM, EJ Kreinar <ejkrei...@gmail.com> wrote: > Hi Tien, > > If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can > follow the example provided in the Makefile for the noc_block_fft_tb: > https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/n > oc_block_fft_tb/Makefile > > Note the three steps: > 1. set LIB_IP_DIR > 2. Include the Makefile.inc associated with the Xilinx IP > 3. Append generated IP to the DESIGN_SRCS > > If the Xilinx IP you want to use is contained in an OOT repo, then you > would want to follow the Makefile.inc process of including the OOT repo: > https://github.com/ejk43/rfnoc-ootexample > > The "noc_block_complextomagphase_tb" example shows an example of how to > include and simulate Xilinx IP inside an OOT repo: > https://github.com/ejk43/rfnoc-ootexample/blob/master/ > rfnoc/testbenches/noc_block_complextomagphase_tb/Makefile > > For another example, this repo with a polyphase channelizer also shows how > to include and simulate Xilinx IP in an OOT repo: https://github.com/e33b1 > 711/rfnoc-ppchan > > Hope this helps, > EJ > > On Fri, Jan 19, 2018 at 10:28 PM, Dang tien Vo-Huu via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi all, >> I have this error when trying to simulate a custom RFNoC block in an OOT >> module: >> >> $ make noc_block_hbFilter_tb >> ..... >> ..... >> Starting static elaboration >> ERROR: [VRFC 10-2063] Module <fir_compiler_0> not found while processing >> module instance <fir_compile_0_inst> [/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] >> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design >> unit(s) in library work failed. >> INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/r >> fnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_ >> tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' >> ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check >> the Tcl console output or '/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xs >> im_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more >> information. >> ..... >> ..... >> >> I can build an FPGA image with the custom RFNoC block following the >> instruction here: http://www.synchronouslabs.com/blog/creating-a-custom- >> rfnoc-block-with-using-xillinx-ip >> but I haven't found a way to simulate this block. >> Is there any way to run the simulation in this situation? Otherwise it >> would be difficult to debug if anything goes wrong.. >> >> Thanks in advance. >> >> Best, >> Tien >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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