Hi Sarah,

I have submitted a pull request with some OFDM improvements including a fix
for this issue, hopefully it will be merged soon. I'll send you the patch
set to try out in the meantime.
Jonathon

On Fri, Sep 28, 2018 at 11:05 AM Sarah Tran via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi all,
>
>
> I am trying to build a custom FPGA image for my X310
> (daughterboards=UBX-160) using the uhd_image_builder gui and trying to use
> the following blocks:
>
> fft
>
> schmidl_cox
>
> eq
>
> ofdm_constellation_demapper
>
>
> as the code is running and building, it always stops on this error:
>
> '
> [00:22:41] Current task: Logic Optimization +++ Current Phase: Finished
> [00:22:41] Starting Connectivity Check Task
> ERROR: [Opt 31-2] SRLC32E
> x300_core/inst_eq/inst_axi_wrapper/header_fifo/fifo_short/gen_srlc32e[64].srlc32e
> is missing a connection on D pin.
> [00:22:51] Current task: Connectivity Check +++ Current Phase: Starting
> [00:22:51] Current task: Connectivity Check +++ Current Phase: Finished
> [00:22:51] Process terminated. Status: Failure
>
> ========================================================
> Warnings:           862
> Critical Warnings:  36
> Errors:             1
>
> Makefile.x300.inc:111: recipe for target 'bin' failed
> make[1]: *** [bin] Error 1
> make[1]: Leaving directory '/home/lsop/rfnoc/fpga/usrp3/top/x300'
> Makefile:119: recipe for target 'X310_RFNOC_HG' failed
> make: *** [X310_RFNOC_HG] Error 2'
>
> I can't seem to get it resolved, and I was wondering if there was a trick
> that someone else was able to use to get it to build. Any help or insight
> is appreciated.
>
> Thank you,
> Sarah
>
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