itialization" should implement
> the original intent of the reverted commit in a more robust manner.
>
> This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Bin Meng
> ---
Reviewed-by: Rick Chen
ipi_clear
> - Only compile dummy_pending_ipi_clear when SMP is enabled
>
> Changes in v2:
> - Make riscv_ipi_init_secondary_hart static
>
> arch/riscv/cpu/cpu.c | 20 ++++
> 1 file changed, 20 insertions(+)
>
Reviewed-by: Rick Chen
tion")
> Signed-off-by: Sean Anderson
> Reviewed-by: Bin Meng
>
> ---
>
> Changes in v3:
> - Clarify XIP comment
>
> Changes in v2:
> - Set gp early with XIP
>
> arch/riscv/cpu/start.S | 28 +---
> arch/riscv/lib/interrupts.c | 3 ++-
> 2 files changed, 27 insertions(+), 4 deletions(-)
>
Reviewed-by: Rick Chen
| 38 -
> drivers/timer/Kconfig | 4 ++--
> drivers/timer/riscv_timer.c| 39 +-
> 8 files changed, 25 insertions(+), 71 deletions(-)
> delete mode 100644 arch/riscv/lib/rdtime.c
>
Reviewed-by: Rick Chen
imer.h | 15 +++
> 2 files changed, 40 insertions(+)
>
Reviewed-by: Rick Chen
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Friday, September 25, 2020 2:31 PM
> To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List
> Cc: Bin Meng
> Subject: Re: [PATCH 1/2] ram: sifive: Check return value on clk_enable()
>
> On Tue, Sep 15, 2020 at 4:05 PM Bin Meng wrote:
>
Hi Sean
> This function is designed to be used when a timer used to be initialized by
> the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
> such a case, the timer may prefer to use the clocks and clock-frequency
> properties, but should be able to fall back on using the cpu
Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> Saving and restoring the caller's x3 is already handled in mtrap.S.
> efi_loader.h provides an empty fallback efi_restore_gd() function
> if CONFIG_EFI_LOADER=n.
> ---
> arch/riscv/lib/interrupts.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Rick Chen
Hi Heinrich
> On 28.09.20 09:45, Rick Chen wrote:
> >> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> >> Sent: Sunday, September 27, 2020 4:24 PM
> >> To: Rick Jian-Zhi Chen(陳建志)
> >> Cc: Simon Glass; Sean Anderson; Bin Meng; u-boot@lists.den
->t5, regs->t6);
> #endif
> }
> @@ -79,12 +79,12 @@ static void _exit_trap(ulong code, ulong epc, ulong tval,
> struct pt_regs *regs)
> printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
>epc, regs->ra, tval);
>
Hi Tom
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Tuesday, September 29, 2020 7:57 PM
> To: Open Source Project uboot
> Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: Pull request: u-boot-riscv/master 20200929
>
> On Tue, Sep 29, 2020 at 03:50:15PM +0800, ub...@andestec
Hi Heinrich
> On 29.09.20 10:22, Rick Chen wrote:
> >> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> >> Sent: Sunday, September 27, 2020 7:21 AM
> >> To: Rick Jian-Zhi Chen(陳建志)
> >> Cc: Simon Glass; Sean Anderson; Bin Meng; u-boot@lists.denx.de;
the defaults more closely
>
> arch/riscv/dts/k210-maix-bit.dts | 104 +++
> arch/riscv/dts/k210.dtsi | 12
> 2 files changed, 116 insertions(+)
>
Acked-by: Rick Chen
e the button status to decide which program to boot.
>
> Changes in v6:
> - New
>
> arch/riscv/dts/k210-maix-bit.dts | 11 +++
> 1 file changed, 11 insertions(+)
>
Reviewed-by: Rick Chen
iles changed, 9 insertions(+), 8 deletions(-)
> rename arch/riscv/lib/andes_plmt.c => drivers/timer/andes_plmt_timer.c (100%)
Reviewed-by: Rick Chen
> This matches the naming scheme of other timer drivers.
>
> Signed-off-by: Sean Anderson
> ---
>
> arch/riscv/cpu/ax25/Kconfig | 2 +-
> drivers/timer/Kconfig | 2 +-
> drivers/timer/Makefile | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
)
> + return -EINVAL;
> +
> + return timer_timebase_fallback(dev);
> +}
> +
> +static const struct udevice_id sifive_clint_ids[] = {
> + { .compatible = "riscv,clint0" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(sifive_clint) = {
> + .name = "sifive_clint",
> + .id = UCLASS_TIMER,
> + .of_match = sifive_clint_ids,
> + .probe = sifive_clint_probe,
> + .ops= &sifive_clint_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> --
> 2.28.0
LGTM.
Other than that,
Reviewed-by: Rick Chen
d steps are marked as normal text in
> AX25-AE350 documentation.
>
> Move them into code-block so-that it can show it as build steps.
>
> Cc: Heinrich Schuchardt
> Signed-off-by: Jagan Teki
Reviewed-by: Rick Chen
> ---
> doc/board/AndesTech/ax25-ae350.rst | 8 +
25-AE350 RISC-V documentation")
> > Signed-off-by: Heinrich Schuchardt
> > ---
>
> Reviewed-by: Jagan Teki
Reviewed-by: Rick Chen
> > --- a/arch/riscv/cpu/u-boot.lds
> > +++ b/arch/riscv/cpu/u-boot.lds
> > @@ -32,7 +32,6 @@ SECTIONS
> >
> > . = ALIGN(4);
> > .data : {
> > - __global_pointer$ = . + 0x800;
> > *(.data*)
> > }
> > . = ALIGN(4);
Reviewed-by: Rick Chen
> arch/riscv/Kconfig | 3 +++
> arch/riscv/cpu/mtrap.S | 3 ++-
> arch/riscv/lib/interrupts.c | 50 +----
> 3 files changed, 44 insertions(+), 12 deletions(-)
>
Reviewed-by: Rick Chen
Hi Pragnesh
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Friday, January 17, 2020 8:46 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; ja...@amarulasolutions.com;
> troy.benjeger...@sifive.com
rop IMAGE_ENABLE_OF_LIBFDT")
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/lib/bootm.c | 2 --
> arch/riscv/lib/bootm.c | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Rick Chen
configs/qemu-riscv32_smode_defconfig | 4
> configs/qemu-riscv32_spl_defconfig | 7 +++
> configs/qemu-riscv64_defconfig | 4
> configs/qemu-riscv64_smode_defconfig | 4
> configs/qemu-riscv64_spl_defconfig | 7 +++
> 6 files changed, 30 insertions(+)
Reviewed-by: Rick Chen
cv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile | 2 ++
> arch/riscv/lib/interrupts.c | 25 +
> arch/riscv/lib/semihosting.c | 24
> lib/Kconfig | 10 +-
> 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644
> arch/riscv/lib/semihosting.c
Reviewed-by: Rick Chen
ard extension for Single-Precision Floating Point"
> + default y
Shall this default y need to depend on RV32 ?
Reviewed-by: Rick Chen
> + help
> + Adds "F" to the ISA string passed to the compiler.
> +
> +config RISCV_ISA_D
> +
Standard extension for Single-Precision Floating Point"
> >> + default y
> >
> >
> > Shall this default y need to depend on RV32 ?
>
> All RV64 boards that we currently support have the F and D extension and
> these extensions are in RV64GC. There is no
Check firmware_fdt_addr header to see if it is a valid
fdt blob.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index
>
> Reported-by: Yangjie Zhang
> Signed-off-by: Bin Meng
> Tested-by: Yangjie Zhang
>
> ---
>
> board/emulation/qemu-riscv/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
nSBI has been updated to support 8-core AE350 platform,
> the plicsw configuration needs to be modified accordingly.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/lib/andes_plic.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Rick Chen
Check firmware_fdt_addr header to see if it
is a valid fdt blob.
Signed-off-by: Rick Chen
Reviewed-by: Leo Yu-Chi Liang
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech
Reviewed-by: Conor Dooley
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 75 +---
> 1 file changed, 17 insertions(+), 58 deletions(-)
Reviewed-by: Rick Chen
d to the Icicle Kit by using the
> Mikroe Flash 5 click board and the Pi 3 Click shield.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Conor Dooley
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 16 ++++
> 1 file changed, 16 insertions(+)
Reviewed-by: Rick Chen
is made at the end of 32-bit DDR to
> provide some memory for the HSS to use.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Conor Dooley
> ---
> board/microchip/mpfs_icicle/Kconfig | 7 +++
> configs/microchip_mpfs_icicle_defconfig | 1 +
> 2 files changed, 8 insertions(+)
Reviewed-by: Rick Chen
deletions(-) rename
> arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%)
Reviewed-by: Rick Chen
as been ack'd for the Linux kernel, remove
> > support here as well.
> >
> > Cc: Rick Chen
> > Signed-off-by: Tom Rini
>
> Ping?
Sorry for the late responses.
Thanks for the information.
Thanks,
Rick
>
> --
> Tom
> On Fri, Apr 22, 2022 at 04:45:28PM +0800, Rick Chen wrote:
> > Hi, Tom,
> >
> > > From: Tom Rini
> > > Sent: Wednesday, April 20, 2022 2:43 AM
> > > To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > > Subject: Re: [PATCH] nds32: Remove t
>
> Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other
> architectures too.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> move the setting to /Kconfig
> ---
> Kconfig| 2 +-
> arch/riscv/Kconfig | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
Reviewed-by: Rick Chen
LIC is used for external interrupt, while PLICSW is an Andes-specific design
> for software interrupt.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/include/asm/global_data.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
It seems not relative to cache
--
> drivers/cache/Kconfig | 1 -
> 3 files changed, 2 insertions(+), 93 deletions(-)
Reviewed-by: Rick Chen
ard_init()
>
> The L2-cache is not enabled currently, the enbale_caches() will call the
> v5l2_enable() callback to enable it in SPL.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen
Hi Peter,
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH 08/11] configs: ae350: Enable v5l2 cache for AE350 platforms
>
> Enable cache-v5l2
Peter Lin
> Reviewed-by: Leo Yu-Chi Liang
> ---
> drivers/cache/cache-v5l2.c | 32
> 1 file changed, 24 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen
arch/riscv/include/asm/arch-andes/csr.h | 29 +++
> 2 files changed, 41 insertions(+), 37 deletions(-) create mode 100644
> arch/riscv/include/asm/arch-andes/csr.h
Reviewed-by: Rick Chen
changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
1 file changed, 68 insertions(+), 30 deletions(-)
Reviewed-by: Rick Chen
/ae350_rv64_spl_xip_defconfig | 2 ++
> 5 files changed, 9 insertions(+)
Reviewed-by: Rick Chen
2 ++
> configs/ae350_rv32_spl_xip_defconfig | 2 ++
> configs/ae350_rv32_xip_defconfig | 2 ++
> configs/ae350_rv64_defconfig | 2 ++
> configs/ae350_rv64_spl_defconfig | 2 ++
> configs/ae350_rv64_spl_xip_defconfig | 2 ++
> configs/ae350_rv64_xip_defconfig | 2 ++
> 8 files changed, 16 insertions(+)
Reviewed-by: Rick Chen
Hi Zong,
> From: Leo Yu-Chi Liang(梁育齊)
> Sent: Monday, February 06, 2023 3:58 PM
> To: Simon Glass
> Cc: U-Boot Mailing List ; Rick Jian-Zhi Chen(陳建志)
> ; zong...@sifive.com; vincent.c...@sifive.com
> Subject: Re: Docs for RISC-V
>
> Hi Simon,
>
> On Thu, Feb 02, 2023 at 10:25:36AM -0700, Simon
> So it will be named similarly to the related ftgmac100 driver.
> The old name 'nds32_mac' is not referred to anywhere in U-Boot.
>
> Signed-off-by: Sergei Antonov
> Reviewed-by: Ramon Fried
Reviewed-by: Rick Chen
#x27;phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in struct
> ftmac100_data. It allows to remove casting in a number of places.
>
> Since priv->iobase is phys_addr_t, use phys_to_virt() to make a pointer from
> it.
>
> Signed-off-by: Sergei Antonov
Reviewed-by: Rick Chen
s with read and write callbacks to allow the 'mii'
> command to work. Use a timeout of 10 ms to wait for the R/W operations to
> complete.
>
> Signed-off-by: Sergei Antonov
> ---
Reviewed-by: Rick Chen
Tested-by: Rick Chen
I have verified this patch on AE350 platform an
related defconfigs could also support newer Andes CPU IP,
> so modify the names of CPU from ax25 to andesv5, and board name from
> ax25-ae350 to ae350.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Rick Chen
off-by: Leo Yu-Chi Liang
> ---
> configs/ae350_rv32_spl_defconfig | 6 +++---
> configs/ae350_rv32_spl_xip_defconfig | 6 +++---
> configs/ae350_rv64_spl_defconfig | 6 +++---
> configs/ae350_rv64_spl_xip_defconfig | 6 +++---
> 4 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Rick Chen
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen
---
arch/riscv/dts/binman.dtsi | 1 +
tools/binman/missing-blob-help | 4
2 files changed, 5 insertions(+)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.
gt; - Add some pointers to OpenSBI document
>
> [1]
> https://patchwork.ozlabs.org/project/uboot/patch/20230212070053.14800-1-peter...@andestech.com/
> ---
> MAINTAINERS| 1 +
> doc/arch/index.rst | 1 +
> doc/arch/riscv.rst | 74 ++
> 3 files changed, 76 insertions(+)
> create mode 100644 doc/arch/riscv.rst
Reviewed-by: Rick Chen
Hi Leo
> On Thu, Feb 16, 2023 at 09:19:45AM +0800, Rick Chen wrote:
> > Add the 'missing-msg' for more detailed output
> > on missing system firmware.
> >
> > Signed-off-by: Rick Chen
> > ---
> > arch/riscv/dts/binman.dtsi | 1 +
> >
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen
Reviewed-by: Leo Yu-Chi Liang
---
Changes in v2
- Add more descriptions about fw_dynamic.bin
---
arch/riscv/dts/binman.dtsi | 1 +
tools/binman/missing-blob-help | 6 ++
2 fil
.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/cpu/cpu.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
Hi Heinrich
> From: Heinrich Schuchardt
> Sent: Tuesday, November 08, 2022 11:14 PM
> To: Bin Meng
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Conor Dooley ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] riscv: clarify meaning of CONFIG_SBI_V02
>
> On 11/8/22 16:05, Bin Meng
ff-by: Heinrich Schuchardt
> >>
> >> ---
> >> arch/riscv/Kconfig | 14 +++---
> >> 1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Rick Chen
instead of select for SPL_SEPARATE_BSS
>
> Use imply instead of select, then it can still be disabled by board-specific
> defconfig, or be set to n manually.
>
> Signed-off-by: Zong Li
> ---
> arch/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
> From: Zong Li
> Sent: Tuesday, November 29, 2022 10:02 AM
> To: Sean Anderson
> Cc: s...@chromium.org; michal.si...@amd.com; sean.ander...@seco.com; Leo
> Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH] riscv: use imply instead of select for SPL_SEP
.
Signed-off-by: Rick Chen
---
common/spl/Kconfig | 14 ++
common/spl/spl_fit.c | 3 ++-
common/spl/spl_opensbi.c | 25 -
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 05181bdba3
By enabling SPL_OPENSBI_OS_BOOT, it will generate linux.itb instead
of default u-boot.itb after compiling. And Lnux Kernel Image will be
appended in linux.itb. Then it can jump to Linux Kernel from openSBI
directly.
Signed-off-by: Rick Chen
---
arch/riscv/dts/binman.dtsi | 24
Add defconfig for Fast Boot
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 7 ++-
configs/ae350_rv32_spl_fastboot_defconfig | 53 +++
configs/ae350_rv64_spl_fastboot_defconfig | 53 +++
3 files changed, 111 insertions(+), 2
Descript how to boot Kernel with Fast Boot and record
booting messages here.
Signed-off-by: Rick Chen
---
doc/board/AndesTech/ax25-ae350.rst | 140 +
1 file changed, 140 insertions(+)
diff --git a/doc/board/AndesTech/ax25-ae350.rst
b/doc/board/AndesTech/ax25-ae350
to the Kconfig file. If this is user configurable, it needs to be exposed
> rather than hidden, and should probably be renamed as well.
>
> Cc: Rick Chen
> Signed-off-by: Tom Rini
> ---
> board/AndesTech/ax25-ae350/Kconfig | 4
> include/configs/ax25-ae350.h |
; arch/riscv/cpu/fu740/spl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
ivetree API for this driver.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/mmc/ftsdc010_mci.c | 22 +++---
> 1 file changed, 7 insertions(+), 15 deletions(-)
Reviewed-by: Rick Chen
configs/ae350_rv64_spl_xip_defconfig | 1 +
> configs/ae350_rv64_xip_defconfig | 1 +
Reviewed-by: Rick Chen
ster
>
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
>
> Signed-off-by: Brad Kim
> ---
> arch/riscv/cpu/start.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rick Chen
> diff --
Hi Pragnesh,
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Tuesday, November 17, 2020 7:05 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Jia
Hi Pragnesh
> Hi Rick,
>
> >-Original Message-----
> >From: Rick Chen
> >Sent: 24 November 2020 13:08
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Atish Patra
> >; Bin Meng ; Paul Walmsley (
> >Sifive) ; Anup Patel ; Sagar
> >Kad
Hi, Pragnesh
> Hi Rick,
>
> >-Original Message-----
> >From: Rick Chen
> >Sent: 26 November 2020 14:44
> >To: Pragnesh Patel
> >Cc: Simon Glass ; U-Boot Mailing List >b...@lists.denx.de>; Atish Patra ; Bin Meng
> >; Paul Walmsley ( Sifive) ;
Hi Padmarao
> From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> Sent: Thursday, December 03, 2020 4:32 AM
> To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
> anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com;
> lu...@denx.de; atish.pa.
Hi Pragnesh
> Hi Rick,
>
> [...]
> >>
> >>Following are the configurations, steps and debug logs:
> >>
> >>+++ b/configs/ae350_rv64_defconfig
> >>q+CONFIG_TRACE=y
> >>+CONFIG_TRACE_BUFFER_SIZE=0x0100
> >>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
> >>+CONFIG_CMD_TRACE=y
> >>+CONFIG_TIMER_EARLY=y
> >>
> > Subject: [PATCH v4 0/3] RISC-V S-mode support
> >
> > This patchset allows us runing u-boot in S-mode which is useful on platforms
> > where M-mode runtime firmware is an independent firmware and u-boot is used
> > as last stage OS bootloader.
> >
> > The patchset based upon git://git.denx.de/u
> Hi All,
>
>
>
> Is it possible to include this series for next U-Boot release?
Hi Anup
Yes.
I will do some verification.
And prepare the PR ASAP.
Can you prepare a version which will be rebase on the latest u-boot-riscv.git
Thanks
Rick
>
>
>
> Regards,
>
> Anup
>
__
> > > > Currently, the RISC-V U-Boot is saving a2 register at
> > > > CONFIG_SYS_DRAM_BASE in start.S which does not make sense because
> > > > there is no information passed by previous booting stage in a2
> > > > register.
> > > >
> > > > This patch removes redundant a2 store on DRAM base.
> > >
> > > Hi Tom,
> > >
> > > Please pull the following patch from u-boot-riscv into your tree.
> > > Thanks!
> >
> > In the future can you please include a short summary here if you aren't
> > using a
> > signed tag? Thanks!
Hi Tom
Sorry about that !
I will use a signed tag or include a short s
Anup Patel 於 2018年11月27日 週二 上午11:28寫道：
>
> On Tue, Nov 27, 2018 at 8:50 AM Rick Chen wrote:
> >
> > > > > > Currently, the RISC-V U-Boot is saving a2 register at
> > > > > > CONFIG_SYS_DRAM_BASE in start.S which does not make sense because
> &
Anup Patel 於 2018年11月27日 週二 下午1:47寫道：
>
> On Tue, Nov 27, 2018 at 11:14 AM Anup Patel wrote:
> >
> > On Tue, Nov 27, 2018 at 10:50 AM Rick Chen wrote:
> > >
> > > Anup Patel 於 2018年11月27日 週二 上午11:28寫道：
> > > >
> >
Anup Patel 於 2018年11月27日 週二 下午2:14寫道：
>
>
>
> On Tue, 27 Nov, 2018, 11:38 AM Rick Chen >
>> Anup Patel 於 2018年11月27日 週二 下午1:47寫道：
>> >
>> > On Tue, Nov 27, 2018 at 11:14 AM Anup Patel wrote:
>> > >
>> > > On Tue, Nov 27, 2018 at 10:
> > Subject: [PATCH v5 1/4] riscv: Add kconfig option to run U-Boot in S-mode
> >
> > This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When
> > this
> > opition is enabled we use s CSRs instead of m CSRs.
> >
> > It is important to note that there is no equivalent S-mode CSR for
> > > > > When we run U-Boot in S-mode the BBL runs from 0x8000 so this
> > > > > two lines corrupts BBL instructions.
Hi Anup
You said
Your patchset based upon git://git.denx.de/u-boot-riscv.git
Why you announce this problem in [PATCH v5 4/4] riscv: Remove
redundant a2 store on DRAM base in
Anup Patel 於 2018年11月27日 週二 下午2:40寫道：
>
> On Tue, Nov 27, 2018 at 12:00 PM Rick Chen wrote:
> >
> > Anup Patel 於 2018年11月27日 週二 下午2:14寫道：
> > >
> > >
> > >
> > > On Tue, 27 Nov, 2018, 11:38 AM Rick Chen > >>
> > >> An
Anup Patel 於 2018年11月27日 週二 下午3:56寫道：
>
> On Tue, Nov 27, 2018 at 12:30 PM Rick Chen wrote:
> >
> > Anup Patel 於 2018年11月27日 週二 下午2:40寫道：
> > >
> > > On Tue, Nov 27, 2018 at 12:00 PM Rick Chen wrote:
> > > &g
Bin Meng 於 2018年11月27日 週二 下午6:07寫道：
>
> Hi Rick,
>
> On Tue, Nov 27, 2018 at 4:43 PM Rick Chen wrote:
> >
> > Anup Patel 於 2018年11月27日 週二 下午3:56寫道：
> > >
> > > On Tue, Nov 27, 2018 at 12:30 PM Rick Chen wrote:
> > > >
> > > >
Alexander Graf 於 2018年11月27日 週二 下午6:42寫道：
>
>
>
> On 27.11.18 09:42, Anup Patel wrote:
> > On Tue, Nov 27, 2018 at 1:26 PM Anup Patel wrote:
> >>
> >> On Tue, Nov 27, 2018 at 12:30 PM Rick Chen wrote:
> >>>
> >>> Anup Patel 於 2018年11月
Bin Meng 於 2018年11月27日 週二 下午5:54寫道：
>
> Hi Rick,
>
> On Wed, Nov 21, 2018 at 4:53 PM Rick Chen wrote:
> >
> > Bin Meng 於 2018年11月21日 週三 下午3:18寫道：
> > >
> > > Hi Rick,
> > >
> > > On Wed, Nov 21, 2018 at 2:00 PM Rick Chen wrote:
>
Rick Chen 於 2018年11月29日 週四 下午6:42寫道：
>
> Bin Meng 於 2018年11月27日 週二 下午6:07寫道：
> >
> > Hi Rick,
> >
> > On Tue, Nov 27, 2018 at 4:43 PM Rick Chen wrote:
> > >
> > > Anup Patel 於 2018年11月27日 週二 下午3:56寫道：
> > > >
> > > > On
Bin Meng 於 2018年11月30日 週五 上午9:48寫道：
>
> Hi Rick,
>
> On Thu, Nov 29, 2018 at 6:41 PM Rick Chen wrote:
> >
> > Bin Meng 於 2018年11月27日 週二 下午6:07寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Nov 27, 2018 at 4:43 PM Rick Chen
Bin Meng 於 2018年11月30日 週五 下午2:21寫道：
>
> Hi Rick,
>
> On Fri, Nov 30, 2018 at 2:05 PM Rick Chen wrote:
> >
> > Bin Meng 於 2018年11月30日 週五 上午9:48寫道：
> > >
> > > Hi Rick,
> > >
> > > On Thu, Nov 29, 2018 at 6:41 PM Rick Chen
Anup Patel 於 2018年11月27日 週二 下午8:38寫道：
>
> On Tue, Nov 27, 2018 at 4:17 PM Alexander Graf wrote:
> >
> >
> >
> > On 27.11.18 07:52, Anup Patel wrote:
> > > On Tue, Nov 27, 2018 at 12:09 PM Rick Chen wrote:
> > >>
> > >>>&g
Bin Meng 於 2018年11月30日 週五 下午2:57寫道：
>
> Hi Rick,
>
> On Fri, Nov 30, 2018 at 2:41 PM Rick Chen wrote:
> >
> > Bin Meng 於 2018年11月30日 週五 下午2:21寫道：
> > >
> > > Hi Rick,
> > >
> > > On Fri, Nov 30, 2018 at 2:05 PM Rick Chen
Bin Meng 於 2018年11月30日 週五 下午3:26寫道：
>
> Hi Rick,
>
> On Fri, Nov 30, 2018 at 3:15 PM Rick Chen wrote:
> >
> > Bin Meng 於 2018年11月30日 週五 下午2:57寫道：
> > >
> > > Hi Rick,
> > >
> > > On Fri, Nov 30, 2018 at 2:41 PM Rick Chen
> > From: Anup Patel [mailto:a...@brainfault.org]
> > Sent: Monday, December 03, 2018 6:30 PM
> > To: Bin Meng
> > Cc: Rick Jian-Zhi Chen(陳建志); Lukas Auer; Alexander Graf; Palmer Dabbelt;
> > Atish Patra; Christoph Hellwig; U-Boot Mailing List
> > Subject: Re: [PATCH v7 4/4] RISC-V: Add S-mode time
Bin Meng 於 2018年12月4日 週二 下午5:36寫道：
>
> Hi Anup,
>
> On Tue, Dec 4, 2018 at 4:37 PM Anup Patel wrote:
> >
> > On Tue, Dec 4, 2018 at 1:44 PM Bin Meng wrote:
> > >
> > > Hi Rick,
> > >
> > > On Tue, Dec 4, 2018 at 3:12 PM Rick
4:16 +0800)
Anup Patel (3):
riscv: Add kconfig option to run U-Boot in S-mode
riscv: qemu: Use different SYS_TEXT_BASE for S-mode
riscv: Add S-mode defconfigs for QEMU virt machine
Rick Chen (1):
riscv: ax25-a
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