> > > > Currently, the RISC-V U-Boot is saving a2 register at > > > > CONFIG_SYS_DRAM_BASE in start.S which does not make sense because > > > > there is no information passed by previous booting stage in a2 > > > > register. > > > > > > > > This patch removes redundant a2 store on DRAM base. > > > > > > > > Signed-off-by: Anup Patel <a...@brainfault.org> > > > > --- > > > > arch/riscv/cpu/start.S | 2 -- > > > > 1 file changed, 2 deletions(-) > > > > > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index > > > > 704190f946..e4276e8e19 100644 > > > > --- a/arch/riscv/cpu/start.S > > > > +++ b/arch/riscv/cpu/start.S > > > > @@ -38,8 +38,6 @@ _start: > > > > mv s0, a0 > > > > mv s1, a1 > > > > > > > > - li t0, CONFIG_SYS_SDRAM_BASE > > > > - SREG a2, 0(t0) > > > > la t0, trap_entry > > > > #ifdef CONFIG_RISCV_SMODE > > > > csrw stvec, t0 > > > > -- > > > > > > This is weird. I remember these two lines were already removed by > > > Lukas's patch series before? Did not have time to dig out the history > > > though. > > >
> > > Regards, > > > Bin > > > > You are correct, however I removed it again, because I did not want to break > > Rick's board. He did add a commit to the last pull request that removes > > these > > two lines and adjusts his board accordingly, but it is not in the current > > one. > > Hi Likas Thanks for your explanation. RIck's commit as below https://www.mail-archive.com/u-boot@lists.denx.de/msg305880.html B.R Rick > > Thanks, > > Lukas _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
