> From: Kautuk Consul <kcon...@ventanamicro.com>
> Sent: Friday, September 23, 2022 3:03 PM
> To: Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com>; Sean Anderson 
> <sean.ander...@seco.com>; Rick Jian-Zhi Chen(陳建志) <r...@andestech.com>; Leo 
> Yu-Chi Liang(梁育齊) <ycli...@andestech.com>; Bin Meng <bmeng...@gmail.com>; 
> Simon Glass <s...@chromium.org>; Ilias Apalodimas 
> <ilias.apalodi...@linaro.org>; Alexandru Gagniuc <mr.nuke...@gmail.com>; 
> Philippe Reynes <philippe.rey...@softathome.com>; Heinrich Schuchardt 
> <xypron.g...@gmx.de>; Rasmus Villemoes <rasmus.villem...@prevas.dk>; Eugen 
> Hristev <eugen.hris...@microchip.com>; Stefan Roese <s...@denx.de>; Loic 
> Poulain <loic.poul...@linaro.org>; Peng Fan <peng....@nxp.com>; Michal Simek 
> <michal.si...@amd.com>
> Cc: u-boot@lists.denx.de; Kautuk Consul <kcon...@ventanamicro.com>; Anup 
> Patel <apa...@ventanamicro.com>
> Subject: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
>
> We add RISC-V semihosting based serial console for JTAG based early debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> Signed-off-by: Anup Patel <apa...@ventanamicro.com>
> Signed-off-by: Kautuk Consul <kcon...@ventanamicro.com>
> ---
>  arch/riscv/include/asm/spl.h |  1 +
>  arch/riscv/lib/Makefile      |  2 ++
>  arch/riscv/lib/interrupts.c  | 25 +++++++++++++++++++++++++  
> arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++
>  lib/Kconfig                  | 10 +++++-----
>  5 files changed, 57 insertions(+), 5 deletions(-)  create mode 100644 
> arch/riscv/lib/semihosting.c

Reviewed-by: Rick Chen <r...@andestech.com>

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